8 Commits

Author	SHA1	Message	Date
Grissiom	939c58c295	rm48x50: remove unused vPortTaskUsesFPU	2013-05-30 17:39:32 +08:00
Grissiom	4d40978a70	rm48x50: add finsh support	2013-05-29 23:39:09 +08:00
Grissiom	50c8cbe1d5	rm48x50: now it has console	2013-05-29 17:26:34 +08:00
Grissiom	435f305fa2	rm48x50: temperately disable the VFP register test	2013-05-26 22:15:26 +08:00
Grissiom	56b640ecb6	rm48x50: add vRegTestTask2	2013-05-26 22:14:24 +08:00
Grissiom	2805d315bd	rm48x50: fix bug in reg_test from FreeRTOS ... It does not satisfy AAPCS.	2013-05-26 21:49:26 +08:00
Grissiom	85ec844de9	rm48x50: add reg_test from FreeRTOS ... The code is GPLv2 so I think we could use it for free(both free beer and free speech).	2013-05-26 21:16:14 +08:00
Grissiom	f51bce3fed	add rm48x50 bsp and libcpu ... We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.	2013-05-24 22:55:13 +08:00