7c425408b4
[license] Change the license of libarm to Apache.
2018-10-15 01:35:07 +08:00
1253a1b445
Merge pull request #1812 from liruncong/am335x-mmu
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修正am335x中mmu问题
2018-10-10 08:49:18 +08:00
d96027f156
[libcpu] Fix the FPU definition in M4/M7 for ARM Clang
2018-09-25 11:08:58 +08:00
ff08faf605
[Kernel] Adjust the copyright information
2018-09-25 11:06:07 +08:00
b98a0ba804
[Kernel] Add ARMCC 6.x support.
2018-09-23 12:08:44 +08:00
af1044955a
修正am335x中mmu问题
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1) mmu_disable_dcache/mmu_enable_dcache等, 应使用rt_cpu_xxx相关函数,否则会跑飞. armcc并没有提供rt_cpu_xxx对应汇编代码,先删除
2) mmu_setmtt抽取为函数mmu_setmtts,并增加RT_WEAK.mmu_setmtts此处作为示例函数.实际用户板子可在bsp中重新实现该函数.可在rt_components_board_init函数前调用rt_hw_mmu_init
2018-09-15 11:37:14 +08:00
6d16685011
rt_hw_backtrace中多余括号删除. armclang给出警告
2018-09-10 19:58:28 +08:00
b46e7f3172
add rt_hw_cpu_reset for cortex-m cpu
2018-08-01 11:57:56 +08:00
d431f4b5f9
[libcpu][comtex-m7] enhancement hard fault exception handler.
2018-07-25 21:39:45 +08:00
6c39b2d54d
[libcpu][comtex-m4] enhancement hard fault exception handler.
2018-07-25 21:39:44 +08:00
a0fe71f78f
fixed get sp in HardFault_Handler. close #1646
2018-07-25 21:39:43 +08:00
944b0f1c94
fix annotation error
2018-06-13 15:04:31 +08:00
7a1f8ee1c4
[libcpu][arm][arm926] Using C header file to define stack and heap size.
2018-06-04 13:34:45 +08:00
dd1041bb7f
[libcpu]: fixed #1196 FPU FPCA issue.
2018-01-31 18:54:11 +08:00
fc7a5abc76
[libcpu]: add 8-byte alignment for arm architecture && optimize code format
2017-12-21 16:37:38 +08:00
336207ad31
[libcpu]: add 8-byte alignment for armv6 architecture
2017-12-21 15:35:48 +08:00
a4a85a28da
[libcpu]:optimize code format
2017-12-21 15:14:23 +08:00
e7b1786759
[libcpu]:optimize code format
2017-12-21 14:55:34 +08:00
15715692d2
[libcpu]: add 8-byte alignment for armv6 architecture
2017-12-21 10:13:47 +08:00
eb72d19179
[libcpu] add volatile for __asm.
2017-11-22 09:54:36 +08:00
2488624a18
[libcpu] add volatile for asm (" mcr ") or asm (" mrc ") instruct.
2017-11-22 09:54:27 +08:00
f6170a6e5b
[BSP] add i.MX 6UL BSP
2017-11-01 13:30:17 +08:00
6085f6826d
[bsp][at91sam9260] Fix the problem of the finsh function failure by using component initialization.
2017-10-19 23:46:17 +08:00
5e3b3b19a6
[BSP] change the type of cmd.
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1. Change the type of cmd to 'int';
2. Remove RT_LWIP_USING_RT_MEM macro;
2017-10-16 13:23:03 +08:00
cb247e913f
update libcpu: cortex-m0 fault handlers always enable.
2017-09-01 10:22:55 +08:00
9bbc4e5e6b
update cortex-m libcpu: fixed compile error.
2017-08-23 16:13:51 +08:00
9b7303e511
update libcpu: ensure fault enable.
2017-08-18 11:12:58 +08:00
a74a2a25a8
Add libcpu/arm/am335x/context_iar.S file
2017-02-06 21:57:15 +08:00
4e95fdff4a
[BSP] Update VFP code in armv6.
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committed by FH.
2016-05-20 14:20:34 +08:00
923594c7ab
[BSP] Enable VFP.
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committed by FH.
2016-05-20 12:24:51 +08:00
43f68131ce
[BSP] Add fh8620 bsp from Shanghai Fullhan Microelectronics Co., Ltd.
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FH8620 BSP
Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
All rights reserved
2016-04-18 13:52:39 +08:00
3983f39f34
Add iar compiler support for am335x.
2015-11-11 23:44:05 +08:00
3faca6d5df
[BSP] update stm32f7-disco
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code cleanup.
2015-09-24 16:03:09 +08:00
2021f5a276
Add the license.
2015-09-04 21:58:08 +08:00
b71cb4c09d
Add dm365 porting.
2015-09-04 12:30:20 +08:00
af8a91457e
[bsp]add the stm32f74x bsp.
2015-08-07 13:30:13 +08:00
9fe3cbf76f
Align thread stack to 8 byte.
2015-06-05 19:14:08 +08:00
314379cc77
implement __user_initial_stackheap
2015-06-04 12:23:24 +08:00
be76b10be6
Align stack address to 8 byte.
2015-06-04 11:59:18 +08:00
1fa5711712
fixed assembly warnings.
2015-05-22 16:48:01 +08:00
73df162d3f
fixed assembly warnings.
2015-05-13 11:57:34 +08:00
4222677933
[libcpu][am335x] Fix the booting failure when enabling MMU
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Since the 16 domains are configured as the client domains in
mmu_setttbase(), a Permission fault is generated if the XN bit
(Execute-never) is set in the short-descriptor translation table
(for section and supersection). This leads to the booting failure
when enabling MMU for beagleboard bsp. Here is log:
----------------------------------------------------------------
SD/MMC found on device 0
reading uEnv.txt
117 bytes read in 3 ms (38.1 KiB/s)
Loaded environment from uEnv.txt
Importing environment from mmc ...
Running uenvcmd ...
reading rtthread.bin
162624 bytes read in 24 ms (6.5 MiB/s)
\## Starting application at 0x80200000 ...
----------------------------------------------------------------
This commit removes the XN bit configuration in the section of the
short-descriptor translation table. The OS can be booted successfully
with applying this commit.
2015-05-11 10:36:11 +08:00
a13132b302
[libcpu][arm926] Optimize irq trap code.
2015-05-04 16:13:43 +08:00
49fa5c44d7
[libcpu][arm926] Optimize code
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1. Combine code for IAR and GCC in file mmu.c and cpuport.c
2. Remove remap code in start_xxx.S. User should config MMU to map vector table to visual address 0x0
2015-04-22 11:19:50 +08:00
175e357ace
[libcpu][arm926] Remove unused SPSR register PUSH/POP when os switch thread.
2015-04-16 14:13:43 +08:00
cf3d639fcb
[libcpu][arm926] Define vector table start at BSP/{board}/platform/ assemble INC files.
2015-04-16 10:35:12 +08:00
6aa242645f
1. [bsp][sam9260] Fix the bug that auto reset after boot 20s. Disable watchdog in rt_lovel_level_init function.
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2. [bsp][sam9260] Modify SCONS scripts to support IAR tool chain.
3. [bsp][sam9260] Move link strips in to folder link_scripts.
4. [libcpu][arm926] Add copy right to source file and format code.
2015-04-15 16:13:30 +08:00
39452b67b0
1. [cpu] split ARM926 cpu code from AT91SAM9260 BSP
2015-04-14 21:56:34 +08:00
0b5958d700
Fix compile warning:
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..\..\libcpu\arm\cortex-m3\context_rvds.S(207):
warning: A1581W: Added 2 bytes of padding at address 0xd6
2015-03-09 09:31:23 +08:00
62af08370b
Merge pull request #2 from RT-Thread/master
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sync
2014-09-20 01:19:42 +08:00
267c61ebce
[libcpu] Add builtin ffs implementation for Cortex-M4.
2014-09-11 12:51:33 +08:00
fd6ef4b235
[libcpu]am335x edit vector
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vector_undef and vector_dabt
2014-08-12 18:26:22 +08:00
2c47f2e683
Fix some spell error;
2014-07-31 13:59:25 +08:00
97fb91dcc6
bsp: add zynq7000
2014-06-27 14:12:36 +08:00
2b7be29cad
[bsp/rva8] enable group{0,1} interrupt forwarding in gic initialization
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When RT-Thread is running stand alone, it forgot to enable the
distributor of GIC.
2014-04-08 11:54:03 +08:00
c0f0c2322f
[libcpu/arm] remove useless cpsr updating in rt_hw_context_switch_to
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This piece of code will enable the interrupt early before switching to
the first thread. Although it is harmless, but not prefect.
2014-04-08 11:24:04 +08:00
28f11fdd7b
[vmm] add realview-pb-a8 VMM support
2014-04-03 17:59:14 +08:00
9382a7105f
add CM_PER_UARTx_CLKCTRL
2014-01-11 15:14:36 +08:00
0c9b9ced31
cortex-r4: use byte to allocate the stack
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Unit of "byte" is more intuitive than "long".
2013-11-17 12:49:08 +08:00
a8520ed383
cortex-r4: let svc mode reuse the stack of IRQ on startup
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As the svc stack is the stack of threads, there is no need to allocate a
separate stack for the startup. Reuse the IRQ stack should be OK.
Tested on rm48 board.
2013-11-17 12:49:07 +08:00
06987e72e5
Fix hardfault bug for gcc port
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for 2013-02-20 aozima commmit "port for gcc", but the commit is
not tested,and the kernel is breakdown in context_gcc.S, the file
is a copy from cortex-m3,but not port for cortex-m0, so i complete
this port for aozima, test it in stm32f0discovery board ,
and it works fine.
2013-11-04 16:10:11 +08:00
377c6e6cc9
cortex-r4: dump register on traps
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We could not handle any traps except IRQ/FIQ.
2013-10-20 23:46:50 +08:00
e1e563e85c
cortex-r4: remove RM48x50.h and add armv7.h
2013-10-20 21:10:26 +08:00
81ab083ae5
rm48: move some asm file to libcpu
2013-10-20 18:51:46 +08:00
9568669109
rm48x50: add GCC support
2013-10-20 18:51:45 +08:00
7bdb082c91
Delete SConscript
2013-09-22 06:59:52 +08:00
9d09cd9f23
Import beaglebone porting
2013-09-20 21:20:51 +08:00
37ac4855da
Embedded GPLv2 license.
2013-07-21 20:01:24 +08:00
36c4604a36
fix compiling error
2013-07-21 19:39:21 +08:00
42f9840653
commit again
2013-07-21 17:32:55 +08:00
3bdbf640b7
update at91sam9260 project directory structure.
2013-07-21 17:19:30 +08:00
885301bb14
update AT91SAM9260 usart driver， using serial driver component.
2013-07-21 15:01:42 +08:00
ce4f0329db
enhancement hard fault exception handler.
2013-07-09 22:02:12 +08:00
5120f54a29
fix spelling error.
2013-06-24 22:57:27 +08:00
34d59ccb0f
update libcpu/arm/cortex-m4: support lazy stack optimized.
2013-06-23 18:10:46 +08:00
b045f93b47
fixed bug: correct cortex-m SCB->VTOR address.
2013-06-23 18:08:16 +08:00
93b9b28297
format code by Astyle.
2013-06-23 18:07:10 +08:00
a2ff85c03f
update libcpu/arm/cortex-m0: restore MSP.
2013-06-22 18:59:51 +08:00
4d421cad73
update libcpu/arm/cortex-m3: restore MSP.
2013-06-22 18:59:50 +08:00
f9e673354a
update libcpu/arm/cortex-m4: restore MSP.
2013-06-22 18:59:49 +08:00
3071e35c54
Merge pull request #109 from grissiom/rm48x50
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Rm48x50
2013-06-19 01:29:12 -07:00
c986754c49
Signed-off-by: visitor83 <wolflouiswang@gmail.com>
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format the s3c24x0 serial.c and mini2440 rtconfig.py
2013-06-18 12:51:55 +08:00
c56fa7c907
ident format
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Signed-off-by: visitor83 <root@wolflouis.(none)>
2013-06-16 10:00:34 +08:00
009239ceed
rm48x50: rt_interrupt_nest should be `volatile rt_uint8_t`
2013-06-12 23:56:10 +08:00
9b949c28b7
rm48x50: add cache_{enable, disable}
2013-06-12 21:03:04 +08:00
e8bbbe6788
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-06-05 23:21:06 +08:00
228a6be077
cortex-r4: add __rt_ffs
2013-06-05 23:20:39 +08:00
e74befca44
move libcpu/arm/rm48x50/ to libcpu/arm/cortex-r4
2013-05-31 21:06:26 +08:00
24fc6e6ebb
rm48x50: VFP lazy stacking
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You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT
will turn on VFP for all threads and stack all the VFP registers. When
doing lazy stacking, VFP will only be turned on for the thread who
issued VFP instructions.
Currently, if a thread turned on VFP, it cannot be turned off. RTT will
never know what time the thread doesn't need VFP any more. The thread
might could turn off the VFP for it self in proper time.
2013-05-31 20:58:08 +08:00
8bbfd45ce3
rm48x50: change STMFD/LDMFD to STMDB/LDMIA
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VFP instructions only have IA(Increment After)/DB(Decrement Before)
mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
ec1203bfab
rm48x50: turn on VFP support
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This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
83ea4dd628
rm48x50: small cleanup on context_ccs.asm
2013-05-30 17:37:50 +08:00
810311b624
rm48x50: fix bug in rt_hw_interrupt_{mask,unmask}
2013-05-29 23:36:32 +08:00
f08df08897
rm48x50: optimize a BEQ
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Use condition flag in the ORR. This could eliminate a BEQ.
2013-05-26 23:37:56 +08:00
19fe6251e7
rm48x50: optimize context_switch_interrupt_to by reuse registers
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When saving thread registers in context_switch_interrupt_to, we don't
change them, just move them. So there is no need to always r0-r3 from
stack to the real r0-r3. So just use the intermediate registers and
eliminate 2 MOV.
2013-05-26 22:37:49 +08:00
3d0647efb3
rm48x50: optimize context_switch_interrupt_do
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Substitude STMFD, MOV, ADD with STMFD, SUB. It reduce one instruction.
Tested on board and it works like a charm.
2013-05-26 17:22:36 +08:00
b39d038cf0
rm48x50: utilize CPS instruction and remove some useless code
2013-05-26 16:55:39 +08:00
f51bce3fed
add rm48x50 bsp and libcpu
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We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
2013-05-24 22:55:13 +08:00
db548a1b37
fixed compiling error related to the RT_USING_INTERRUPT_INFO in mini4020
2013-04-10 00:49:18 +08:00
d9d39a8d21
Use SRAM as EMAC transmit buffer, to avoid the underrun error, especially in the large amount of data communication.
2013-04-08 21:57:24 +08:00
Bernard Xiong
liruncong
hichard_ren@yeah.net
aozima
=
ArdaFu
SummerGift
weety
bernard
zchong-cht
nongxiaoming
Adrian Huang
Bright Pan
陈豪
Grissiom
RTsien
Bright Pan
visitor83
visitor83
yiyue.fang