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403 Commits

Author SHA1 Message Date
aozima dd1041bb7f [libcpu]: fixed #1196 FPU FPCA issue. 2018-01-31 18:54:11 +08:00
Bernard Xiong d78f5eb674
Merge pull request #1124 from SummerGGift/add_arm_8-byte_alignment 
[libcpu]: add 8-byte alignment for arm architecture && optimize code …
 2017-12-21 17:07:34 +08:00
SummerGift fc7a5abc76 [libcpu]: add 8-byte alignment for arm architecture && optimize code format 2017-12-21 16:37:38 +08:00
Bernard Xiong cc75366fda
Merge pull request #1123 from SummerGGift/8-byte_alignment 
[libcpu]: add 8-byte alignment for armv6 architecture
 2017-12-21 15:36:21 +08:00
SummerGift 336207ad31 [libcpu]: add 8-byte alignment for armv6 architecture 2017-12-21 15:35:48 +08:00
SummerGift a4a85a28da [libcpu]:optimize code format 2017-12-21 15:14:23 +08:00
SummerGift e7b1786759 [libcpu]:optimize code format 2017-12-21 14:55:34 +08:00
SummerGift 15715692d2 [libcpu]: add 8-byte alignment for armv6 architecture 2017-12-21 10:13:47 +08:00
Bernard Xiong bb46058d8e [libcpu] Add ARCH_ARM_ARM9/11 type 2017-12-19 17:39:23 +08:00
SummerGift eb72d19179 [libcpu] add volatile for __asm. 2017-11-22 09:54:36 +08:00
SummerGift 2488624a18 [libcpu] add volatile for asm (" mcr ") or asm (" mrc ") instruct. 2017-11-22 09:54:27 +08:00
tangyuxin afc2256d01 [libcpu]Support x1000 CPU 2017-11-10 19:50:14 +08:00
Bernard Xiong f6170a6e5b [BSP] add i.MX 6UL BSP 2017-11-01 13:30:17 +08:00
bernard 756bfcc5e2 Update Kconfig. 
1. Add IPADDR/GWADDR etc;
2. Add Kconfig for libcpu.
 2017-10-31 09:54:23 +08:00
weety 6085f6826d [bsp][at91sam9260] Fix the problem of the finsh function failure by using component initialization. 2017-10-19 23:46:17 +08:00
bernard 5e3b3b19a6 [BSP] change the type of cmd. 
1. Change the type of cmd to 'int';
2. Remove RT_LWIP_USING_RT_MEM macro;
 2017-10-16 13:23:03 +08:00
bernard f8a1bf6fd8 [libcpu] code cleanup for nds32. 2017-10-09 18:06:58 +08:00
Bernard Xiong c2f028ed8d Update cpuport.c 2017-10-06 11:43:50 +08:00
Bernard Xiong ea18ef60ed Merge pull request #826 from ArcherChang/master 
[BSP] Add Andes N1068 porting and simple bsp.
 2017-10-06 11:03:02 +08:00
Bernard Xiong 0d193254f8 Merge pull request #845 from caogos/master 
[BSP] Add FPU option for loongson1c.
 2017-09-14 17:06:11 +08:00
勤为本 574e22bdbd 在配置文件“rtconfig.h”中增加硬浮点FPU的配置项， 
浮点经常会用到，所以默认使用硬浮点。
 2017-09-13 15:21:09 +08:00
aozima cb247e913f update libcpu: cortex-m0 fault handlers always enable. 2017-09-01 10:22:55 +08:00
Bernard Xiong 2ac493698b [BSP] cleanup for hifive1 bsp. 2017-08-26 11:02:39 +08:00
ArcherChang 652ea85a39 [1] Andes N1068体系移植 
a. Libc改用官方版本（工具链附带版本）；
    b. 去除未使用文件；
 2017-08-25 14:25:35 +08:00
Bernard Xiong b9ebd183ae Merge pull request #827 from caogos/master 
[BSP] Add EMAC driver in loongson1C (ported by chinesebear, https://github.com/chinesebear/rtt-net)
 2017-08-25 11:07:34 +08:00
ArcherChang 921fbfbc21 [1] 添加Andes N1068体系； 
[2] 基于AE210P EVB板；
[3] 详细信息参阅bsp/AE210P/readme文件夹；
    《Andes工程创建和调试》文档；等。
 2017-08-25 10:25:33 +08:00
aozima 9bbc4e5e6b update cortex-m libcpu: fixed compile error. 2017-08-23 16:13:51 +08:00
勤为本 838c63f365 添加龙芯1C片内网卡的驱动（原创作者是chinesebear，https://github.com/chinesebear/rtt-net） 2017-08-23 15:46:51 +08:00
aozima 9b7303e511 update libcpu: ensure fault enable. 2017-08-18 11:12:58 +08:00
Bernard Xiong 4626b19ead Merge pull request #784 from zhangjun1996/master 
[BSP] add bsp for sifive(risc-v e310).
 2017-08-10 16:51:59 +08:00
勤为本 7129d77bee 增加龙芯1c硬浮点的支持（可以使用硬浮点了） 2017-08-10 15:35:03 +08:00
zhangjun 72cfe9dd68 modify： drivers/cpuusage.c 
modify：     ../../libcpu/risc-v/e310/stack.c
	rmove unused macro definition
modify：     ../../src/idle.c
	Return to the original version
 2017-07-31 12:05:45 +08:00
zhangjun 0cd49e7c4a Merge branch 'master' of https://github.com/RT-Thread/rt-thread 
add new bsp for risc-v
 2017-07-31 11:27:46 +08:00
zhangjun e9f1bdf2da new file： ../../libcpu/risc-v/e310/trap.c 
add file that forget to submit before
	auto change timer mtimercmp register on the base of RT_TICK_PER_SECOND in rtconfig.h
	no flashing led
new file：   ../../src/idle.c
	recover old file
 2017-07-31 11:12:28 +08:00
zhangjun a5305c05df fix bug in context_gcc.s and start_gcc.s: 
save mie into stack
msh  running normaly
 2017-07-31 10:59:59 +08:00
zhangjun b032dff161 fix bug in rt_hw_context_switch_interrupt_do 
save sp to old thread
	clear rt_thread_switch_interrupt_flag
always enable interrupt after rt_hw_context_switch
judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt)
 2017-07-30 19:46:28 +08:00
zhangjun 2d56a27c20 修改： ../../libcpu/risc-v/e310/context_gcc.S 
enable interrupt after return form rt_hw_context_switch
 2017-07-30 15:34:32 +08:00
zhangjun 3c51848d33 fix trap_entry 2017-07-29 15:37:20 +08:00
zhangjun b80f83f360 modified: ../../libcpu/risc-v/e310/context_gcc.S 
fix open timer intrrupt
 2017-07-26 16:27:54 +08:00
zhangjun 98a6896cfa remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable(); 
it will lead to interrupt again in interrupt
 2017-07-26 16:07:01 +08:00
勤为本 358612c8a2 支持GPIO中断（外部中断） 2017-07-20 17:35:03 +08:00
勤为本 d1bb7c61f4 将支持的中断个数从32个扩展到160个，至此可以支持所有中断 2017-07-20 17:05:59 +08:00
勤为本 f39164203e 修正龙芯1c的中断号 2017-07-18 17:04:32 +08:00
zhangjun b334347a24 deleted: rtthread.s /*just for debug*/ 
modified:   ../../libcpu/risc-v/e310/context_gcc.S
	change  ret to mret and switch to new task with mepc
 2017-07-17 16:55:33 +08:00
zhangjun e01455155a add context_gcc.s 2017-07-17 15:44:00 +08:00
zchong-cht a74a2a25a8 Add libcpu/arm/am335x/context_iar.S file 2017-02-06 21:57:15 +08:00
kontais b96f07e477 flush cache after exception code install 2016-06-15 08:09:56 -07:00
Bernard Xiong 4e95fdff4a [BSP] Update VFP code in armv6. 
committed by FH.
 2016-05-20 14:20:34 +08:00
Bernard Xiong 923594c7ab [BSP] Enable VFP. 
committed by FH.
 2016-05-20 12:24:51 +08:00
Bernard Xiong 255f8b7c34 [BSP] Add BSP for Ingenic X1000 CPU 2016-04-24 19:34:41 +08:00