Commit Graph

35 Commits

Author SHA1 Message Date
Chen Wang 83a250f05f
bsp: qemu-virt64-riscv: Improve README (#9651)
Improved README document
- Unified the usage process of Standard Edition and Smart Edition.
- Deleted the description of running RTT in Machine Mode. Currently,
  both Standard Edition and Smart Edition RTT run in S-mode by default.

At the same time, some unnecessary scripts were cleaned up.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-11-14 22:09:23 +08:00
Shell 7528645f59 feat: libcpu/risc-v: unify context on c906, virt64
Changes:
- added config for NEW_CTX_SWITCH
- used new context on c906 sched switch routine
- update _rt_hw_stack_init to fit into NEW_CTX_SWITCH
- separated vector ctx from the generic

Signed-off-by: Shell <smokewood@qq.com>
2024-09-11 18:06:51 -04:00
Shell adbbd24ad7 feat: bsp: qemu risc-v64: fit into common64 2024-09-11 18:06:51 -04:00
Shell b6f1b16d7a feat: bsp: qemu-riscv64: using klibc API for printf 2024-09-01 15:12:34 -04:00
Shell a5042f5bb5 feat: bsp: qemu-riscv64: updates of building & docs
- using generic command instead of abs path
- update BSP configurations
- update README
2024-09-01 15:12:34 -04:00
Shell 1c5340ce3a feat: bsp: qemu-riscv64: remove useless configs 2024-09-01 15:12:34 -04:00
MuChenger 0efc408a00 adapt to rv64ilp32 toolchain 2024-07-18 15:59:40 +08:00
Shell 65ffe4e13e [libcpu/rv64] feat: unify tick.c
The changes unify the tick.c implementations for all risc-v64
architectures, leveraging the CPUTIME feature. This refactoring was
necessary to streamline the codebase, and ensure consistent timer
handling across different platforms.

Changes:
- Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues.
- Updated .config for BSPs to update `CPUTIME_TIMER_FREQ`
- Updated header of for API `riscv_cputime_init`
- Initialized riscv timer on `rt_hw_tick_init`
- Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`:
  - Replaced direct use of `rdtime` with `clock_cpu_gettime`.
  - Removed redundant timer frequency definitions.
  - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`.
  - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`.
  - Integrated `ktime` support for tick initialization.

Signed-off-by: Shell <smokewood@qq.com>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-15 12:06:39 +08:00
latercomer fe3c4d456e bsp中option env语句替换为新语句,并同步更新了source "$xxx"语句 2024-06-20 14:40:42 +08:00
Shell 65c9947225
[libcpu] rv64: support for ARCH_REMAP_KERNEL (#9067)
* [libcpu] support for ARCH_REMAP_KERNEL

These changes introduce support for the ARCH_REMAP_KERNEL configuration,
which isolates kernel space in high virtual address regions. This feature
is necessary to enhance memory protection and management by segregating
user and kernel spaces more effectively.

Changes:
- Updated conditional macros to check for ARCH_REMAP_KERNEL instead of
  ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new
  configuration option.
- Modified qemu-virt64-riscv Kconfig and SConstruct files to include and
  utilize ARCH_REMAP_KERNEL.
- Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv.
- Updated rtconfig.py to use a more flexible execution path setup.
- Enhanced user address space definitions in `lwp_arch.h` to support the
  new virtual address mappings.
- Adjusted kernel memory initialization and mapping logic in `c906/mmu.c`
  and `virt64/mmu.c` to account for high virtual address regions.
- Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures.
- Enhanced memory setup functions to support new mapping scheme, including
  updates to early page table setup and address relocation logic.

These modifications ensure that the system can utilize high memory
addresses for the kernel, improving memory isolation and system stability.

Signed-off-by: Shell <smokewood@qq.com>

* fixup: CI run failed

* bsp: default config without using smart

* fixup: static checks

* restore rt_hw_mmu_kernel_map_init for D1

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-06-18 11:15:59 +08:00
heyuanjie87 f778a66d6e
[bsp/qemu-riscv]修正打开串口后中断被关闭的问题 (#9035) 2024-06-05 09:52:32 +08:00
Meco Man 3f26998f9c [bsp] update projects 2024-03-21 11:23:29 +08:00
Yuqiang Wang c6bdee3c50
[ci] open ci check with function declaration warning (#8546) 2024-02-20 22:45:04 -05:00
Shell 70a8d1d465
[kservice] improve backtrace service in kernel (#8144)
Signed-off-by: Shell <smokewood@qq.com>
2023-10-21 20:14:45 +08:00
guozhanxin 9e79333512 [project] update mdk/iar project and config. 2023-10-08 11:21:00 +08:00
zhkag 29a508222c 修复 qemu 挂载 elm 文件系统失败 2023-09-26 13:23:48 +08:00
xqyjlj 0eb75ced70
[time]时钟框架重构 (#7794) 2023-07-17 20:11:58 +08:00
wusongjie 8aa4366cb2 Drivers: Support Open Firmware API and model of PIC
We support OFW API to replace fdt old API, and add
IRQ, IO, Platform-Bus, CPUs ... OFW node contorl.
To support work with Device Tree or ACPI in drivers
that use IRQ, we make a programmable interrupt
controller driver's model.

Signed-off-by: GuEe-GUI <GuEe-GUI@github.com>
2023-07-05 16:45:16 +08:00
yangjie11 95e6b69b8e
sync and update all projects (#7138)
* sync and update
2023-03-31 16:49:48 +08:00
Yaochenger de4f237482
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053)
* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构

* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
  * 1.规范代码风格
  * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试

---------

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
Shell 2d09749086
[rt-smart] PV_OFFSET as a variable (#6904)
* [rt-smart/mem] remove pv_offset

* [rt-smart] list kernel space command

* [rt-smart] restore ioremap region

* [revert] restore kernel space isolation

* [rt-smart/pv_off] code format

* [rt-smart] add get_pvoff()

* [pvoffset] pvoff as constant for C codes

* [pvoff] pvoff as interfaces
2023-02-14 23:08:32 +08:00
Bernard Xiong e4edf7e182
[BSP] Add color build for qemu gcc config. (#6924) 2023-02-11 17:14:55 +08:00
Bernard Xiong 98e0c58527
Add ADT Kconfig and fix MMU kconfig issue in Cortex-A (#6901)
* Add ADT Kconfig and fix MMU kconfig issue in Cortex-A

* [BSP] enable ADT
2023-02-06 01:11:04 +08:00
Shell f0dadcb3c3
[rt-smart] porting c906 and D1s to mm (#6848)
* [rv64/bsp] porting to mm

* [mm] report more info for debugging

* [fix] code format

* [libcpu/c906] porting to RTOS

* [fix] using rtdbg api

* [fix] add return

* [fix] report more information for debugging

* [fix] use assert 0 for unrecoverable error
2023-01-16 08:24:03 +08:00
Meco Man 592284c66c format link scripts 2023-01-08 22:52:13 -05:00
Meco Man 9bc68d26a4 format Kconfig and sconscript 2023-01-08 22:52:13 -05:00
Shell 7450ef6c4d
[rt-smart] kernel virtual memory management layer (#6809)
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes
2023-01-08 21:08:55 -05:00
guo 68ca9f07a6
[rt-smart] 弱化 RT_USING_LWP,使用 RT_USING_SMART 作为宏配置 (#6740)
* [dfs] sync cromfs

* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration

* [format] fix some format issue.
2022-12-16 18:38:28 +08:00
Man, Jianting (Meco) 99bdf978d7
[rtdef] use lower-case to define attributes (#6728)
* [rtdef] rename RT_WEAK attribute as rt_weak

* [rtdef] rename RT_USED attribute as rt_used

* [rtdef] rename RT_SECTION attribute as rt_section

* [rtdef] rename ALIGN attribute as rt_align

* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support
2022-12-11 13:12:03 -05:00
Shell e991be9c51
[smart][risc-v/libcpu] port rv64 cpu code (#6704)
* [risc-v/libcpu] porting Smart & RTOS
* [fix] rv64 plic
* [risc-v/rv64] remove macro in rtdef
2022-12-10 22:16:42 +08:00
guo ecf2d82159
sync branch rt-smart. (#6641)
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
Meco Man 8b0610fc34 [bsp][readme] 增加scons --exec-path=xxx 命令的使用说明 2022-10-10 09:42:44 +08:00
liuxianliang a4eb64b873 update the project for RT-Thread_V4.1.1 2022-08-16 19:38:48 +08:00
rewine 53ed031498 [bsp/qemu-virt64-riscv]: dont use sbi in m-mode 2022-06-13 21:26:49 +08:00
rewine 9ebe0f3b47 [bsp] rename qemu-riscv-virt64 to qemu-virt64-riscv 2022-05-25 10:05:23 +08:00