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Author SHA1 Message Date
Yaochenger de4f237482
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053) 
* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构

* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
  * 1.规范代码风格
  * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试

---------

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
 2023-03-23 20:06:50 +08:00
Zxy 4ed9bc11f7
[errno code]fix that use RT_ENOSYS without - (#7084) 
* [errno code]fix that use RT_ENOSYS without -

* Update bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.c

---------

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
 2023-03-23 01:54:42 -04:00
flyingcys a538b26858
[bsp] add bl808 lp core (#7069) 
* Add riscv_32e support

* add bl808 lp core

* update README.md
 2023-03-19 23:16:12 +08:00
flyingcys c11f5bb251
add bl60x/bl70x/bl61x/bl808 (#7063) 
Co-authored-by: flyingcys <flyingcys!163.com>
 2023-03-19 14:41:18 +08:00
Shell 18a14cc935
[rt-smart] move sys_cacheflush to lwp_syscall.c (#7048) 
* [syscall] move sys_cacheflush to lwp_syscall.c

* [syscall] improve assertion

* [format] rename to rt_ctassert

* [debug] modified ct assertion on mm_page.c
 2023-03-17 15:11:38 +08:00
Shell 2394e75265
[libcpu/risc-v] support noncached normal memory (#7051) 
* [libcpu/risc-v] support noncached normal memory

* [mm] check before dereference in _fetch_page

* [mm] add comments on ioremap

* [ioremap] report more info on failed
 2023-03-16 10:26:55 +08:00
zilong 50e1f6327d
[libcpu/riscv/virt64] fix (#5979) (#7040) 2023-03-11 12:34:14 +08:00
chenhy0106 f6847af0cd
[libcpu/riscv/c906] fix "next_asid" type error (#7031) 
MAX_ASID最大为0x10000，在next_asid==MAX_ASID时进入下一个generation。因此next_asid不能只有16位，否则将不能进入下一个generation。修改rt_uint16_t为rt_uint32_t。
 2023-03-09 07:25:54 -05:00
Yaochenger cfc6bf9b12 [libcpu/risc-v]更新移植readme 2023-03-07 22:04:26 -05:00
Yaochenger 922e6e40d3
[libcpu/risc-v]迁移libcpu/risc-v/e310与rv32m1文件中内容至bsp (#7015) 2023-03-05 19:43:58 -05:00
Shell 0de21341f9
[fix] mm bugs (#7010) 
* [fix] implementation fault on avl

* [fix] mm may free varea allocated statically

* [test] add test and benchmark for avl
 2023-03-03 11:51:21 +08:00
Yaochenger 95540854a6
[libcpu/riscv]迁移libcpu/riscv/ch32中文件至bsp (#7004) 2023-03-02 09:17:43 -05:00
Yaochenger fc2e122ee2 [libcpu/risc-v]迁移libcpu/risc-v/hpmicro中的文件至bsp 2023-03-02 09:16:59 -05:00
Yaochenger 6aa2445522 [libcpu/risc-v]移除bumblebee文件夹与nuclei文件夹中的内容至bsp 2023-03-02 09:16:12 -05:00
Yaochenger 892ef3dc5b
[libcpu/risc-v]将cv32e40p文件夹中文件移至BSP (#7002) 2023-03-01 21:34:35 -05:00
Yaochenger b9e4fcfc68
[libcpu][riscv]整合libcpu/riscv中的移植文件 提供一份公共代码于common (#6941) 
整合libcpu/riscv中的移植文件 提供一份公共代码于common

在提交本pr时，除hpmicro的内核，rv32内核bsp已完成去除大部分的冗余，大部分代码采用common中的实现。本pr的作用是进一步统一common中的文件，从而提供一份公用代码，新移植的RV32内核的BSP可以全部使用common代码。

- 在common中提供一份公用文件：interrupt_gcc.S
- 修改原有的文件，将原有的中断中上下文切换代码替换为interrupt_gcc.S
- 基于上述修改，修改仓库中risc-v内核的BSP与移植相关的部分 (主要包含中断入口函数 中断栈等)
- 在common中提供一份公用文件：trap_common.c；提供统一中断入口函数，中断入口函数初始化，中断入口注册等函数，并完善异常时的信息输出

- 在common中提供一份公用文件：rt_hw_stack_frame.h；将栈帧结构体剥离，供用户使用

- 在上述工作完成后，在上述工作的基础上测试仓库中risc-v内核的BSP

- 完善函数中的命名，完善中断栈的获取

- 提供一份详细的基于现有common文件的移植指南

  #### 在什么测试环境下测试通过 

- 1.CH32V307V-R1-R0
- 2.CH32V208W-R0-1V4
- 3.HPM6750EVKMINI
- 4.GD32VF103V-EVAL
- 5.qemu(CORE-V-MCU )

> 与上述开发板使用同样芯片的BSP均测试通过

在CH32V307V-R1-R0与HPM6750EVKMINI上基于现有移植文件进行多线程复杂场景下的长时间测试，测试过程系统运行正常。
 2023-03-01 01:32:43 -05:00
Bernard Xiong f295d3df78
[libcpu.aarch64] add rt_backtrace function. (#6982) 
* [libcpu.aarch64] add rt_backtrace function.
 2023-02-27 10:04:10 +08:00
wangxiaoyao 12f0df9279 [libcpu/aarch64] stop when no page is free 2023-02-25 20:05:59 +08:00
Shell 382e9bcac7
[rt-smart] handling kernel from accessing unmapped user stack (#6957) 
[rt-smart] handling kernel from accessing unmapped user stack
 2023-02-24 14:52:16 +08:00
wangxiaoyao 1c2daeafdc [fix] typo 2023-02-21 08:48:49 +08:00
wangxiaoyao 26891e9117 [fix] pipeline 2023-02-21 08:48:49 +08:00
wangxiaoyao 484a0d602e [fixup] add cache maintenance ops; 
fix bugs on cache maintenance when starting user app
 2023-02-21 08:48:49 +08:00
Shell 2d09749086
[rt-smart] PV_OFFSET as a variable (#6904) 
* [rt-smart/mem] remove pv_offset

* [rt-smart] list kernel space command

* [rt-smart] restore ioremap region

* [revert] restore kernel space isolation

* [rt-smart/pv_off] code format

* [rt-smart] add get_pvoff()

* [pvoffset] pvoff as constant for C codes

* [pvoff] pvoff as interfaces
 2023-02-14 23:08:32 +08:00
Meco Man f58d3c5200 rt_device_write/read return data type as rt_ssize_t 
rt_ssize_t can give negative error code, which follows the unix style correctly
 2023-02-07 21:43:57 -05:00
wdfk-prog 7296117203 [cortex-m7]rt_hw_cpu_dcache_ops函数uint32_t替换为rt_uint32_t 2023-02-07 12:05:27 -05:00
Bernard Xiong 98e0c58527
Add ADT Kconfig and fix MMU kconfig issue in Cortex-A (#6901) 
* Add ADT Kconfig and fix MMU kconfig issue in Cortex-A

* [BSP] enable ADT
 2023-02-06 01:11:04 +08:00
chenhy0106 9db73a47c4
为c906添加asid支持 (#6870) 
* [rt-smart] asid for c906
 2023-01-28 13:08:40 -05:00
Shell f0dadcb3c3
[rt-smart] porting c906 and D1s to mm (#6848) 
* [rv64/bsp] porting to mm

* [mm] report more info for debugging

* [fix] code format

* [libcpu/c906] porting to RTOS

* [fix] using rtdbg api

* [fix] add return

* [fix] report more information for debugging

* [fix] use assert 0 for unrecoverable error
 2023-01-16 08:24:03 +08:00
Meco Man 9bc68d26a4 format Kconfig and sconscript 2023-01-08 22:52:13 -05:00
Shell 7450ef6c4d
[rt-smart] kernel virtual memory management layer (#6809) 
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes
 2023-01-08 21:08:55 -05:00
flyingcys 98a997c57e
[bsp]add new bsp-bl808 (#6824) 
* add new bsp-bl808

* support ARCH_RISCV_FPU_S && update rtconfig.py
 2023-01-07 02:03:21 -05:00
Yaochenger b99769f686
[libcpu][riscv]移除ch32中的冗余文件,使用common下的文件 (#6813) 
* [libcpu][riscv]移除ch32中的冗余文件,使用common下的文件

* 修正cpuport.h宏定义

* 规范宏定义格式
 2023-01-04 21:06:09 -05:00
Yaochenger f2a66e122f [libcpu][riscv]移除cv32e40p中部分文件，采用common中的文件 2023-01-02 16:42:18 -05:00
Yaochenger 882a0af94e [libcpu][riscv] 添加宏用于区别是否开启FPU，更新ch32v208v-r0 ->ch32v208w-r0，更新注释 2022-12-28 18:47:39 -05:00
Yaochenger b77241935c
[bsp][ch32v208]添加ch32v208BSP,合并libcpu/riscv 中ch系列的port文件 (#6780) 
【1】添加ch32v208-r0 bsp
【2】合并libcpu/riscv 下ch系列mcu的port文件
 2022-12-27 13:24:02 -05:00
bernard 1f092da9e0 fix compiling warning. 2022-12-26 14:24:26 +08:00
bernard 401ad16449 [bsp][smart] fix virt64 aarch64 link script for smart. 2022-12-26 14:24:26 +08:00
linshire c930b4f623
[ch32]对接了rt_hw_context_switch_interrupt接口 (#6749) 
* 对接了rt_hw_context_switch_interruptC(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)接口

* Update libcpu/risc-v/ch32v1/cpuport.c

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
 2022-12-22 09:34:36 +08:00
Shell e8504c7cf1
[smart/aarch64] code sync (#6750) 
* [smart/aarch64] sync aarch64
 2022-12-20 17:49:37 +08:00
guo 68ca9f07a6
[rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740) 
* [dfs] sync cromfs

* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration

* [format] fix some format issue.
 2022-12-16 18:38:28 +08:00
guozhanxin e2bdd8a184 [libcpu] fix cpp11 error 2022-12-14 11:04:00 +08:00
Man, Jianting (Meco) 99bdf978d7
[rtdef] use lower-case to define attributes (#6728) 
* [rtdef] rename RT_WEAK attribute as rt_weak

* [rtdef] rename RT_USED attribute as rt_used

* [rtdef] rename RT_SECTION attribute as rt_section

* [rtdef] rename ALIGN attribute as rt_align

* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support
 2022-12-11 13:12:03 -05:00
linshire 8f9198eb99
对接了rthw.h的接口，修复了不能编译的问题 (#6722) 2022-12-10 23:04:26 +08:00
Shell e991be9c51
[smart][risc-v/libcpu] port rv64 cpu code (#6704) 
* [risc-v/libcpu] porting Smart & RTOS
* [fix] rv64 plic
* [risc-v/rv64] remove macro in rtdef
 2022-12-10 22:16:42 +08:00
Yaochenger 9d8da76543
[bsp] add core-v-mcu bsp (#6705) 
* add core-v-mcu bsp

* 规范bsp格式 添加readme

* 修改readme

Co-authored-by: 1516081466@qq.com <ws051000>
 2022-12-08 15:01:37 -05:00
guo ecf2d82159
sync branch rt-smart. (#6641) 
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
 2022-12-03 12:07:44 +08:00
xiaoguang_ma 16f6157b1e [bsp] faster startup for cortex-a 
If the application defines dozens of global variables,
the speed of clearing the bss segment will be slower.

Because icache can be enabled before the mmu enabled.
Therefore, in order to speed up the process of clearing the BSS segment,
enable icache needs to be put ahead.
 2022-11-25 18:04:35 +09:00
Yunjie Gu 8fa9fde43a
[bsp][c28x] add support to not disable global interrupt in context-switch to enable zero-latency isr for critical interrupts. 2022-10-19 23:41:13 -04:00
Wayne Lin ece0c6eef8 Move gtimer driver to libcpu. 2022-10-11 08:46:01 +08:00
Wayne 5d014e8d31 Revert "[libcpu] remove gtimer/pmu from cortex-a" 2022-10-11 08:46:01 +08:00