Evlers
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8c0f689452
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[libcpu][arm][cortex-m4] allows rewrite to interrupt enable/disable api to support independent interrupts management
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2024-08-29 11:58:52 +08:00 |
blta
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b1a9c4c4ea
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[libcpu/arm]: add dsb and isb instructions in the end of rt_hw_context_switch_to (#5748)
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2022-04-08 12:52:22 +08:00 |
aozima
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c3d63e49de
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set Systick interrupt priority to the lowest
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2020-05-30 15:23:25 +08:00 |
Bernard Xiong
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bde47018b8
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[libcpu] Add SConscript in libcpu.
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2019-01-07 06:09:45 +08:00 |
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aozima
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6c39b2d54d
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[libcpu][comtex-m4] enhancement hard fault exception handler.
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2018-07-25 21:39:44 +08:00 |
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aozima
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dd1041bb7f
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[libcpu]: fixed #1196 FPU FPCA issue.
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2018-01-31 18:54:11 +08:00 |
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aozima
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9b7303e511
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update libcpu: ensure fault enable.
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2017-08-18 11:12:58 +08:00 |
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aozima
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2c47f2e683
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Fix some spell error;
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2014-07-31 13:59:25 +08:00 |
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aozima
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34d59ccb0f
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update libcpu/arm/cortex-m4: support lazy stack optimized.
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2013-06-23 18:10:46 +08:00 |
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aozima
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f9e673354a
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update libcpu/arm/cortex-m4: restore MSP.
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2013-06-22 18:59:49 +08:00 |
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Bernard Xiong
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72782e9203
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convert end of line
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2013-01-08 05:05:02 -08:00 |
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wuyangyong
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38ba67a867
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update libcpu cortex-m4.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1967 bbd45198-f89e-11dd-88c7-29a3b14d5316
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2012-02-18 17:46:08 +00:00 |
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wuyangyong
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7906287cfe
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IAR not support VSTMFD and VLDMFD, use VSTMDB and VLDMIA.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1947 bbd45198-f89e-11dd-88c7-29a3b14d5316
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2012-02-16 03:45:50 +00:00 |
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wuyangyong
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aad32f8546
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support context switch load/store FPU register.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1901 bbd45198-f89e-11dd-88c7-29a3b14d5316
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2011-12-31 20:25:44 +00:00 |
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bernard.xiong@gmail.com
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3ac0b7b966
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add STM32F40x porting (uncompleted)
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1770 bbd45198-f89e-11dd-88c7-29a3b14d5316
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2011-10-20 23:55:08 +00:00 |