Fix some code style and init for V2M, ITS.
V2M is the PCI MSI/MSI-X for GICv2.
ITS is the PCI MSI/MSI-X for GICv3/v4.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
PIC may free because some wrongs in debug.
We should remove in PIC list or there are
some undefined behavior will happen.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
The mode permissions for character, block, and pipe devices were
previously set to 0777, which is overly permissive and not in line
with standard practice. This change reduces the permissions to 0666,
restricting execute permissions while still allowing read/write access.
Changes:
- Adjusted permissions for character/block/pipe devices from 0777 to 0666.
Signed-off-by: Shell <smokewood@qq.com>
The `LWP_CONSOLE_INPUT_BUFFER_SIZE` is a legacy config option for TTY
driver used in smart. Since the driver is updated, there's no dependency
of this option any more.
Changes:
- Removed unused Kconfig option `LWP_CONSOLE_INPUT_BUFFER_SIZE`
Signed-off-by: Shell <smokewood@qq.com>
In manual, the prototype of lseek is
`off_t lseek(int fd, off_t offset, int whence);`
where the return type is `off_t` but not ssize_t.
Signed-off-by: Shell <smokewood@qq.com>
The ofw parse should:
1. Check obj_name EQU the current node's rt_data.
2. Find the next object name.
3. goto "2" until obj_name EQU the cmp_cell's obj_name.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
When the driver request a API gets RT_NULL which return value is ptr,
they could not know why get a RT_NULL.
some API return RT_NULL, is not error internal maybe, it just not
supported for this platform, but the driver still could work ok,
the API can return (RT_NULL + -RT_EEMPTY) to driver.
on the other hand, the driver can do more behaviors by error no.
When the API return the -RT_EBUSY, driver can wait for a moment and retry.
When the API return the -RT_ENOSYS, driver can try the next mode or request's name.
Signed-off-by: GuEe-GUI <wusongjie@rt-thread.com>
PCI/PCIe have better performance and more devices support, such as
NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by
IOMMU that the virtualiztion and userspace driver will more safety.
PCI/PCIe device could hot plugging, no design modifications SoC required,
PCI/PCIe on Embedded SoC is popular now.
We make a simple framework to support them.
Feature Lists:
1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC.
2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC.
3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework.
4.Endpoint: a simple EP framework for PCI FPGA or NTB function.
5.OFW: we only support work on OFW SoC, ACPI support in the future maybe.
Host controller:
1. Common PCI host controller on ECAM.
2. Generic PCI host controller on ECAM.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
1. RT_FIELD_PREP: prepare a bitfield element.
2. RT_FIELD_GET: extract a bitfield element.
3. rt_offsetof: member offset of a struct
4. rt_upper_32_bits: high 32 bits of value.
5. rt_lower_32_bits: lower 32 bits of value.
6. rt_upper_16_bits: high 16 bits of value.
7. rt_lower_16_bits: lower 16 bits of value.
8. rt_max_t: fix type of max(...).
9. rt_ilog2: integer logarithm base 2.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
This patch addresses the potential issue of uninitialized elements in
the argument vector returned by `lwp_get_command_line_args()`. The
previous implementation could leave `argv` in an inconsistent state
if certain errors occurred, leading to possible undefined behavior.
Changes:
- Replaced `rt_malloc()` with `rt_calloc()` to ensure `argv` is properly initialized.
- Added a consistent error handling path using `goto error_exit` to handle memory allocation failures and string copy errors.
- Ensured `lwp_free_command_line_args()` is called before returning on error, preventing potential memory leaks.
Signed-off-by: Shell <smokewood@qq.com>
Since the completion is used to sync with ISR mostly, we should set the
default semantic to ISR-safe. So most user will be happy and don't see
any weird behavior in their codes.
Changes:
- Added `rt_completion_wait_noisr` and
`rt_completion_wait_flags_noisr` functions in `completion.h`,
`completion_comm.c`, `completion_mp.c`, and `completion_up.c`.
- The new APIs allow waiting for completions in non-ISR contexts
while ensuring thread context safety.
- Existing documentation and comments were updated to clarify
usage contexts and emphasize restrictions on ISR usage.
Signed-off-by: Shell <smokewood@qq.com>
Analysis: There is still an omission in the preprocessing control of
_control_rtc in 24b0a81 ("Add RT_USING_RTC conditional
compilation protection in ctimer.c")
Solution: Add RT_USING_RTC preprocessing control to missing
_control_rtc
Signed-off-by: Shicheng Chu <1468559561@qq.com>
Analysis: RT_USING_RTC preprocessing is used in 47cd52d ("修复不
使能 RT_USING_DEVICE 时编译报错") to control the reference of
rtdevice.h, as well as the implementation and call of _control_rtc,
but there are some omissions.
Solution: Add RT_USING_RTC preprocessing control to missing
_control_rtc
Signed-off-by: Shicheng Chu <1468559561@qq.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
To support more choice on bootfs. romfs, cromfs are now supported on
risc_v_big platform.
Changes:
- added mount operations under port
- added prototypes for cromfs init APIs
Signed-off-by: Shell <smokewood@qq.com>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9229
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
This patch focuses on the ARM64 general context handling code.
The modifications are aimed at enhancing performance by simplifying
context save/restore operations.
Changes include:
- Adjusted stack alignment in `arch_set_thread_context` function.
- Updated `lwp_gcc.S` to reset frame pointer and link register.
- Refined `rt_hw_backtrace_frame_unwind` to handle user space address checks.
- Added `GET_THREAD_SELF` macro in `asm-generic.h`.
- Simplified context saving/restoring in `context_gcc.h` and related files.
- Optimized `rt_hw_context_switch_interrupt` and related assembly routines.
Signed-off-by: Shell <smokewood@qq.com>
Do unmap before shrink so we don't see mapped entry on page table
insertion, which is not acceptable for riscv implementation of
architecture porting.
Changes:
- add un-mapping of pte on `_null_shrink()`
Signed-off-by: Shell <smokewood@qq.com>
[dfs] feat: Mark dirty on unmap for shared mapping
This patch optimizes the pcache varea management by refining the
conditions under which pages are marked dirty, specifically targeting
the unmap operations in the dfs_pcache component. These changes were
necessary to enhance the efficiency of page cache management.
Changes:
- Adjusted include statements in `dfs_pcache.c` for better organization.
- Modified `dfs_aspace_unmap` function:
- Added a check to ensure `varea` is not privately locked before marking a page as dirty.
- Updated `dfs_aspace_page_unmap` function:
- Added a similar check for `varea` lock status before marking a page as dirty.
Signed-off-by: Shell <smokewood@qq.com>
The changes unify the tick.c implementations for all risc-v64
architectures, leveraging the CPUTIME feature. This refactoring was
necessary to streamline the codebase, and ensure consistent timer
handling across different platforms.
Changes:
- Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues.
- Updated .config for BSPs to update `CPUTIME_TIMER_FREQ`
- Updated header of for API `riscv_cputime_init`
- Initialized riscv timer on `rt_hw_tick_init`
- Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`:
- Replaced direct use of `rdtime` with `clock_cpu_gettime`.
- Removed redundant timer frequency definitions.
- Added static assertions to check the value of `CPUTIME_TIMER_FREQ`.
- Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`.
- Integrated `ktime` support for tick initialization.
Signed-off-by: Shell <smokewood@qq.com>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
feat: [libcpu/c906] support ARCH_REMAP_KERNEL
This change was necessary to enable the remapping of the kernel image to
a high virtual address region on the c906 platform.
Changes:
- Introduced new configuration options `ARCH_REMAP_KERNEL`, and
`ARCH_USING_ASID` under the `ARCH_RISCV64` section.
- Updated MMU initialization and switching functions to incorporate
remapping handling.
- Modified page table setup for proper memory attribute settings.
- Added support for early memory setup, kernel remapping
- Added conditional compilation for ASID support in the `rt_aspace` struct,
since this is not enable currently for most architecture.
Signed-off-by: Shell <smokewood@qq.com>
Skip configure on open since all configs are copied from the current
configuration on device. So we don't bother to set it back to device
again.
Changes:
- test and skip configuration on open() of tty device
Signed-off-by: Shell <smokewood@qq.com>
[ktime] feat: remove recursion on hrtimer
Replace recursive algorithm with a loop in hrtimer
when determining next timeout event and setup hr timer.
Signed-off-by: Shell <smokewood@qq.com>
* support period time
* enable multiple ktimer
* mv set delay_cnt to hrtimer_start
* add ktime debug info
* change current_irq_begin to local var
* fix bug: setting current timer and setting timeout in driver aren't atomicly
* create->init
* refactoring ktime
* [libcpu] support for ARCH_REMAP_KERNEL
These changes introduce support for the ARCH_REMAP_KERNEL configuration,
which isolates kernel space in high virtual address regions. This feature
is necessary to enhance memory protection and management by segregating
user and kernel spaces more effectively.
Changes:
- Updated conditional macros to check for ARCH_REMAP_KERNEL instead of
ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new
configuration option.
- Modified qemu-virt64-riscv Kconfig and SConstruct files to include and
utilize ARCH_REMAP_KERNEL.
- Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv.
- Updated rtconfig.py to use a more flexible execution path setup.
- Enhanced user address space definitions in `lwp_arch.h` to support the
new virtual address mappings.
- Adjusted kernel memory initialization and mapping logic in `c906/mmu.c`
and `virt64/mmu.c` to account for high virtual address regions.
- Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures.
- Enhanced memory setup functions to support new mapping scheme, including
updates to early page table setup and address relocation logic.
These modifications ensure that the system can utilize high memory
addresses for the kernel, improving memory isolation and system stability.
Signed-off-by: Shell <smokewood@qq.com>
* fixup: CI run failed
* bsp: default config without using smart
* fixup: static checks
* restore rt_hw_mmu_kernel_map_init for D1
---------
Signed-off-by: Shell <smokewood@qq.com>
* [utest] remove delay for on thread testing
The delay is introduced from 0dc7b9a5a2.
Though this is unnecessary for on sync utest.
So this is removed by a new entry and delay for asynchronous utest only.
Signed-off-by: Shell <smokewood@qq.com>
* fixup: msh cmd prototype
---------
Signed-off-by: Shell <smokewood@qq.com>
There is no next-level directory under the components/mm/
directory. Do not need to enter the next-level directory
to process the SConscript file.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* [smart] add CPU usage tracing config
This patch introduces following features:
- Added CPU usage tracing functionality, enabled by default, for
applications like 'top'
- update time as smart independent
Signed-off-by: Shell <smokewood@qq.com>
* fixup: add ump idle thread
---------
Signed-off-by: Shell <smokewood@qq.com>
* [DM/feature] Implement PIC irq state { get; set }
There are some common state for irq:
1. Pending: IRQ was triggered, but software not ACK.
2. Active: IRQ was ACK, but not EOI.
3. Masked: IRQ was masked or umasked.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [DM/pic] Support IRQ state { get; set } for ARM GICv2/v3
Signed-off-by: GuEe-GUI <2991707448@qq.com>
---------
Signed-off-by: GuEe-GUI <2991707448@qq.com>
This patch fixup the script execution capabilities on argv passing
and adds support for arguments larger than 4k.
According to POSIX, the script parameter is quiet different
from the current implementation. Especially on the way it inserts
the path of executables. At the end, when you execute a script
from `$PATH`, it always fails.
For the script, interpreter will be invoked with the following
arguments: `{interpreter [optional-arg] pathname arg...}`
where pathname is the pathname of the file specified as the first
argument of execve(), and arg... is the series of words pointed
to by the argv argument of execve(), starting at argv[1]. Note that
there is no way to get the argv[0] that was passed to the
execve() call.
The changes include:
- Separating argument, environment variable, and auxiliary vector
processing into a new lwp_args.c file.
- Fixing bugs in script argument processing and supporting arguments
larger than 4k.
- Updating lwp_execve to use the new argscopy function and removing
the old lwp_argscopy function.
- Making various modifications to lwp_load and elf_aux_fill to work
with the new argument processing.
- Removing unnecessary code related to dynamic loading and interpreter
scripts.
Signed-off-by: Shell <smokewood@qq.com>
* [Feature] Power domain for device
1.Support device power on/off.
2.Support attach/detach device.
3.Support power domain driver api.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [DM/platform] Enhanced platform bus
1.Add power domain for device.
2.Support `remove` and `shutdown` bus interface.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
---------
Signed-off-by: GuEe-GUI <2991707448@qq.com>
Correct `sched_setaffinity()` to use the thread IDs (TIDs) instead of
process IDs (PIDs). The previous implementation used PIDs, which
caused issues since affinity settings need to be applied at the
thread level.
As the manual documented, the signature is:
> int sched_setaffinity(pid_t pid, size_t cpusetsize,
> const cpu_set_t *mask);
Yes, it's tricky, the identification passing in is called **'PID'**.
But when we talk about 'pid' from GNU libc, it's the **'task-id'**,
aka, `thread->tid` known in kernel.
Changes were made by updating the function signatures and logic in
`lwp.h`, `lwp_pid.c`, and `lwp_syscall.c` to accept TIDs. Specifically,
the `lwp_setaffinity` function and related internal functions now
operate using thread IDs and adjust thread affinity settings accordingly
Signed-off-by: Shell <smokewood@qq.com>
[OFW] io ranges use ptr array to storage without ofw data
ofw data is private data for every ofw node that
the drivers of ofw node will use item.
replace the ranges supported to a ptr array.
the ptr array size is config by `RT_USING_OFW_BUS_RANGES_NUMBER`
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [PIC] Make affinity helper interface
Signed-off-by: GuEe-GUI <2991707448@qq.com>
* [PIC/GIC] Fixup GIC affinity init
GICv2 is not support if current CPU is not startup,
but RT-Thread SMP is startup after the devices init
in the `main` thread.
This patch fixup the cpumask to init once and check
the init status in affinity interface.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
---------
Signed-off-by: GuEe-GUI <2991707448@qq.com>
The OFW map id is always use in DMA, PCI, IOMMU
bus system to find the device identity. this is
a access interface.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
DFS mount auto by kernel parameters
1.Mount the rootfs options by parameters:
- root=: root device, like vda1, sda1, sd0p1, nvme0n0p1...
- rootfstype=: root file system type, like elm, ext, crom...
- rw/ro: root is readonly or all enable, if not have 'rw' flag,
the 'ro' flag is default.
- rootwait: always wait for root device status is OK.
- rootdelay=: mount rootfs delay amount of time (millisecond).
2.Mount the other fs options by `fstab.sh`, it will read the script
after root mount is OK, it's format is a list of mount cmds in MSH:
mount vda2 /mnt elm
mount 192.168.1.1:/ /mnt/remote nfs
Signed-off-by: GuEe-GUI <2991707448@qq.com>
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