guo
2babfedd52
Merge pull request #5397 from liukangcc/cflag
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[update] CFLAGS
2021-12-21 17:50:54 +08:00
Man, Jianting (Meco)
6369e89502
[posix] POSIX standard implementation for PSE51 ( #5384 )
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* [posix] POSIX standard implementation for PSE51
- add some posix's interfaces that we haven't before.
- these PR have passed the interface definition test across gcc platfrom;
- have tested base on qemu-a9 and stm32h750-art-pi.
* [newlib] only enable POSIX.1-1990
* update projects
2021-12-17 15:34:17 +08:00
liukangcc
b0f6c2fbae
[update] CFLAGS
2021-12-17 14:28:40 +08:00
Meco Man
bd80b7a4a1
对finsh_set_device调用增加宏定义限制
2021-11-24 08:57:12 -05:00
guo
b1baf42d4e
Revert "Fix compiler flags issue"
2021-10-14 14:36:18 +08:00
JCZou
0369db718c
Fix compiler flags issue
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CCFLAGS is used by gcc and g++ compiler. So CFLAGS should be used for
gcc to avoid passing gcc flags to g++.
2021-08-19 08:53:27 +02:00
yangjie
75e4c9dd0a
[bsp]update GPL license to Apache-2.0, and format files
2021-04-09 10:52:34 +08:00
Bernard Xiong
b8567de625
Merge pull request #4469 from mysterywolf/lpc
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[lpcxxx] auto formatted
2021-03-23 20:04:44 +08:00
Meco Man
958d940575
[lpcxxx] auto formatted
2021-03-17 02:26:35 +08:00
Meco Man
b138082fcc
[python3] 部分脚本从python2语法升级到python3
2021-03-16 17:06:03 +08:00
Meco Man
6263211623
[CI]修复脚本语法错误,解决CI报警
2021-03-10 14:05:08 +08:00
liruncong
6df5634b52
[bsp]SECTION=>RT_SECTION(与catch2中SECTION冲突)
2021-02-09 23:25:56 +08:00
David Lin
95c76c6202
Update vbus_hw.h
2020-11-26 23:41:20 +08:00
David Lin
dc64aa41b6
Update vbus_hw.h
2020-11-26 23:34:12 +08:00
Ernest
7be06b67bb
[add] default environment
2019-10-22 16:48:57 +08:00
yangjie
2f0e312a7f
[bsp]remove log_trace item from all bsp
2019-04-23 14:23:07 +08:00
armink
0d7ba79219
Remove the DBG_COLOR and DBG_ENABLE definition.
2019-03-06 17:54:30 +08:00
chenchaoqun@rt-thread.com
bb8e89e851
【串口】宏定义对应增加
2018-12-17 09:38:53 +08:00
misonyo
a454393994
[BSP][all NXP]change license to Apache-2.0
2018-10-22 11:02:50 +08:00
liang yongxiang
cd39c2525a
[bsp] support get compiler path by environment variables for IAR
2018-04-07 15:43:45 +08:00
moebius.ever
8160a4089a
fixed #1261 , modify "axf" to "elf" in rtconfig.py for GCC Toolchains configuration.
2018-03-07 15:28:51 +08:00
aozima
19433e0cf5
update SConscript: support scons 3.
2018-02-06 20:07:28 +08:00
bernard
5e3b3b19a6
[BSP] change the type of cmd.
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1. Change the type of cmd to 'int';
2. Remove RT_LWIP_USING_RT_MEM macro;
2017-10-16 13:23:03 +08:00
Bernard Xiong
1368e01470
[BSP] fix RT_DFS_ELM_MAX_LFN to 255.
2017-04-09 19:23:28 +08:00
Grissiom
81b37fb1f9
lpc43xx: add copy-right info in vbus drivers
2015-01-08 17:16:26 +08:00
Grissiom
05a01884e6
lpc43xx: fix clock configure
2015-01-07 17:15:50 +08:00
Grissiom
11026d0579
lpc43xx: clean the .o before building M0 and M4
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SCons will omit the file in parent dir of SConstruct somehow and build
the object files in that dir instead of in variant dir. This cause
problem because we cannot mix the object files between M0 and M4 which
SCons failed to rebuild. So we have to manually remove the files before
building.
2015-01-07 17:15:49 +08:00
Grissiom
17a75eaa02
lpc43xx: remove the fpu settings in startup_LPC43xx_M0
2015-01-07 17:15:49 +08:00
Grissiom
22938a93ef
lpc43xx: fix some compile warnings
2015-01-07 17:15:49 +08:00
Grissiom
f7415e595e
VBus: added
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Currently only lpc43xx is supported.
2015-01-07 17:15:49 +08:00
Grissiom
fcff552626
lpc43xx: fix the SConscripts
2015-01-07 10:25:44 +08:00
Grissiom
03a2847f12
lpc43xx: fix some compile warnings
2015-01-07 10:25:44 +08:00
Grissiom
7965708050
lpc43xx: add -Wall
2015-01-07 10:25:44 +08:00
Grissiom
df31744178
lpc43xx: fix the M0 project template
2015-01-07 10:25:43 +08:00
Grissiom
0ca281c162
lpc43xx: add flash linker script for GCC
2015-01-06 13:40:46 +08:00
Grissiom
bcbe180886
lpc43xx: fix the default RTT_ROOT in SConstruct
2015-01-06 13:39:54 +08:00
Grissiom
fca84daa9d
lpc43xx: fix the startup code for GCC
2015-01-06 12:42:12 +08:00
Grissiom
833339e1c6
lpc43xx: output a newline in the header file
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Some compiler is brain-damaged that it will yeild a warning for headers
not ended with a newline. Yes, I mean you, Keil.
2015-01-06 11:03:01 +08:00
Grissiom
ff3ab9c0ab
lpc43xx: add readme
2015-01-06 10:46:32 +08:00
Grissiom
090adcf4c0
lpc43xx: don't set the Clock again in M0 core
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M0 core is always booted by the M4 core. It means that if we are running
in M0, the clock is always configured.
2015-01-06 10:46:32 +08:00
Grissiom
21ef733251
lpc43xx: use the RIT timer as SysTick in M0 core
2015-01-06 10:46:31 +08:00
Grissiom
773a884a4b
lpc43xx: move board.c into M0/M4
2015-01-06 10:46:31 +08:00
Grissiom
d2e4050a70
lpc43xx: update template.uvproj and add sct files
2015-01-06 10:46:31 +08:00
Grissiom
959f6c695f
lpc43xx: move the application code into its own space
2015-01-06 10:46:31 +08:00
Grissiom
5542af8b7c
lpc43xx/driver: fix the VTOR setting
2015-01-06 10:25:43 +08:00
Grissiom
f609a63564
lpc43xx: add uart3 support
2015-01-06 10:25:43 +08:00
Grissiom
a447b5f3cf
lpc43xx: refactor uart drivers
2015-01-06 10:25:43 +08:00
xiaonong
d5332e2799
bsp:fix the bug of lpc43xx uart interrupt enable in driver initialize.
2014-11-03 23:02:36 +08:00
bernard
c45f5a2490
[Drivers] re-write serial framework.
2014-07-18 06:45:54 +08:00
nongxiaoming
7b32a2bd31
lpc43xx:add the linker script file.
2014-07-15 15:42:22 +08:00