5c1b071a0c
[HUST][CSE]mips/common/exception.c/rt_set_except_vector ( #7238 )
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* mips/common/exception.c/rt_set_except_vector
* Update exception.c
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Co-authored-by: Bernard Xiong <bernard.xiong@gmail.com>
2023-04-14 14:06:43 +08:00
f5b0bfd3f4
uniform code writing-disable interrupt
2022-04-20 14:22:43 +08:00
6c907c3a47
[libcpu] auto formatted
2021-03-27 17:51:56 +08:00
a8928c881e
MIPS:fix the RT_EXCEPTION_MAX value
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from <see mips run> know that cp0_cause's ExcCode have 5 bit filed and
the max exception is 32.
2020-09-14 11:10:44 +08:00
c66314a8b6
fixed loongson bsp build on windows
2020-09-04 11:57:35 +08:00
1556ba8e7f
add ls2k mmu
2020-09-04 10:16:34 +08:00
1ec681a551
fix ls2k libc and irq
2020-06-21 23:28:11 +08:00
c024e2e485
add ls2k bsp config
2020-04-07 14:39:20 +08:00
990f731b77
fix mips64 some bug
2020-04-07 14:39:12 +08:00
7c66501861
[libcpu] Refine MIPS common code
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MIPS common code was highly duplicated, This commit
is a attempt to clean-up and refine these code.
The context and exception handle flow is mostly identical
with Linux, but a notable difference is that when FPU enabled,
we save FP registers in stackframe unconditionally.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2019-12-11 15:24:04 +08:00
d1zzy126
thewon86
Meco Man
michael
bigmagic
Jiaxun Yang