PCI/PCIe have better performance and more devices support, such as
NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by
IOMMU that the virtualiztion and userspace driver will more safety.
PCI/PCIe device could hot plugging, no design modifications SoC required,
PCI/PCIe on Embedded SoC is popular now.
We make a simple framework to support them.
Feature Lists:
1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC.
2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC.
3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework.
4.Endpoint: a simple EP framework for PCI FPGA or NTB function.
5.OFW: we only support work on OFW SoC, ACPI support in the future maybe.
Host controller:
1. Common PCI host controller on ECAM.
2. Generic PCI host controller on ECAM.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
1. RT_FIELD_PREP: prepare a bitfield element.
2. RT_FIELD_GET: extract a bitfield element.
3. rt_offsetof: member offset of a struct
4. rt_upper_32_bits: high 32 bits of value.
5. rt_lower_32_bits: lower 32 bits of value.
6. rt_upper_16_bits: high 16 bits of value.
7. rt_lower_16_bits: lower 16 bits of value.
8. rt_max_t: fix type of max(...).
9. rt_ilog2: integer logarithm base 2.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
CV18xx RISC-V C906L.
Configuration value for CPU and ARCH are already defined in rtconfig.py.
Remove these duplication from SConstruct.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
为什么提交这份PR (why to submit this PR)
Issue: using iperf server with sshd together and the kernel will get stuck occasionally.
taken_list is accessed from other mutex when updating priority.
你的解决方案是什么 (what is your solution)
protect taken_list on shared lock, but not on mutex local spinlock.
Signed-off-by: Shell <smokewood@qq.com>
After first called from uart open, the dw8250_uart_configure
API cannot be called again. Otherwise, this will mess up the
device, and uart will not act properly to interrupt again.
Analysis: Configure uart device will close recive interrupte,
causing uart device to malfunction.
Solution: After configure uart device, enable the device's
recive interrupte.
Signed-off-by: Shicheng Chu <1468559561@qq.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
This patch fixes GCC build support for FRDM-MCXC444.
* Updated compiler flags to Cortex-M0 without FPU.
* Updated linker script to add RT-Thread const tables.
Supports both big and little cores of RISC-V C906,
but does not support ARM cores. Currently, only UART
drivers are supported on the peripherals.
Signed-off-by: Shicheng Chu <1468559561@qq.com>
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