Commit Graph

3 Commits

Author SHA1 Message Date
GuEe-GUI 86ba3b666f [DM/FIXUP] Fixup MSI first IRQ read offset
Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-20 16:34:10 +08:00
GuEe-GUI 34cf382c8b [DM/FIXUP] Fixup PCI MSI global irq map
Don't use `irq` as a var when clear MSI global
irq map, the irq which alloc before will rewrite.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-11-20 16:34:10 +08:00
GuEe-GUI 2168ed8e7d [DM/Feature] Basic PCI/PCIe (Peripheral Component Interconnect Express) bus
PCI/PCIe have better performance and more devices support, such as
NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by
IOMMU that the virtualiztion and userspace driver will more safety.
PCI/PCIe device could hot plugging, no design modifications SoC required,
PCI/PCIe on Embedded SoC is popular now.
We make a simple framework to support them.

Feature Lists:
1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC.
2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC.
3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework.
4.Endpoint: a simple EP framework for PCI FPGA or NTB function.
5.OFW: we only support work on OFW SoC, ACPI support in the future maybe.

Host controller:
1. Common PCI host controller on ECAM.
2. Generic PCI host controller on ECAM.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
2024-09-06 17:45:03 -04:00