a0fe71f78f
fixed get sp in HardFault_Handler. close #1646
2018-07-25 21:39:43 +08:00
944b0f1c94
fix annotation error
2018-06-13 15:04:31 +08:00
7785dc5d01
[libcpu] add c-sky ck802 support
2018-06-11 09:43:39 +08:00
aa08164cb3
[libcpu] Sconscript: fix spell srror.
2018-06-04 14:23:54 +08:00
099062de78
[tools][building] Add ASFLAGS in DefineGroup.
2018-06-04 14:18:31 +08:00
7a1f8ee1c4
[libcpu][arm][arm926] Using C header file to define stack and heap size.
2018-06-04 13:34:45 +08:00
32c5b2515f
[libcpu] add risc-v e310 porting
2018-05-31 14:53:26 +08:00
fe691c2ab3
Merge pull request #1484 from TanekLiang/riscv-update
...
remove hifive1 bsp and risc-v/e310 porting
2018-05-29 16:20:39 +08:00
46b9be6038
[libcpu] remove nds32 porting
2018-05-29 12:59:54 +08:00
5faae3350c
[libcpu] remove libcpu/risc-v
2018-05-29 12:59:13 +08:00
330bdf6989
[bsp/ls1cdev]跟上一提交，漏提两个文件
2018-05-12 19:36:08 +08:00
9a7caed323
[bsp/ls1cdev]添加自引导特性，添加配置选项
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1、添加自引导特性，添加配置选项
2、修复cpuport.c的bug
3、修复ls1c_pin.c不能默认复用的bug
2018-05-12 19:33:32 +08:00
dd1041bb7f
[libcpu]: fixed #1196 FPU FPCA issue.
2018-01-31 18:54:11 +08:00
d78f5eb674
Merge pull request #1124 from SummerGGift/add_arm_8-byte_alignment
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[libcpu]: add 8-byte alignment for arm architecture && optimize code …
2017-12-21 17:07:34 +08:00
fc7a5abc76
[libcpu]: add 8-byte alignment for arm architecture && optimize code format
2017-12-21 16:37:38 +08:00
cc75366fda
Merge pull request #1123 from SummerGGift/8-byte_alignment
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[libcpu]: add 8-byte alignment for armv6 architecture
2017-12-21 15:36:21 +08:00
336207ad31
[libcpu]: add 8-byte alignment for armv6 architecture
2017-12-21 15:35:48 +08:00
a4a85a28da
[libcpu]:optimize code format
2017-12-21 15:14:23 +08:00
e7b1786759
[libcpu]:optimize code format
2017-12-21 14:55:34 +08:00
15715692d2
[libcpu]: add 8-byte alignment for armv6 architecture
2017-12-21 10:13:47 +08:00
bb46058d8e
[libcpu] Add ARCH_ARM_ARM9/11 type
2017-12-19 17:39:23 +08:00
eb72d19179
[libcpu] add volatile for __asm.
2017-11-22 09:54:36 +08:00
2488624a18
[libcpu] add volatile for asm (" mcr ") or asm (" mrc ") instruct.
2017-11-22 09:54:27 +08:00
afc2256d01
[libcpu]Support x1000 CPU
2017-11-10 19:50:14 +08:00
f6170a6e5b
[BSP] add i.MX 6UL BSP
2017-11-01 13:30:17 +08:00
756bfcc5e2
Update Kconfig.
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1. Add IPADDR/GWADDR etc;
2. Add Kconfig for libcpu.
2017-10-31 09:54:23 +08:00
6085f6826d
[bsp][at91sam9260] Fix the problem of the finsh function failure by using component initialization.
2017-10-19 23:46:17 +08:00
5e3b3b19a6
[BSP] change the type of cmd.
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1. Change the type of cmd to 'int';
2. Remove RT_LWIP_USING_RT_MEM macro;
2017-10-16 13:23:03 +08:00
f8a1bf6fd8
[libcpu] code cleanup for nds32.
2017-10-09 18:06:58 +08:00
c2f028ed8d
Update cpuport.c
2017-10-06 11:43:50 +08:00
ea18ef60ed
Merge pull request #826 from ArcherChang/master
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[BSP] Add Andes N1068 porting and simple bsp.
2017-10-06 11:03:02 +08:00
0d193254f8
Merge pull request #845 from caogos/master
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[BSP] Add FPU option for loongson1c.
2017-09-14 17:06:11 +08:00
574e22bdbd
在配置文件“rtconfig.h”中增加硬浮点FPU的配置项，
...
浮点经常会用到，所以默认使用硬浮点。
2017-09-13 15:21:09 +08:00
cb247e913f
update libcpu: cortex-m0 fault handlers always enable.
2017-09-01 10:22:55 +08:00
2ac493698b
[BSP] cleanup for hifive1 bsp.
2017-08-26 11:02:39 +08:00
652ea85a39
[1] Andes N1068体系移植
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a. Libc改用官方版本（工具链附带版本）；
b. 去除未使用文件；
2017-08-25 14:25:35 +08:00
b9ebd183ae
Merge pull request #827 from caogos/master
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[BSP] Add EMAC driver in loongson1C (ported by chinesebear, https://github.com/chinesebear/rtt-net )
2017-08-25 11:07:34 +08:00
921fbfbc21
[1] 添加Andes N1068体系；
...
[2] 基于AE210P EVB板；
[3] 详细信息参阅bsp/AE210P/readme文件夹；
《Andes工程创建和调试》文档；等。
2017-08-25 10:25:33 +08:00
9bbc4e5e6b
update cortex-m libcpu: fixed compile error.
2017-08-23 16:13:51 +08:00
838c63f365
添加龙芯1C片内网卡的驱动（原创作者是chinesebear， https://github.com/chinesebear/rtt-net）
2017-08-23 15:46:51 +08:00
9b7303e511
update libcpu: ensure fault enable.
2017-08-18 11:12:58 +08:00
4626b19ead
Merge pull request #784 from zhangjun1996/master
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[BSP] add bsp for sifive(risc-v e310).
2017-08-10 16:51:59 +08:00
7129d77bee
增加龙芯1c硬浮点的支持（可以使用硬浮点了）
2017-08-10 15:35:03 +08:00
72cfe9dd68
modify： drivers/cpuusage.c
...
modify： ../../libcpu/risc-v/e310/stack.c
rmove unused macro definition
modify： ../../src/idle.c
Return to the original version
2017-07-31 12:05:45 +08:00
0cd49e7c4a
Merge branch 'master' of https://github.com/RT-Thread/rt-thread
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add new bsp for risc-v
2017-07-31 11:27:46 +08:00
e9f1bdf2da
new file： ../../libcpu/risc-v/e310/trap.c
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add file that forget to submit before
auto change timer mtimercmp register on the base of RT_TICK_PER_SECOND in rtconfig.h
no flashing led
new file： ../../src/idle.c
recover old file
2017-07-31 11:12:28 +08:00
a5305c05df
fix bug in context_gcc.s and start_gcc.s:
...
save mie into stack
msh running normaly
2017-07-31 10:59:59 +08:00
b032dff161
fix bug in rt_hw_context_switch_interrupt_do
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save sp to old thread
clear rt_thread_switch_interrupt_flag
always enable interrupt after rt_hw_context_switch
judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt)
2017-07-30 19:46:28 +08:00
2d56a27c20
修改： ../../libcpu/risc-v/e310/context_gcc.S
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enable interrupt after return form rt_hw_context_switch
2017-07-30 15:34:32 +08:00
3c51848d33
fix trap_entry
2017-07-29 15:37:20 +08:00
b80f83f360
modified: ../../libcpu/risc-v/e310/context_gcc.S
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fix open timer intrrupt
2017-07-26 16:27:54 +08:00
98a6896cfa
remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();
...
it will lead to interrupt again in interrupt
2017-07-26 16:07:01 +08:00
358612c8a2
支持GPIO中断（外部中断）
2017-07-20 17:35:03 +08:00
d1bb7c61f4
将支持的中断个数从32个扩展到160个，至此可以支持所有中断
2017-07-20 17:05:59 +08:00
f39164203e
修正龙芯1c的中断号
2017-07-18 17:04:32 +08:00
b334347a24
deleted: rtthread.s /*just for debug*/
...
modified: ../../libcpu/risc-v/e310/context_gcc.S
change ret to mret and switch to new task with mepc
2017-07-17 16:55:33 +08:00
e01455155a
add context_gcc.s
2017-07-17 15:44:00 +08:00
a74a2a25a8
Add libcpu/arm/am335x/context_iar.S file
2017-02-06 21:57:15 +08:00
b96f07e477
flush cache after exception code install
2016-06-15 08:09:56 -07:00
4e95fdff4a
[BSP] Update VFP code in armv6.
...
committed by FH.
2016-05-20 14:20:34 +08:00
923594c7ab
[BSP] Enable VFP.
...
committed by FH.
2016-05-20 12:24:51 +08:00
255f8b7c34
[BSP] Add BSP for Ingenic X1000 CPU
2016-04-24 19:34:41 +08:00
86216ceecc
start exception by chinesebear
2016-04-19 22:08:23 +08:00
43f68131ce
[BSP] Add fh8620 bsp from Shanghai Fullhan Microelectronics Co., Ltd.
...
FH8620 BSP
Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
All rights reserved
2016-04-18 13:52:39 +08:00
3983f39f34
Add iar compiler support for am335x.
2015-11-11 23:44:05 +08:00
3faca6d5df
[BSP] update stm32f7-disco
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code cleanup.
2015-09-24 16:03:09 +08:00
a0de58a008
[BSP] fix x86 bsp compiling issue
2015-09-15 11:50:29 +00:00
2021f5a276
Add the license.
2015-09-04 21:58:08 +08:00
b71cb4c09d
Add dm365 porting.
2015-09-04 12:30:20 +08:00
af8a91457e
[bsp]add the stm32f74x bsp.
2015-08-07 13:30:13 +08:00
4ad1b35537
chinesebear add bsp & libcpu
2015-07-09 07:38:07 +08:00
9fe3cbf76f
Align thread stack to 8 byte.
2015-06-05 19:14:08 +08:00
314379cc77
implement __user_initial_stackheap
2015-06-04 12:23:24 +08:00
be76b10be6
Align stack address to 8 byte.
2015-06-04 11:59:18 +08:00
1fa5711712
fixed assembly warnings.
2015-05-22 16:48:01 +08:00
73df162d3f
fixed assembly warnings.
2015-05-13 11:57:34 +08:00
4222677933
[libcpu][am335x] Fix the booting failure when enabling MMU
...
Since the 16 domains are configured as the client domains in
mmu_setttbase(), a Permission fault is generated if the XN bit
(Execute-never) is set in the short-descriptor translation table
(for section and supersection). This leads to the booting failure
when enabling MMU for beagleboard bsp. Here is log:
----------------------------------------------------------------
SD/MMC found on device 0
reading uEnv.txt
117 bytes read in 3 ms (38.1 KiB/s)
Loaded environment from uEnv.txt
Importing environment from mmc ...
Running uenvcmd ...
reading rtthread.bin
162624 bytes read in 24 ms (6.5 MiB/s)
\## Starting application at 0x80200000 ...
----------------------------------------------------------------
This commit removes the XN bit configuration in the section of the
short-descriptor translation table. The OS can be booted successfully
with applying this commit.
2015-05-11 10:36:11 +08:00
a13132b302
[libcpu][arm926] Optimize irq trap code.
2015-05-04 16:13:43 +08:00
49fa5c44d7
[libcpu][arm926] Optimize code
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1. Combine code for IAR and GCC in file mmu.c and cpuport.c
2. Remove remap code in start_xxx.S. User should config MMU to map vector table to visual address 0x0
2015-04-22 11:19:50 +08:00
175e357ace
[libcpu][arm926] Remove unused SPSR register PUSH/POP when os switch thread.
2015-04-16 14:13:43 +08:00
cf3d639fcb
[libcpu][arm926] Define vector table start at BSP/{board}/platform/ assemble INC files.
2015-04-16 10:35:12 +08:00
6aa242645f
1. [bsp][sam9260] Fix the bug that auto reset after boot 20s. Disable watchdog in rt_lovel_level_init function.
...
2. [bsp][sam9260] Modify SCONS scripts to support IAR tool chain.
3. [bsp][sam9260] Move link strips in to folder link_scripts.
4. [libcpu][arm926] Add copy right to source file and format code.
2015-04-15 16:13:30 +08:00
39452b67b0
1. [cpu] split ARM926 cpu code from AT91SAM9260 BSP
2015-04-14 21:56:34 +08:00
0b5958d700
Fix compile warning:
...
..\..\libcpu\arm\cortex-m3\context_rvds.S(207):
warning: A1581W: Added 2 bytes of padding at address 0xd6
2015-03-09 09:31:23 +08:00
4fea46c83c
support rx62n
2014-11-12 01:09:43 +08:00
62af08370b
Merge pull request #2 from RT-Thread/master
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sync
2014-09-20 01:19:42 +08:00
267c61ebce
[libcpu] Add builtin ffs implementation for Cortex-M4.
2014-09-11 12:51:33 +08:00
11fb9060e0
mips/loongson_1b: format code
2014-08-18 15:24:21 +08:00
0ee101ccb0
mips/loongson_1b: install NULL handler is OK
2014-08-18 15:22:16 +08:00
1d928f7daf
mips/loongson_1b: fix rt_interrupt_dispatch
2014-08-18 15:21:09 +08:00
fd6ef4b235
[libcpu]am335x edit vector
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vector_undef and vector_dabt
2014-08-12 18:26:22 +08:00
2c47f2e683
Fix some spell error;
2014-07-31 13:59:25 +08:00
2604440ceb
[bsp] Remove none-released porting
2014-07-12 11:08:38 +08:00
97fb91dcc6
bsp: add zynq7000
2014-06-27 14:12:36 +08:00
2b7be29cad
[bsp/rva8] enable group{0,1} interrupt forwarding in gic initialization
...
When RT-Thread is running stand alone, it forgot to enable the
distributor of GIC.
2014-04-08 11:54:03 +08:00
c0f0c2322f
[libcpu/arm] remove useless cpsr updating in rt_hw_context_switch_to
...
This piece of code will enable the interrupt early before switching to
the first thread. Although it is harmless, but not prefect.
2014-04-08 11:24:04 +08:00
28f11fdd7b
[vmm] add realview-pb-a8 VMM support
2014-04-03 17:59:14 +08:00
9382a7105f
add CM_PER_UARTx_CLKCTRL
2014-01-11 15:14:36 +08:00
0c9b9ced31
cortex-r4: use byte to allocate the stack
...
Unit of "byte" is more intuitive than "long".
2013-11-17 12:49:08 +08:00
a8520ed383
cortex-r4: let svc mode reuse the stack of IRQ on startup
...
As the svc stack is the stack of threads, there is no need to allocate a
separate stack for the startup. Reuse the IRQ stack should be OK.
Tested on rm48 board.
2013-11-17 12:49:07 +08:00
06987e72e5
Fix hardfault bug for gcc port
...
for 2013-02-20 aozima commmit "port for gcc", but the commit is
not tested,and the kernel is breakdown in context_gcc.S, the file
is a copy from cortex-m3,but not port for cortex-m0, so i complete
this port for aozima, test it in stm32f0discovery board ,
and it works fine.
2013-11-04 16:10:11 +08:00
377c6e6cc9
cortex-r4: dump register on traps
...
We could not handle any traps except IRQ/FIQ.
2013-10-20 23:46:50 +08:00
e1e563e85c
cortex-r4: remove RM48x50.h and add armv7.h
2013-10-20 21:10:26 +08:00
81ab083ae5
rm48: move some asm file to libcpu
2013-10-20 18:51:46 +08:00
9568669109
rm48x50: add GCC support
2013-10-20 18:51:45 +08:00
7bdb082c91
Delete SConscript
2013-09-22 06:59:52 +08:00
9d09cd9f23
Import beaglebone porting
2013-09-20 21:20:51 +08:00
3ebc766521
sim/posix: move rt_hw_context_switch_interrupt after it's definition
...
This fix a compile error in Clang.
2013-09-04 00:05:03 +08:00
e301d14979
Merge pull request #132 from MrVan/sep6200
...
SEP6200 Support
2013-07-29 22:35:31 -07:00
37ac4855da
Embedded GPLv2 license.
2013-07-21 20:01:24 +08:00
36c4604a36
fix compiling error
2013-07-21 19:39:21 +08:00
42f9840653
commit again
2013-07-21 17:32:55 +08:00
3bdbf640b7
update at91sam9260 project directory structure.
2013-07-21 17:19:30 +08:00
885301bb14
update AT91SAM9260 usart driver， using serial driver component.
2013-07-21 15:01:42 +08:00
82bc21ff7b
Cleanup and add licencse
2013-07-17 18:42:19 +08:00
73beced22a
SEP6200 Support
2013-07-17 13:37:31 +08:00
ce4f0329db
enhancement hard fault exception handler.
2013-07-09 22:02:12 +08:00
5120f54a29
fix spelling error.
2013-06-24 22:57:27 +08:00
34d59ccb0f
update libcpu/arm/cortex-m4: support lazy stack optimized.
2013-06-23 18:10:46 +08:00
b045f93b47
fixed bug: correct cortex-m SCB->VTOR address.
2013-06-23 18:08:16 +08:00
93b9b28297
format code by Astyle.
2013-06-23 18:07:10 +08:00
a2ff85c03f
update libcpu/arm/cortex-m0: restore MSP.
2013-06-22 18:59:51 +08:00
4d421cad73
update libcpu/arm/cortex-m3: restore MSP.
2013-06-22 18:59:50 +08:00
f9e673354a
update libcpu/arm/cortex-m4: restore MSP.
2013-06-22 18:59:49 +08:00
3071e35c54
Merge pull request #109 from grissiom/rm48x50
...
Rm48x50
2013-06-19 01:29:12 -07:00
c986754c49
Signed-off-by: visitor83 <wolflouiswang@gmail.com>
...
format the s3c24x0 serial.c and mini2440 rtconfig.py
2013-06-18 12:51:55 +08:00
c56fa7c907
ident format
...
Signed-off-by: visitor83 <root@wolflouis.(none)>
2013-06-16 10:00:34 +08:00
009239ceed
rm48x50: rt_interrupt_nest should be `volatile rt_uint8_t`
2013-06-12 23:56:10 +08:00
9b949c28b7
rm48x50: add cache_{enable, disable}
2013-06-12 21:03:04 +08:00
e8bbbe6788
cortex-r4: wrap asm functions with .asmfunc/.endasmfunc
2013-06-05 23:21:06 +08:00
228a6be077
cortex-r4: add __rt_ffs
2013-06-05 23:20:39 +08:00
e74befca44
move libcpu/arm/rm48x50/ to libcpu/arm/cortex-r4
2013-05-31 21:06:26 +08:00
24fc6e6ebb
rm48x50: VFP lazy stacking
...
You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT
will turn on VFP for all threads and stack all the VFP registers. When
doing lazy stacking, VFP will only be turned on for the thread who
issued VFP instructions.
Currently, if a thread turned on VFP, it cannot be turned off. RTT will
never know what time the thread doesn't need VFP any more. The thread
might could turn off the VFP for it self in proper time.
2013-05-31 20:58:08 +08:00
8bbfd45ce3
rm48x50: change STMFD/LDMFD to STMDB/LDMIA
...
VFP instructions only have IA(Increment After)/DB(Decrement Before)
mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31 18:38:42 +08:00
ec1203bfab
rm48x50: turn on VFP support
...
This support Common VFPv2 sub-architecture.
2013-05-31 18:32:21 +08:00
83ea4dd628
rm48x50: small cleanup on context_ccs.asm
2013-05-30 17:37:50 +08:00
810311b624
rm48x50: fix bug in rt_hw_interrupt_{mask,unmask}
2013-05-29 23:36:32 +08:00
f08df08897
rm48x50: optimize a BEQ
...
Use condition flag in the ORR. This could eliminate a BEQ.
2013-05-26 23:37:56 +08:00
19fe6251e7
rm48x50: optimize context_switch_interrupt_to by reuse registers
...
When saving thread registers in context_switch_interrupt_to, we don't
change them, just move them. So there is no need to always r0-r3 from
stack to the real r0-r3. So just use the intermediate registers and
eliminate 2 MOV.
2013-05-26 22:37:49 +08:00
3d0647efb3
rm48x50: optimize context_switch_interrupt_do
...
Substitude STMFD, MOV, ADD with STMFD, SUB. It reduce one instruction.
Tested on board and it works like a charm.
2013-05-26 17:22:36 +08:00
b39d038cf0
rm48x50: utilize CPS instruction and remove some useless code
2013-05-26 16:55:39 +08:00
f51bce3fed
add rm48x50 bsp and libcpu
...
We currently only support building with CCS and SCons is not using.
bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
You may need to regenerate the source file as you like, providing that:
1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
channel 5 in enabled and connected to IRQ.
2, RTI driver is enabled and compare3 source is selected to counter1
and the compare3 will generate tick in the period of 10ms. This
value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
In CCS, you need to create a new CCS project and create link folders
pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
to add the include path to the Build Properties.
2013-05-24 22:55:13 +08:00
db548a1b37
fixed compiling error related to the RT_USING_INTERRUPT_INFO in mini4020
2013-04-10 00:49:18 +08:00
d9d39a8d21
Use SRAM as EMAC transmit buffer, to avoid the underrun error, especially in the large amount of data communication.
2013-04-08 21:57:24 +08:00
0594734d8d
clean up code
2013-04-02 20:33:56 +08:00
03aa76155e
fixed context thread issue when using armcc compile
2013-04-02 20:27:08 +08:00
fb9ea5eada
enable at91sam9260 mmu, update SDIO and EMAC drivers
2013-04-02 20:24:51 +08:00
92d4c1939b
fixed at91sam9260 context thread issue, avoid idle thread stack overflow
2013-04-02 20:23:11 +08:00
edef109d76
fix interrupt compiling issue in PPC
2013-03-31 22:58:36 -04:00
c1b600644f
Merge pull request #56 from aozima/aozima
...
Modify the interrupt interface implementations.
2013-03-31 04:14:40 -07:00
2ccb3c7589
update LPC2478: Modify the interrupt interface implementations.
2013-03-31 18:25:51 +08:00
710a0fc4a5
fix issue when print interrupt info
2013-03-31 18:24:51 +08:00
1549b7db90
update LPC214X: Modify the interrupt interface implementations.
2013-03-31 17:58:26 +08:00
eab20a9975
update AT91SAM7X: Modify the interrupt interface implementations.
2013-03-31 17:43:09 +08:00
83ce430902
update loongson 1B dev: Modify the interrupt interface implementations.
2013-03-31 17:32:25 +08:00
93e04a1366
update loongson dev3210: Modify the interrupt interface implementations.
2013-03-31 17:32:20 +08:00
6058efbd9b
update Jz47xx: Modify the interrupt interface implementations.
2013-03-31 17:32:16 +08:00
29a3ae4368
update sep4020: Modify the interrupt interface implementations.
2013-03-31 17:32:04 +08:00
fbc1b05dd8
update mini2440: Modify the interrupt interface implementations.
2013-03-31 17:30:30 +08:00
608074deaf
update to interrupt description
2013-03-30 08:15:27 +08:00
8e6a534fa3
fix compiling issue in Jz47XX
2013-03-26 09:08:25 +08:00
bb72be94b2
code cleanup for interrupt description
2013-03-26 08:52:33 +08:00
5639c5daed
implement __rt_ffs for armv5
2013-03-24 16:03:23 +08:00
1abaa0492d
implement __rt_ffs in kernel service library
2013-03-23 11:27:29 +08:00
7917cf09e7
remain the old handler to keep forward compatibility
2013-03-19 11:25:46 +08:00
9678ee67e9
Modified the interrupt function comments
2013-03-19 11:25:33 +08:00
b21028474b
Modify the interrupt interface implementations, changes in the part of the parameter definition.
2013-03-19 11:25:12 +08:00
be59c9287f
fixed cache initial bug.
2013-03-08 11:23:40 +08:00
9ccdf4172e
basic mingw support for simulator: kernel and finsh
2013-02-26 16:03:08 +08:00
d80888a194
port stm32f0x to gcc.
2013-02-20 22:03:31 +08:00
b8aaa6e730
clean code in cpu_port.c, add some comments
2013-01-16 18:49:07 +08:00
b8bd5c8309
fix bug in cpu_port.c(can work very well)
2013-01-15 23:59:14 +08:00
395178ebfa
rewrite cpu_port.c (but still has bug)
2013-01-15 21:38:54 +08:00
07da6caafd
surport finsh
2013-01-14 22:38:54 +08:00
8f70786c30
add finsh, but still cannot work, only can be built with gcc
2013-01-14 16:50:40 +08:00
7b42f926a0
re-write the rt_hw_interrupt_enable/disable
2013-01-14 14:14:40 +08:00
5685a395be
add some comments and clean code in cpu_port.c
2013-01-14 01:23:08 +08:00
7b58dd92fa
add libcpu/sim/posix/cpu_port.c
2013-01-13 22:58:45 +08:00
72782e9203
convert end of line
2013-01-08 05:05:02 -08:00
ecd66612cf
remove lpc122x because there is a common cortex-m0 porting.
2013-01-04 06:03:03 -08:00
68fadd9edc
Add exception hook function.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2551 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-29 09:36:16 +00:00
ac9c373d7f
Add thread name to Win32Thread.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2541 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-29 03:28:31 +00:00
8df650d861
clean code in sim/win32/cpu_port.c
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2536 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-27 08:31:53 +00:00
468ade5e98
fixed the coding style in libcpu/arm
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2518 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-24 06:59:14 +00:00
f6629a1e4c
rename the file name using low case
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2514 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-24 03:50:42 +00:00
eab30ebbda
fixed the fixed the gcc compiling error in ubuntu host OS
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2512 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-24 03:34:04 +00:00
5be0c53dd8
stack addr align to 8byte.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2509 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-23 07:40:31 +00:00
2955dbfcda
add LPC4330 BSP based on NGX xplorer development board
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2487 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-17 08:21:29 +00:00
6ae9a5d95c
revert wrongly commit.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2408 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-11-13 08:10:23 +00:00
f78a50883b
remove nuc1xx because there is a cortex-m0 branch.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2407 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-11-13 07:59:28 +00:00
ec0cb881d8
remove lpc1100 because there is a cortex-m0 branch.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2406 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-11-13 07:56:40 +00:00
6fe2afed8c
for rt-thread 1.1.0
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2372 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-26 03:36:13 +00:00
20352571e2
add libcpu/sim/win32 to support the win32 bsp (compiled by visual studio)
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2359 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-21 04:46:24 +00:00
806ecbbb2b
update libcpu/SConscript to support cl(c compiler of visual studio)
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2358 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-21 04:42:49 +00:00
0c13711396
Add taihu bsp (PPC405)
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2350 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-14 23:28:37 +00:00
0057604ad2
update hdisr_gcc.S: push argument for ISR.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2341 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-10-10 16:39:49 +00:00
e0a5c0ae81
save texit address in to thread stack in m16c
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2308 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-09-26 06:43:35 +00:00
c784dd2ed8
update V850 BSP, now supporting scons + IAR
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2306 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-09-25 04:18:24 +00:00
6dcb1207b1
initialize register r31(LP) with texit in V850/cpuport.c
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2305 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-09-25 03:19:43 +00:00
056228cce6
fixed bug: store r8 - r11.
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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2258 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-08-22 15:53:54 +00:00
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