Commit Graph

148 Commits

Author SHA1 Message Date
Shell dfd8ccf262 feat: kernel/libcpu: fit into ilp32d 2024-09-01 15:12:34 -04:00
flyingcys 82f30aa54f
rename c906 FPU macro (#9290)
1. 修改 ENABLE_FPU 为 ARCH_RISCV_FPU,与libcpu/common 保持统一
2. 对 bsp/cvitek/cv18xx_risc-v 中增加使能 ARCH_RISCV_FPU 的动作。解决了 issue #9075
2024-08-27 00:46:41 -04:00
Yaochenger a4a5953256 [bsp][ch32] add eth driver 2024-08-01 17:31:52 +08:00
MuChenger 0efc408a00 adapt to rv64ilp32 toolchain 2024-07-18 15:59:40 +08:00
Shell f6f570df74
Merge branch 'master' into shell/rv64-tick 2024-07-17 09:39:54 +08:00
Fan Yang 96ba787e25
Bugfix/fix weak handle trap in riscv common crash rv64 trap handling (#9189)
* [bsp][hpmicro] add weak handle_trap implementation

- added weak handle_trap implementation

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

* [libcpu][risc-v][common] remove weak handle_trap function

- removed weak handle_trap function from trap_common.c

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

---------

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2024-07-15 17:51:32 +08:00
Shell 65ffe4e13e [libcpu/rv64] feat: unify tick.c
The changes unify the tick.c implementations for all risc-v64
architectures, leveraging the CPUTIME feature. This refactoring was
necessary to streamline the codebase, and ensure consistent timer
handling across different platforms.

Changes:
- Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues.
- Updated .config for BSPs to update `CPUTIME_TIMER_FREQ`
- Updated header of for API `riscv_cputime_init`
- Initialized riscv timer on `rt_hw_tick_init`
- Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`:
  - Replaced direct use of `rdtime` with `clock_cpu_gettime`.
  - Removed redundant timer frequency definitions.
  - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`.
  - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`.
  - Integrated `ktime` support for tick initialization.

Signed-off-by: Shell <smokewood@qq.com>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-15 12:06:39 +08:00
Shell beee77f372
feat: support ARCH_REMAP_KERNEL on libcpu/c906 (#9123)
feat: [libcpu/c906] support ARCH_REMAP_KERNEL

This change was necessary to enable the remapping of the kernel image to
a high virtual address region on the c906 platform.

Changes:
- Introduced new configuration options `ARCH_REMAP_KERNEL`, and
  `ARCH_USING_ASID` under the `ARCH_RISCV64` section.
- Updated MMU initialization and switching functions to incorporate
  remapping handling.
- Modified page table setup for proper memory attribute settings.
- Added support for early memory setup, kernel remapping
- Added conditional compilation for ASID support in the `rt_aspace` struct,
  since this is not enable currently for most architecture.

Signed-off-by: Shell <smokewood@qq.com>
2024-07-11 11:00:04 +08:00
heyuanjie87 b09a9784f9
[libcpu/c906]与virt同步 (#9095) 2024-06-26 12:16:37 +08:00
heyuanjie87 a5a89c439f
[rv]修正signal退出后用户态sp少8的问题 (#9080) 2024-06-24 21:36:32 +08:00
heyuanjie87 06ad67d549
[rv]信号处理进入用户态前恢复gp (#9072)
* [rv/virt/stackframe.h]添加GP寄存器保存偏移量宏

* 【rv/c906/stackframe.h]定义GP寄存器存储偏移量

* [rv]信号处理切换到用户态前恢复gp
2024-06-21 09:09:41 +08:00
Shell 65c9947225
[libcpu] rv64: support for ARCH_REMAP_KERNEL (#9067)
* [libcpu] support for ARCH_REMAP_KERNEL

These changes introduce support for the ARCH_REMAP_KERNEL configuration,
which isolates kernel space in high virtual address regions. This feature
is necessary to enhance memory protection and management by segregating
user and kernel spaces more effectively.

Changes:
- Updated conditional macros to check for ARCH_REMAP_KERNEL instead of
  ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new
  configuration option.
- Modified qemu-virt64-riscv Kconfig and SConstruct files to include and
  utilize ARCH_REMAP_KERNEL.
- Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv.
- Updated rtconfig.py to use a more flexible execution path setup.
- Enhanced user address space definitions in `lwp_arch.h` to support the
  new virtual address mappings.
- Adjusted kernel memory initialization and mapping logic in `c906/mmu.c`
  and `virt64/mmu.c` to account for high virtual address regions.
- Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures.
- Enhanced memory setup functions to support new mapping scheme, including
  updates to early page table setup and address relocation logic.

These modifications ensure that the system can utilize high memory
addresses for the kernel, improving memory isolation and system stability.

Signed-off-by: Shell <smokewood@qq.com>

* fixup: CI run failed

* bsp: default config without using smart

* fixup: static checks

* restore rt_hw_mmu_kernel_map_init for D1

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-06-18 11:15:59 +08:00
Shell e5b7f3fdd8
[kservice] Enhance support for backtrace service (#9037)
[feat] Enhance support for backtrace service

rt_backtrace_formatted_print() and rt_backtrace_to_buffer() to help
debug routines.

Also, following modification are included:
- make rt_backtrace_frame patchable with weak attr
- replace lwp backtrace with sync output

Signed-off-by: Shell <smokewood@qq.com>
2024-06-13 08:55:53 +08:00
Shell f00db6381a
[mm] precise & readable mm fault type (#9047)
* [smart] fixup: precise mm fault type

Also, fixup arm64 read access fault

* arm64: using meaningful macro on trap

* fixup: renaming macro
2024-06-07 21:34:03 +08:00
Shell 397cdcd132
[libcpu] discard rt_current_thread (#8976)
* [libcpu] rv64: discard rt_current_thread

* arm: using rt_thread_self to fetch current TCB
2024-05-26 22:00:17 +08:00
Shell 48bd0e49f2
[ipc] support of lockless rt_completion (#8887)
* [ipc] lockless rt_completion implementation

The new rt_completion implemented by lockless algorithm can improve timer resolution for up to ~12%, compare to sem IPC.

Signed-off-by: Shell <smokewood@qq.com>

* fixup: error

* remove useless changes

---------

Signed-off-by: Shell <smokewood@qq.com>
2024-05-08 09:25:57 +08:00
Fan Yang c21ba6985d
Fix compiling eror in hpmicro bsp (#8889)
- added 'DEVICE' to rtconfig.py
- fixed compiling error cuased by change in interrupt_gcc.S

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2024-04-30 20:11:47 +08:00
flyingcys 2c8c4ccc47
[bsp]support cvitek sdhci drvier (#8849)
support cvitek sdhci drvier
2024-04-24 05:40:22 +08:00
Shell ea63dd6c57
[libcpu/rv64] fixup for parameter passing on backtrace (#8655)
Signed-off-by: Shell <smokewood@qq.com>
2024-03-21 20:23:36 +08:00
LiuLingze 8120fa5e31 [bsp][cv1800b] fix a implicit-function-declaration warning
Signed-off-by: LiuLingze <luiyanbing@foxmail.com>
2024-03-19 08:10:43 -04:00
LiuLingze 26b40d534c [bsp][cv1800b] fix a int-conversion warning
Signed-off-by: LiuLingze <luiyanbing@foxmail.com>
2024-03-19 08:10:43 -04:00
Shell 71560bafb5
🎯 Sync smart & scheduler codes (#8537)
Signed-off-by: Shell <smokewood@qq.com>
Co-authored-by: xqyjlj <xqyjlj@126.com>
2024-02-23 17:49:15 +08:00
Yuqiang Wang c6bdee3c50
[ci] open ci check with function declaration warning (#8546) 2024-02-20 22:45:04 -05:00
Meco Man bd228eb9c5 [ci] fix errors under strick compiling mode 2024-02-20 08:39:05 +08:00
Meco Man 6d4503363a [libcpu][SConscript]规范group名为libcpu 2024-02-20 08:39:05 +08:00
flyingcys 3f41bd95d1
add libcpu/risc-v/rv64 (#8511) 2024-01-28 13:39:39 +08:00
xqyjlj 1b6f0e88a3
🐞 fix: fix d1s smart build (#8212) 2023-11-02 20:16:02 +08:00
Shell 70a8d1d465
[kservice] improve backtrace service in kernel (#8144)
Signed-off-by: Shell <smokewood@qq.com>
2023-10-21 20:14:45 +08:00
Shell 1d678e5596
[smart] fixup: mmap support (#8154)
Signed-off-by: Shell <smokewood@qq.com>
2023-10-20 13:28:20 +08:00
geniusgogo ecd29fda60
Sync dfs lwp (#8123) 2023-10-17 13:07:59 +08:00
Shell 47b183a297
[smart/syscall] fix exit(2) and add exit_group(2) (#8005)
Signed-off-by: shell <smokewood@qq.com>
Signed-off-by: shell <wangxiaoyao@rt-thread.com>
Signed-off-by: Shell <smokewood@qq.com>
2023-09-09 09:35:56 +08:00
Shell d862816a51
[components/mm] add unmap page API (#7834)
Signed-off-by: Shell <smokewood@qq.com>
2023-08-16 15:38:59 +08:00
Fan YANG 5308cc4716 [libcpu][risc-v][common] Fix application crash on risc-v soc if FPU is
enabled

- Defined ARCH_RISCV_FPU once the __riscv_flen macro was detected

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2023-08-11 21:20:28 -04:00
Fan YANG 5ac509b6d0 [libcpu][risc-v][common] Avoid using t0 before being saved
- Fixed the issue that t0 was modified unexpectedly before being saved

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2023-08-09 01:07:11 -04:00
Meco Man c6a2f5b7bd rt_hw_cpu_shutdown: implement default weak function
and remvoe duplicated default functions in each cpu/bsp level
2023-08-08 22:34:25 -04:00
xqyjlj d23dd56692 🐞 fix(ktime): fix wrong boottime
因为tick从中断到设置中间的时延特别大,因此暂不采用tick做基准时间,直接取gtime的cnt做基准时间
2023-07-27 11:35:29 +08:00
xqyjlj 0eb75ced70
[time]时钟框架重构 (#7794) 2023-07-17 20:11:58 +08:00
flyingcys c78f646891
[bsp]add cv1800b (#7753) 2023-06-30 00:05:55 +08:00
Liu,Yuan 1d8165851b
[risc-v][libcpu] 删去无用局部变量 (#7634) 2023-06-07 17:04:12 -04:00
Bernard Xiong 4b4c3c85f2
[atomic] add stdc atomic detection. (#7536) 2023-05-20 23:41:29 +08:00
Shell b7554a70d2
[libcpu][component][debug] add debug info for gdb (#7033) 2023-05-14 23:48:16 +08:00
flyingcys cbedb6b40b
[libcpu/risc-v/c906] add ioremap && default param (#7345) 2023-04-24 09:21:15 +08:00
Shicheng Chu 93f3cb30e4
[kernel] 将rt_thread结构体改为显式继承rt_object (#7131) 2023-04-04 09:06:27 -04:00
Yaochenger 38eb3fc40f
[utest][atomic]添加返回值测试 (#7124)
* [utest][atomic]添加返回值测试
2023-03-30 11:06:21 +08:00
Shell eec78d9f5d
[rt-smart] testcase & improvements for memory management (#7099)
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format & modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch
2023-03-30 08:25:15 +08:00
flyingcys 0cf3bcf495
[bsp]fix esp32_c3 compile error (#7107)
* fix rt_hw_interrupt_install return value

* add __rt_rvstack
2023-03-29 19:01:26 +08:00
Yaochenger de4f237482
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053)
* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构

* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
  * 1.规范代码风格
  * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试

---------

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
flyingcys a538b26858
[bsp] add bl808 lp core (#7069)
* Add riscv_32e support

* add bl808 lp core

* update README.md
2023-03-19 23:16:12 +08:00
flyingcys c11f5bb251
add bl60x/bl70x/bl61x/bl808 (#7063)
Co-authored-by: flyingcys <flyingcys!163.com>
2023-03-19 14:41:18 +08:00
Shell 18a14cc935
[rt-smart] move sys_cacheflush to lwp_syscall.c (#7048)
* [syscall] move sys_cacheflush to lwp_syscall.c

* [syscall] improve assertion

* [format] rename to rt_ctassert

* [debug] modified ct assertion on mm_page.c
2023-03-17 15:11:38 +08:00