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5 Commits

Author SHA1 Message Date
zhangjun
2d56a27c20 修改： ../../libcpu/risc-v/e310/context_gcc.S 
enable interrupt after return form rt_hw_context_switch
 2017-07-30 15:34:32 +08:00
zhangjun
3c51848d33 fix trap_entry 2017-07-29 15:37:20 +08:00
zhangjun
b80f83f360 modified: ../../libcpu/risc-v/e310/context_gcc.S 
fix open timer intrrupt
 2017-07-26 16:27:54 +08:00
zhangjun
98a6896cfa remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable(); 
it will lead to interrupt again in interrupt
 2017-07-26 16:07:01 +08:00
zhangjun
f147f3398a new bsp for risc-v 2017-07-16 20:37:03 +08:00