The mode permissions for character, block, and pipe devices were
previously set to 0777, which is overly permissive and not in line
with standard practice. This change reduces the permissions to 0666,
restricting execute permissions while still allowing read/write access.
Changes:
- Adjusted permissions for character/block/pipe devices from 0777 to 0666.
Signed-off-by: Shell <smokewood@qq.com>
The `LWP_CONSOLE_INPUT_BUFFER_SIZE` is a legacy config option for TTY
driver used in smart. Since the driver is updated, there's no dependency
of this option any more.
Changes:
- Removed unused Kconfig option `LWP_CONSOLE_INPUT_BUFFER_SIZE`
Signed-off-by: Shell <smokewood@qq.com>
In manual, the prototype of lseek is
`off_t lseek(int fd, off_t offset, int whence);`
where the return type is `off_t` but not ssize_t.
Signed-off-by: Shell <smokewood@qq.com>
The ofw parse should:
1. Check obj_name EQU the current node's rt_data.
2. Find the next object name.
3. goto "2" until obj_name EQU the cmp_cell's obj_name.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
When the driver request a API gets RT_NULL which return value is ptr,
they could not know why get a RT_NULL.
some API return RT_NULL, is not error internal maybe, it just not
supported for this platform, but the driver still could work ok,
the API can return (RT_NULL + -RT_EEMPTY) to driver.
on the other hand, the driver can do more behaviors by error no.
When the API return the -RT_EBUSY, driver can wait for a moment and retry.
When the API return the -RT_ENOSYS, driver can try the next mode or request's name.
Signed-off-by: GuEe-GUI <wusongjie@rt-thread.com>
PCI/PCIe have better performance and more devices support, such as
NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by
IOMMU that the virtualiztion and userspace driver will more safety.
PCI/PCIe device could hot plugging, no design modifications SoC required,
PCI/PCIe on Embedded SoC is popular now.
We make a simple framework to support them.
Feature Lists:
1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC.
2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC.
3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework.
4.Endpoint: a simple EP framework for PCI FPGA or NTB function.
5.OFW: we only support work on OFW SoC, ACPI support in the future maybe.
Host controller:
1. Common PCI host controller on ECAM.
2. Generic PCI host controller on ECAM.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
1. RT_FIELD_PREP: prepare a bitfield element.
2. RT_FIELD_GET: extract a bitfield element.
3. rt_offsetof: member offset of a struct
4. rt_upper_32_bits: high 32 bits of value.
5. rt_lower_32_bits: lower 32 bits of value.
6. rt_upper_16_bits: high 16 bits of value.
7. rt_lower_16_bits: lower 16 bits of value.
8. rt_max_t: fix type of max(...).
9. rt_ilog2: integer logarithm base 2.
Signed-off-by: GuEe-GUI <2991707448@qq.com>
This patch addresses the potential issue of uninitialized elements in
the argument vector returned by `lwp_get_command_line_args()`. The
previous implementation could leave `argv` in an inconsistent state
if certain errors occurred, leading to possible undefined behavior.
Changes:
- Replaced `rt_malloc()` with `rt_calloc()` to ensure `argv` is properly initialized.
- Added a consistent error handling path using `goto error_exit` to handle memory allocation failures and string copy errors.
- Ensured `lwp_free_command_line_args()` is called before returning on error, preventing potential memory leaks.
Signed-off-by: Shell <smokewood@qq.com>
Shell
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