d431f4b5f9
[libcpu][comtex-m7] enhancement hard fault exception handler.
2018-07-25 21:39:45 +08:00
6c39b2d54d
[libcpu][comtex-m4] enhancement hard fault exception handler.
2018-07-25 21:39:44 +08:00
a0fe71f78f
fixed get sp in HardFault_Handler. close #1646
2018-07-25 21:39:43 +08:00
944b0f1c94
fix annotation error
2018-06-13 15:04:31 +08:00
7a1f8ee1c4
[libcpu][arm][arm926] Using C header file to define stack and heap size.
2018-06-04 13:34:45 +08:00
dd1041bb7f
[libcpu]: fixed #1196 FPU FPCA issue.
2018-01-31 18:54:11 +08:00
fc7a5abc76
[libcpu]: add 8-byte alignment for arm architecture && optimize code format
2017-12-21 16:37:38 +08:00
336207ad31
[libcpu]: add 8-byte alignment for armv6 architecture
2017-12-21 15:35:48 +08:00
a4a85a28da
[libcpu]:optimize code format
2017-12-21 15:14:23 +08:00
e7b1786759
[libcpu]:optimize code format
2017-12-21 14:55:34 +08:00
15715692d2
[libcpu]: add 8-byte alignment for armv6 architecture
2017-12-21 10:13:47 +08:00
eb72d19179
[libcpu] add volatile for __asm.
2017-11-22 09:54:36 +08:00
2488624a18
[libcpu] add volatile for asm (" mcr ") or asm (" mrc ") instruct.
2017-11-22 09:54:27 +08:00
f6170a6e5b
[BSP] add i.MX 6UL BSP
2017-11-01 13:30:17 +08:00
6085f6826d
[bsp][at91sam9260] Fix the problem of the finsh function failure by using component initialization.
2017-10-19 23:46:17 +08:00
5e3b3b19a6
[BSP] change the type of cmd.
...
1. Change the type of cmd to 'int';
2. Remove RT_LWIP_USING_RT_MEM macro;
2017-10-16 13:23:03 +08:00
cb247e913f
update libcpu: cortex-m0 fault handlers always enable.
2017-09-01 10:22:55 +08:00
9bbc4e5e6b
update cortex-m libcpu: fixed compile error.
2017-08-23 16:13:51 +08:00
9b7303e511
update libcpu: ensure fault enable.
2017-08-18 11:12:58 +08:00
a74a2a25a8
Add libcpu/arm/am335x/context_iar.S file
2017-02-06 21:57:15 +08:00
4e95fdff4a
[BSP] Update VFP code in armv6.
...
committed by FH.
2016-05-20 14:20:34 +08:00
923594c7ab
[BSP] Enable VFP.
...
committed by FH.
2016-05-20 12:24:51 +08:00
43f68131ce
[BSP] Add fh8620 bsp from Shanghai Fullhan Microelectronics Co., Ltd.
...
FH8620 BSP
Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
All rights reserved
2016-04-18 13:52:39 +08:00
3983f39f34
Add iar compiler support for am335x.
2015-11-11 23:44:05 +08:00
3faca6d5df
[BSP] update stm32f7-disco
...
code cleanup.
2015-09-24 16:03:09 +08:00
2021f5a276
Add the license.
2015-09-04 21:58:08 +08:00
b71cb4c09d
Add dm365 porting.
2015-09-04 12:30:20 +08:00
af8a91457e
[bsp]add the stm32f74x bsp.
2015-08-07 13:30:13 +08:00
9fe3cbf76f
Align thread stack to 8 byte.
2015-06-05 19:14:08 +08:00
314379cc77
implement __user_initial_stackheap
2015-06-04 12:23:24 +08:00
be76b10be6
Align stack address to 8 byte.
2015-06-04 11:59:18 +08:00
1fa5711712
fixed assembly warnings.
2015-05-22 16:48:01 +08:00
73df162d3f
fixed assembly warnings.
2015-05-13 11:57:34 +08:00
4222677933
[libcpu][am335x] Fix the booting failure when enabling MMU
...
Since the 16 domains are configured as the client domains in
mmu_setttbase(), a Permission fault is generated if the XN bit
(Execute-never) is set in the short-descriptor translation table
(for section and supersection). This leads to the booting failure
when enabling MMU for beagleboard bsp. Here is log:
----------------------------------------------------------------
SD/MMC found on device 0
reading uEnv.txt
117 bytes read in 3 ms (38.1 KiB/s)
Loaded environment from uEnv.txt
Importing environment from mmc ...
Running uenvcmd ...
reading rtthread.bin
162624 bytes read in 24 ms (6.5 MiB/s)
\## Starting application at 0x80200000 ...
----------------------------------------------------------------
This commit removes the XN bit configuration in the section of the
short-descriptor translation table. The OS can be booted successfully
with applying this commit.
2015-05-11 10:36:11 +08:00
a13132b302
[libcpu][arm926] Optimize irq trap code.
2015-05-04 16:13:43 +08:00
49fa5c44d7
[libcpu][arm926] Optimize code
...
1. Combine code for IAR and GCC in file mmu.c and cpuport.c
2. Remove remap code in start_xxx.S. User should config MMU to map vector table to visual address 0x0
2015-04-22 11:19:50 +08:00
175e357ace
[libcpu][arm926] Remove unused SPSR register PUSH/POP when os switch thread.
2015-04-16 14:13:43 +08:00
cf3d639fcb
[libcpu][arm926] Define vector table start at BSP/{board}/platform/ assemble INC files.
2015-04-16 10:35:12 +08:00
6aa242645f
1. [bsp][sam9260] Fix the bug that auto reset after boot 20s. Disable watchdog in rt_lovel_level_init function.
...
2. [bsp][sam9260] Modify SCONS scripts to support IAR tool chain.
3. [bsp][sam9260] Move link strips in to folder link_scripts.
4. [libcpu][arm926] Add copy right to source file and format code.
2015-04-15 16:13:30 +08:00
39452b67b0
1. [cpu] split ARM926 cpu code from AT91SAM9260 BSP
2015-04-14 21:56:34 +08:00
0b5958d700
Fix compile warning:
...
..\..\libcpu\arm\cortex-m3\context_rvds.S(207):
warning: A1581W: Added 2 bytes of padding at address 0xd6
2015-03-09 09:31:23 +08:00
62af08370b
Merge pull request #2 from RT-Thread/master
...
sync
2014-09-20 01:19:42 +08:00
267c61ebce
[libcpu] Add builtin ffs implementation for Cortex-M4.
2014-09-11 12:51:33 +08:00
fd6ef4b235
[libcpu]am335x edit vector
...
vector_undef and vector_dabt
2014-08-12 18:26:22 +08:00
2c47f2e683
Fix some spell error;
2014-07-31 13:59:25 +08:00
97fb91dcc6
bsp: add zynq7000
2014-06-27 14:12:36 +08:00
2b7be29cad
[bsp/rva8] enable group{0,1} interrupt forwarding in gic initialization
...
When RT-Thread is running stand alone, it forgot to enable the
distributor of GIC.
2014-04-08 11:54:03 +08:00
c0f0c2322f
[libcpu/arm] remove useless cpsr updating in rt_hw_context_switch_to
...
This piece of code will enable the interrupt early before switching to
the first thread. Although it is harmless, but not prefect.
2014-04-08 11:24:04 +08:00
28f11fdd7b
[vmm] add realview-pb-a8 VMM support
2014-04-03 17:59:14 +08:00
9382a7105f
add CM_PER_UARTx_CLKCTRL
2014-01-11 15:14:36 +08:00
aozima
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