5 Commits

Author	SHA1	Message	Date
Shell	e991be9c51	[smart][risc-v/libcpu] port rv64 cpu code (#6704) ... * [risc-v/libcpu] porting Smart & RTOS * [fix] rv64 plic * [risc-v/rv64] remove macro in rtdef	2022-12-10 22:16:42 +08:00
guo	ecf2d82159	sync branch rt-smart. (#6641) ... * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>	2022-12-03 12:07:44 +08:00
rewine	825b9ffbc3	[libcpu/risc-v/virt64]: fix parameter for call handle_trap (#6042)	2022-07-10 17:48:57 +08:00
bigmagic	b7c7c7f4de	Support for running with M-Mode	2021-05-21 17:10:07 +08:00
lizhirui	5036816967	add qemu-riscv-virt64 bsp ... add qemu-riscv-virt64 bsp	2021-05-18 09:57:25 +08:00