f6f570df74
Merge branch 'master' into shell/rv64-tick
2024-07-17 09:39:54 +08:00
d8294de640
bsp:cvitek: add pinmux for adc
...
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
2c85bcb463
bsp:cvitek: add pinmux for spi
...
Board level pin available info:
duo & duo256:
NAME SPI CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP6 SPI2_SCK PWR_GPIO[23] SD1_CLK__SPI2_SCK
GP7 SPI2_SDO PWR_GPIO[22] SD1_CMD__SPI2_SDO
GP8 SPI2_SDI PWR_GPIO[21] SD1_D0__SPI2_SDI
GP9 SPI2_CS_X PWR_GPIO[18] SD1_D3__SPI2_CS_X
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
51825a5b5c
bsp:cvitek: add pinmux for pwm
...
Board level pin available info is summarized and list here for memo:
Duo:
NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
PWM-1
GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4
GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4
GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5
GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5
GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6
GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7
PWM-2
GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8
GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9
GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10
GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11
Duo256:
NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
PWM-1
GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4
GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4
GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5
GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5
GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6
GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6
GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7
GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7
PWM-2
GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8
GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9
GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10
GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
114e143d56
bsp:cvitek: add pinmux for uart
...
Board level UART pinmux summary, following capability
should be controlled by pinname whitelist.
Duo:
NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX
GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX
GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX
GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX
GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX
GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX
GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX
GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX
GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX
GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX
GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX
GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX
GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX
GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX
Duo 256m:
NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX
GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX
GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX
GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX
GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX
GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX
GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX
GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX
GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX
GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX
GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX
GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX
GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX
GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX
Note: this patch also update the .config and rtconfig.h
because this patch modify some configuration items's name,
for example: RT_USIMG_UART0 -> BSP_USING_UART0.
FIXME: only handle RISC-V related, no ARM.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
e1eb3d3217
bsp:cvitek: add pinmux for i2c
...
Based on new pinmux framework, add configuration for uart.
Board level pin available info is summarized and should be
controlled by pin whitelist.
Duo
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL
GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo256m
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL
GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo S(Note, we have not supported duo S, just list for memo)
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL
J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL
J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA
J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL
J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL
J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA
J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA
J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL
J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL
J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA
J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 18:29:17 +08:00
d8d0af9143
bsp:cvitek: add calibration for adc
...
The ADC controller needs to be calibrated during the initialization
phase, otherwise the measured voltage value will be inaccurate.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-16 11:47:22 +08:00
a63c07fd75
bsp: cvitek: new design for pinmux
...
In the new design, we require the user to manually enter the
PinName (as a string) in menuconfig instead of being given
menu items to select.
The original method will lead to too many menu item-related
macros being defined in the code, causing ifdef and other
codes scatter everywhere in the driver code, which is
inconvenient to maintain.
The new design adds a pinmux driver module to manage the
multiplexing of pins. This patch provides this driver module.
P.S., the reason why users are allowed to specify pinname
in a string instead of the pin number is mainly because
the technical manual provided by the SOC manufacturer
does not have numbers for some pins, only names.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Yuanjie He <943313837@qq.com>
Reviewed-by: Shell <smokewood@qq.com>
2024-07-16 11:37:23 +08:00
80668e0ba2
bsp:cvitek: revert add i2c pinmux config for c906
...
The contents of the SOC type part in the Kconfig configuration
are retained, and other parts related to I2C pin multiplexing
selection have been rolled back.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Yuanjie He <943313837@qq.com>
Reviewed-by: Shell <smokewood@qq.com>
2024-07-16 11:37:23 +08:00
96ba787e25
Bugfix/fix weak handle trap in riscv common crash rv64 trap handling ( #9189 )
...
* [bsp][hpmicro] add weak handle_trap implementation
- added weak handle_trap implementation
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
* [libcpu][risc-v][common] remove weak handle_trap function
- removed weak handle_trap function from trap_common.c
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
---------
Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2024-07-15 17:51:32 +08:00
65ffe4e13e
[libcpu/rv64] feat: unify tick.c
...
The changes unify the tick.c implementations for all risc-v64
architectures, leveraging the CPUTIME feature. This refactoring was
necessary to streamline the codebase, and ensure consistent timer
handling across different platforms.
Changes:
- Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues.
- Updated .config for BSPs to update `CPUTIME_TIMER_FREQ`
- Updated header of for API `riscv_cputime_init`
- Initialized riscv timer on `rt_hw_tick_init`
- Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`:
- Replaced direct use of `rdtime` with `clock_cpu_gettime`.
- Removed redundant timer frequency definitions.
- Added static assertions to check the value of `CPUTIME_TIMER_FREQ`.
- Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`.
- Integrated `ktime` support for tick initialization.
Signed-off-by: Shell <smokewood@qq.com>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-15 12:06:39 +08:00
df948ad603
[STM32][SPI]移除内部编写的延时函数使用统一延时接口
2024-07-12 17:48:17 +08:00
6180dabab3
[bsp/cvitek]将eth驱动中地址类型改为指针以适应ioremap ( #9137 )
...
ioremap后地址可能超32位
2024-07-11 10:28:02 +08:00
befa478073
[bsp][stm32_rt_spark]Add README_EN
2024-07-09 20:18:53 +08:00
b73396681a
[bsp/allwinner] feat: porting to RT_USING_DEVICE_OPS ( #9142 )
...
* [bsp/allwinner] feat: porting to RT_USING_DEVICE_OPS
This patch ports the codebase to use the RT_USING_DEVICE_OPS structure,
which is required by v5.1.0 Smart kernel, improves modularity and makes
it easier to manage device operations by consolidating them into a
single structure, enhancing maintainability and future scalability.
Changes:
- Added RT_USING_DEVICE_OPS conditionals to partition.c and drv_sdmmc.c.
- Defined rt_device_ops structures for partition and sdmmc drivers.
- Updated device initialization to use the ops structure if defined.
- Replaced direct function calls with rt_dev_control, rt_dev_read, and
rt_dev_write macros where applicable.
- Removed redundant us_delay function from os.c.
Signed-off-by: Shell <smokewood@qq.com>
* feat: update configuration
* feat: fixup compiler warning
---------
Signed-off-by: Shell <smokewood@qq.com>
2024-07-09 13:35:03 +08:00
66ff62413e
document: add ref to gpio pinout
2024-07-08 22:09:35 +08:00
04b77e409e
[bsp][NXP]Fix .md picture mistakes
2024-07-08 22:06:53 +08:00
b47b6df927
[bsp][Infineon]&[NXP] Add README_EN
2024-07-08 22:06:53 +08:00
b171877139
[bsp][qemu]修复qemu-a9使能lcd缺失依赖问题.
2024-07-07 22:24:09 +08:00
776764c4d6
[bsp/cvitek/eth]解决编译警告
2024-07-04 00:33:32 +08:00
5f70f974d5
[bsp][stm32]Increase the serial_v1 tx timeout.
2024-07-04 00:33:06 +08:00
017c31a062
[bsp/cvitek]解决eth编译报错
2024-07-02 22:54:58 +08:00
8487e774a3
[bsp][stm32]fix stm32h7 spi transmit fail probelm.
2024-07-02 22:54:23 +08:00
1e3efd4937
[rtduino][pico] update README.md
2024-06-30 22:30:15 +08:00
cc853de5f3
Update cherryusb to v1.3.1 ( #9122 )
...
* fix(hpmicro): remove duplicate usb variable
* update(cherryusb): update to v1.3.1
2024-06-30 08:01:51 +08:00
df715100f2
[BSP][HC32]add lckfb-hc32f4a0-lqfp100 ( #9119 )
...
* -以ev_hc32f4a0_lqfp176为模板进行修改
* -修改对应引脚
* -更新readme
* -update readme
* -添加 lckfb-hc32f4a0-lqfp100
2024-06-28 23:41:31 +08:00
099e24951c
[BSP][nxp]增加wifi_weather_sample.c ( #9118 )
...
* [BSP][nxp]增加wifi_weather_sample.c
* [BSP][nsp]增加wifi_weather_sample.c
2024-06-28 22:37:22 +08:00
840eef1124
[bsp][nxp] Delete mcxn947 sdk unused path.
2024-06-27 23:04:56 +08:00
e69a7ccfa3
[bsp][nxp] Update mcxn236 & mcxn947 LFLAGS config.
2024-06-27 23:04:56 +08:00
76e123d8ca
[bsp/stm32f407-lckfb-skystar] 天空星高配版的FLASH从GD25Q32升级为W25Q128 ( #9108 )
...
* -更新芯片型号和板子型号
* -天空星目前只有青春版（没有贴外部flash），高配版（有贴外部flash）正在生产，所贴的SPI FLASH 从GD25Q32升级为W25Q128。
2024-06-27 23:04:35 +08:00
6ea7466d89
[file]modify a9/launch.json
2024-06-27 23:03:54 +08:00
eb1d6913b0
[bsp/stm32f103-100ask-mini] extend ROM from 64KB to 128KB
2024-06-27 00:11:18 +08:00
d342450594
[bsp][stm32][uart V1]优化驱动实现
...
* 增加putc超时处理机制,防止死循环
* 优化TX中断初始化与卸载
* 添加TX中断方式实现
2024-06-27 00:11:18 +08:00
7523f40701
[bsp][nxp][frdm-mcxn236] remove sdio and eth
...
there's no sdio/eth in HW, remove it
2024-06-26 23:54:42 +08:00
63578802b9
[bsp][nxp][frdm-mcxn236] fix SW btn
...
This is the SW2 button, a.k.a wakeup button on the board. Another
choice is SW3 a.k.a ISP button which is connected to P0_6.
2024-06-26 23:54:42 +08:00
0f8f0620c3
[bsp][nxp] s/libraries/Libraries
...
The upper/lower case matters under *nix
2024-06-26 23:54:42 +08:00
071b3d9244
[bsp]: fix bugs of cvitek and pico drivers
2024-06-26 20:28:29 +08:00
bc3afab2c9
[bsp][stm32]Optimize ADCs and fix some bugs
2024-06-26 20:26:52 +08:00
f687ace6ef
bsp/cvitek update readme
2024-06-26 20:22:05 +08:00
4d00fd19da
[bsp][nxp mcxn236]Delete unused code with pin_mux.c .
2024-06-26 17:25:18 +08:00
b785ef9ed7
[libcpu][aarch64]memory setup using memblock ( #9092 )
...
* memory setup using memblock
* map pages later
2024-06-26 14:36:49 +08:00
e390290482
[bsp/mcxn236]Port gcc&mdk project.
2024-06-26 01:22:15 +08:00
7ae476dcf2
[bsp/Cvitek]去除shell脚本中的'\r' ( #9097 )
...
* [bsp/cvitek]去除脚本中'\r'
* [bsp/cvitek]删除脚本中的'\r'
* Update combine-fip.sh
2024-06-26 01:21:18 +08:00
8524781cb3
[bsp][mcxn236] Add software i2c driver.
2024-06-26 01:20:59 +08:00
053373c3ac
adapter frdm-mcxn236 iar project ( #9083 )
...
* adapter frdm-mcxn236 iar project
* formate MCXN236 bsp
2024-06-25 01:33:30 +08:00
189f5ed8a9
[chip flash] add drv_flash_l1.c for stm32l1xxx ( #9077 )
...
* [chip flash] add drv_flash_l1.c for stm32l1xxx
* [fix] Modified the SConscript file to support building for STM32L1xxx.
2024-06-25 01:29:36 +08:00
5e04d8b3c1
[bsp]Fix the problem of stm32l431 build ci failure
2024-06-24 13:53:10 +08:00
0f9a4fa032
fixup: building failure in bsp cause by hal ( #9086 )
...
fixup: hal
2024-06-23 21:28:26 +08:00
af5bd68c58
野火启明6m5驱动完善
2024-06-20 21:42:11 +08:00
f0e6d772f3
mkdist和sdk_dist支持kconfiglib语法
2024-06-20 14:40:42 +08:00
Shell
Chen Wang
Fan Yang
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sakumisu
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Abner
andeyqi
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Meco Man
Jisheng Zhang
yiyi
LTreeshu
zms123456
hengchuan.qi
Chasel
ShaquilleLiu
latercomer