Commit Graph

107 Commits

Author SHA1 Message Date
flyingcys cbedb6b40b
[libcpu/risc-v/c906] add ioremap && default param (#7345) 2023-04-24 09:21:15 +08:00
Shicheng Chu 93f3cb30e4
[kernel] 将rt_thread结构体改为显式继承rt_object (#7131) 2023-04-04 09:06:27 -04:00
Yaochenger 38eb3fc40f
[utest][atomic]添加返回值测试 (#7124)
* [utest][atomic]添加返回值测试
2023-03-30 11:06:21 +08:00
Shell eec78d9f5d
[rt-smart] testcase & improvements for memory management (#7099)
* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format & modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch
2023-03-30 08:25:15 +08:00
flyingcys 0cf3bcf495
[bsp]fix esp32_c3 compile error (#7107)
* fix rt_hw_interrupt_install return value

* add __rt_rvstack
2023-03-29 19:01:26 +08:00
Yaochenger de4f237482
[atomic]添加arm与risc-v下的常用原子操作函数 (#7053)
* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构

* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
  * 1.规范代码风格
  * 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试

---------

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2023-03-23 20:06:50 +08:00
flyingcys a538b26858
[bsp] add bl808 lp core (#7069)
* Add riscv_32e support

* add bl808 lp core

* update README.md
2023-03-19 23:16:12 +08:00
flyingcys c11f5bb251
add bl60x/bl70x/bl61x/bl808 (#7063)
Co-authored-by: flyingcys <flyingcys!163.com>
2023-03-19 14:41:18 +08:00
Shell 18a14cc935
[rt-smart] move sys_cacheflush to lwp_syscall.c (#7048)
* [syscall] move sys_cacheflush to lwp_syscall.c

* [syscall] improve assertion

* [format] rename to rt_ctassert

* [debug] modified ct assertion on mm_page.c
2023-03-17 15:11:38 +08:00
Shell 2394e75265
[libcpu/risc-v] support noncached normal memory (#7051)
* [libcpu/risc-v] support noncached normal memory

* [mm] check before dereference in _fetch_page

* [mm] add comments on ioremap

* [ioremap] report more info on failed
2023-03-16 10:26:55 +08:00
zilong 50e1f6327d
[libcpu/riscv/virt64] fix (#5979) (#7040) 2023-03-11 12:34:14 +08:00
chenhy0106 f6847af0cd
[libcpu/riscv/c906] fix "next_asid" type error (#7031)
MAX_ASID最大为0x10000,在next_asid==MAX_ASID时进入下一个generation。因此next_asid不能只有16位,否则将不能进入下一个generation。修改rt_uint16_t为rt_uint32_t。
2023-03-09 07:25:54 -05:00
Yaochenger cfc6bf9b12 [libcpu/risc-v]更新移植readme 2023-03-07 22:04:26 -05:00
Yaochenger 922e6e40d3
[libcpu/risc-v]迁移libcpu/risc-v/e310与rv32m1文件中内容至bsp (#7015) 2023-03-05 19:43:58 -05:00
Yaochenger 95540854a6
[libcpu/riscv]迁移libcpu/riscv/ch32中文件至bsp (#7004) 2023-03-02 09:17:43 -05:00
Yaochenger fc2e122ee2 [libcpu/risc-v]迁移libcpu/risc-v/hpmicro中的文件至bsp 2023-03-02 09:16:59 -05:00
Yaochenger 6aa2445522 [libcpu/risc-v]移除bumblebee文件夹与nuclei文件夹中的内容至bsp 2023-03-02 09:16:12 -05:00
Yaochenger 892ef3dc5b
[libcpu/risc-v]将cv32e40p文件夹中文件移至BSP (#7002) 2023-03-01 21:34:35 -05:00
Yaochenger b9e4fcfc68
[libcpu][riscv]整合libcpu/riscv中的移植文件 提供一份公共代码于common (#6941)
整合libcpu/riscv中的移植文件 提供一份公共代码于common

在提交本pr时,除hpmicro的内核,rv32内核bsp已完成去除大部分的冗余,大部分代码采用common中的实现。本pr的作用是进一步统一common中的文件,从而提供一份公用代码,新移植的RV32内核的BSP可以全部使用common代码。

- 在common中提供一份公用文件:interrupt_gcc.S
- 修改原有的文件,将原有的中断中上下文切换代码替换为interrupt_gcc.S
- 基于上述修改,修改仓库中risc-v内核的BSP与移植相关的部分 (主要包含中断入口函数 中断栈等)
- 在common中提供一份公用文件:trap_common.c;提供统一中断入口函数,中断入口函数初始化,中断入口注册等函数,并完善异常时的信息输出

- 在common中提供一份公用文件:rt_hw_stack_frame.h;将栈帧结构体剥离,供用户使用

- 在上述工作完成后,在上述工作的基础上测试仓库中risc-v内核的BSP

- 完善函数中的命名,完善中断栈的获取

- 提供一份详细的基于现有common文件的移植指南

  #### 在什么测试环境下测试通过 

- 1.CH32V307V-R1-R0
- 2.CH32V208W-R0-1V4
- 3.HPM6750EVKMINI
- 4.GD32VF103V-EVAL
- 5.qemu(CORE-V-MCU )

> 与上述开发板使用同样芯片的BSP均测试通过

在CH32V307V-R1-R0与HPM6750EVKMINI上基于现有移植文件进行多线程复杂场景下的长时间测试,测试过程系统运行正常。
2023-03-01 01:32:43 -05:00
Shell 382e9bcac7
[rt-smart] handling kernel from accessing unmapped user stack (#6957)
[rt-smart] handling kernel from accessing unmapped user stack
2023-02-24 14:52:16 +08:00
wangxiaoyao 484a0d602e [fixup] add cache maintenance ops;
fix bugs on cache maintenance when starting user app
2023-02-21 08:48:49 +08:00
Shell 2d09749086
[rt-smart] PV_OFFSET as a variable (#6904)
* [rt-smart/mem] remove pv_offset

* [rt-smart] list kernel space command

* [rt-smart] restore ioremap region

* [revert] restore kernel space isolation

* [rt-smart/pv_off] code format

* [rt-smart] add get_pvoff()

* [pvoffset] pvoff as constant for C codes

* [pvoff] pvoff as interfaces
2023-02-14 23:08:32 +08:00
chenhy0106 9db73a47c4
为c906添加asid支持 (#6870)
* [rt-smart] asid for c906
2023-01-28 13:08:40 -05:00
Shell f0dadcb3c3
[rt-smart] porting c906 and D1s to mm (#6848)
* [rv64/bsp] porting to mm

* [mm] report more info for debugging

* [fix] code format

* [libcpu/c906] porting to RTOS

* [fix] using rtdbg api

* [fix] add return

* [fix] report more information for debugging

* [fix] use assert 0 for unrecoverable error
2023-01-16 08:24:03 +08:00
Meco Man 9bc68d26a4 format Kconfig and sconscript 2023-01-08 22:52:13 -05:00
Shell 7450ef6c4d
[rt-smart] kernel virtual memory management layer (#6809)
synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes
2023-01-08 21:08:55 -05:00
flyingcys 98a997c57e
[bsp]add new bsp-bl808 (#6824)
* add new bsp-bl808

* support ARCH_RISCV_FPU_S && update rtconfig.py
2023-01-07 02:03:21 -05:00
Yaochenger b99769f686
[libcpu][riscv]移除ch32中的冗余文件,使用common下的文件 (#6813)
* [libcpu][riscv]移除ch32中的冗余文件,使用common下的文件

* 修正cpuport.h宏定义

* 规范宏定义格式
2023-01-04 21:06:09 -05:00
Yaochenger f2a66e122f [libcpu][riscv]移除cv32e40p中部分文件,采用common中的文件 2023-01-02 16:42:18 -05:00
Yaochenger 882a0af94e [libcpu][riscv] 添加宏用于区别是否开启FPU,更新ch32v208v-r0 ->ch32v208w-r0,更新注释 2022-12-28 18:47:39 -05:00
Yaochenger b77241935c
[bsp][ch32v208]添加ch32v208BSP,合并libcpu/riscv 中ch系列的port文件 (#6780)
【1】添加ch32v208-r0 bsp
【2】合并libcpu/riscv 下ch系列mcu的port文件
2022-12-27 13:24:02 -05:00
linshire c930b4f623
[ch32]对接了rt_hw_context_switch_interrupt接口 (#6749)
* 对接了rt_hw_context_switch_interruptC(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)接口

* Update libcpu/risc-v/ch32v1/cpuport.c

Co-authored-by: Man, Jianting (Meco) <920369182@qq.com>
2022-12-22 09:34:36 +08:00
guo 68ca9f07a6
[rt-smart] 弱化 RT_USING_LWP,使用 RT_USING_SMART 作为宏配置 (#6740)
* [dfs] sync cromfs

* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration

* [format] fix some format issue.
2022-12-16 18:38:28 +08:00
Man, Jianting (Meco) 99bdf978d7
[rtdef] use lower-case to define attributes (#6728)
* [rtdef] rename RT_WEAK attribute as rt_weak

* [rtdef] rename RT_USED attribute as rt_used

* [rtdef] rename RT_SECTION attribute as rt_section

* [rtdef] rename ALIGN attribute as rt_align

* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support
2022-12-11 13:12:03 -05:00
linshire 8f9198eb99
对接了rthw.h的接口,修复了不能编译的问题 (#6722) 2022-12-10 23:04:26 +08:00
Shell e991be9c51
[smart][risc-v/libcpu] port rv64 cpu code (#6704)
* [risc-v/libcpu] porting Smart & RTOS
* [fix] rv64 plic
* [risc-v/rv64] remove macro in rtdef
2022-12-10 22:16:42 +08:00
Yaochenger 9d8da76543
[bsp] add core-v-mcu bsp (#6705)
* add core-v-mcu bsp

* 规范bsp格式 添加readme

* 修改readme

Co-authored-by: 1516081466@qq.com <ws051000>
2022-12-08 15:01:37 -05:00
guo ecf2d82159
sync branch rt-smart. (#6641)
* Synchronize the code of the rt mart branch to the master branch.
  * TTY device
  * Add lwP code from rt-smart
  * Add vnode in DFS, but DFS will be re-write for rt-smart
  * There are three libcpu for rt-smart:
    * arm/cortex-a, arm/aarch64
    * riscv64

Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
Fan Yang c1b22ede30
Add BSP for HPM6750EVK and HPM6750EVKMINI (#6374)
* Add CANFD support and correct typos

- Added CANFD required fields to can.h
- Fixed typos in can.h and can.c
- Corrected all the projects affected by the typo
- Fixed wrong line-ending in some affected can driver files

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

* update

* bsp: support boards from hpmicro

- Supported HPM6750EVKMINI
- Supported HPM6750EVK

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
Co-authored-by: Meco Man <920369182@qq.com>
2022-09-06 00:48:16 -04:00
liyangyang d887d6eb19 fix scons 2022-08-22 23:39:39 -04:00
liyangyang 9b750eba84 libcpu 支持 ch32v3系列单片机 2022-08-22 23:39:39 -04:00
emuzit c802fcdcf8
WCH CH569W-R0-1v0 evt board bsp port, first version (#6167)
WCH CH569W-R0-1v0 evt board bsp port, first version

dev/test under Ubuntu 20.04
toolchain from MounRiver_Studio_Community_Linux_x64_V120

tested drivers : SysTick, gpio, gpio interrupt, uart1 (RX interrupt, TX polling)

libcpu/risc-v/SConscript :
group includes rtconfig.CPU only if folder exists

libcpu/risc-v/common/cpuport.c/rt_hw_context_switch_interrupt() :
make it RT_WEAK for customization
2022-07-30 02:10:51 -04:00
rewine 825b9ffbc3
[libcpu/risc-v/virt64]: fix parameter for call handle_trap (#6042) 2022-07-10 17:48:57 +08:00
thewon86 f5b0bfd3f4 uniform code writing-disable interrupt 2022-04-20 14:22:43 +08:00
blta 99526cc047 [bsp/ch32v103r-evt] add ch32v103r-evt bsp
feat: move MRS demo source to bsp and libraries folder

feat: update Sconscript

feat: modify SConstruct in the bsp

feat: use the rtconfig.py of gd32vf103v-eval bsp to modify

feat: use the MRS's rtconfig.h temoporarily

feat: update Kconfig files

feat: use the MRS's .ld and rename as link.lds

feat: add ch32v1 porting folder

perf: remove board/system_ch32v10x.c

fix: define SOC_ARM_SERIES_CH32V103 in rtconfig.h

fix: add some neccessary macros in rtconfig.h

perf: use the menuconfig to generate rtconfig.h

feat: add readme.md

fix: correct the bad encode in main.c

fix: include board.h in main.c

perf: check and update README.md

perf: remove ch32f10x_port_cn.md

feat: ignore the standard libraries's CI checking

feat: add sdk_dist.py

fix: correct some style errors again

perf: simply the board/kconfig

fix: format ch32v103r-evt

fix: format drvs and libcpu
2022-04-06 11:06:55 +08:00
blta ce602a6e4a
[libcpu/risc-v] 修复risc-v scons编译中间文件不能输出到build/kernel/libcpu目录问题 (#5736) 2022-03-29 22:18:05 +08:00
Meco Man 563e49890c [asm] 解决tab和空格混用的问题 2022-01-20 20:57:35 +08:00
jihongbin 7d07c61a47 [fix][libcpu][riscv][t-head] fix rt_hw_interrupt_disable/rt_hw_interrupt_enable bug
使用不同的优化等级会出现不同的效果
当使用-O0 等级时,无法正确得到关闭中断之前的状态

Using different optimization levels will have different effects
When the - o0 level is used, the state before the shutdown interrupt cannot be obtained correctly
2021-11-04 10:36:11 +08:00
BernardXiong be2dec978d [BSP] fix the compiling issue for qemu-riscv64 2021-10-19 15:00:46 +08:00
BernardXiong 6b66207048 [libcpu] fix s-mode issue 2021-10-19 14:35:22 +08:00