[bsp][renesas] Add preliminary ethernet support. (#7204)
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GitHub
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commit
ff12c58bf8
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@ -50,6 +50,9 @@ if GetDepend(['BSP_USING_ONCHIP_FLASH']):
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if GetDepend(['BSP_USING_PWM']):
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src += ['drv_pwm.c']
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if GetDepend(['BSP_USING_ETH']):
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src += ['drv_eth.c']
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if GetDepend(['BSP_USING_CAN']):
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src += ['drv_can.c']
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@ -0,0 +1,444 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-19 SummerGift first version
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* 2018-12-25 zylx fix some bugs
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* 2019-06-10 SummerGift optimize PHY state detection process
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* 2019-09-03 xiaofan optimize link change detection process
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*/
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#include "drv_config.h"
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#include "drv_eth.h"
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#include <hal_data.h>
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#include <netif/ethernetif.h>
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#include <lwipopts.h>
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/*
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* Emac driver uses CubeMX tool to generate emac and phy's configuration,
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* the configuration files can be found in CubeMX_Config folder.
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*/
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/* debug option */
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//#define ETH_RX_DUMP
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//#define ETH_TX_DUMP
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#define MINIMUM_ETHERNET_FRAME_SIZE (60U)
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#define ETH_MAX_PACKET_SIZE 1514
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
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//#define DRV_DEBUG
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#define LOG_TAG "drv.eth"
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#ifdef DRV_DEBUG
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#define DBG_LVL DBG_LOG
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#else
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#define DBG_LVL DBG_INFO
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#endif /* DRV_DEBUG */
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#include <rtdbg.h>
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#define MAX_ADDR_LEN 6
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#undef PHY_FULL_DUPLEX
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#define PHY_LINK (1 << 0)
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#define PHY_100M (1 << 1)
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#define PHY_FULL_DUPLEX (1 << 2)
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struct rt_ra6m3_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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#ifndef PHY_USING_INTERRUPT_MODE
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rt_timer_t poll_link_timer;
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#endif
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/* interface address info, hw address */
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rt_uint8_t dev_addr[MAX_ADDR_LEN];
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};
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static rt_uint8_t *Rx_Buff, *Tx_Buff;
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//static ETH_HandleTypeDef EthHandle;
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static struct rt_ra6m3_eth ra6m3_eth_device;
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#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
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#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
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static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
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{
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unsigned char *buf = (unsigned char *)ptr;
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int i, j;
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for (i = 0; i < buflen; i += 16)
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{
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rt_kprintf("%08X: ", i);
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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rt_kprintf("%02X ", buf[i + j]);
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else
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rt_kprintf(" ");
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rt_kprintf(" ");
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
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rt_kprintf("\n");
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}
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}
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#endif
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extern void phy_reset(void);
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/* EMAC initialization function */
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static rt_err_t rt_ra6m3_eth_init(rt_device_t dev)
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{
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fsp_err_t res;
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res = R_ETHER_Open(&g_ether0_ctrl, &g_ether0_cfg);
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if (res != FSP_SUCCESS)
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LOG_W("R_ETHER_Open failed!, res = %d", res);
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return RT_EOK;
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}
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static rt_err_t rt_ra6m3_eth_open(rt_device_t dev, rt_uint16_t oflag)
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{
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LOG_D("emac open");
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return RT_EOK;
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}
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static rt_err_t rt_ra6m3_eth_close(rt_device_t dev)
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{
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LOG_D("emac close");
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return RT_EOK;
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}
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static rt_ssize_t rt_ra6m3_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
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{
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LOG_D("emac read");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_ssize_t rt_ra6m3_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
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{
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LOG_D("emac write");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t rt_ra6m3_eth_control(rt_device_t dev, int cmd, void *args)
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{
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switch (cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if (args)
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{
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SMEMCPY(args, ra6m3_eth_device.dev_addr, 6);
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}
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else
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{
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return -RT_ERROR;
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}
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/* ethernet device interface */
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/* transmit data*/
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rt_err_t rt_ra6m3_eth_tx(rt_device_t dev, struct pbuf *p)
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{
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fsp_err_t res;
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struct pbuf *q;
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uint8_t *buffer = Tx_Buff;
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uint32_t framelength = 0;
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uint32_t bufferoffset = 0;
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uint32_t byteslefttocopy = 0;
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uint32_t payloadoffset = 0;
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bufferoffset = 0;
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LOG_D("send frame len : %d", p->tot_len);
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/* copy frame from pbufs to driver buffers */
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for (q = p; q != NULL; q = q->next)
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{
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/* Get bytes in current lwIP buffer */
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byteslefttocopy = q->len;
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payloadoffset = 0;
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/* Check if the length of data to copy is bigger than Tx buffer size*/
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while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE)
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{
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/* Copy data to Tx buffer*/
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SMEMCPY((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
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byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
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payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
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framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
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bufferoffset = 0;
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}
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/* Copy the remaining bytes */
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SMEMCPY((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
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bufferoffset = bufferoffset + byteslefttocopy;
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framelength = framelength + byteslefttocopy;
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}
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#ifdef ETH_TX_DUMP
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dump_hex(buffer, p->tot_len);
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#endif
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#ifdef ETH_RX_DUMP
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if (p)
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{
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LOG_E("******p buf frame *********");
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for (q = p; q != NULL; q = q->next)
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{
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dump_hex(q->payload, q->len);
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}
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}
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#endif
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res = R_ETHER_Write(&g_ether0_ctrl, buffer, p->tot_len);//>MINIMUM_ETHERNET_FRAME_SIZE?p->tot_len:MINIMUM_ETHERNET_FRAME_SIZE);
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if (res != FSP_SUCCESS)
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LOG_W("R_ETHER_Write failed!, res = %d", res);
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return RT_EOK;
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}
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/* receive data*/
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struct pbuf *rt_ra6m3_eth_rx(rt_device_t dev)
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{
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struct pbuf *p = NULL;
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struct pbuf *q = NULL;
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uint32_t len = 0;
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uint8_t *buffer = Rx_Buff;
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fsp_err_t res;
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res = R_ETHER_Read(&g_ether0_ctrl, buffer, &len);
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if (res != FSP_SUCCESS)
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LOG_D("R_ETHER_Read failed!, res = %d", res);
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uint32_t bufferoffset = 0;
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uint32_t payloadoffset = 0;
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uint32_t byteslefttocopy = 0;
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LOG_D("receive frame len : %d", len);
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if (len > 0)
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{
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/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
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p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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}
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#ifdef ETH_RX_DUMP
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if (p)
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{
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dump_hex(buffer, p->tot_len);
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}
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#endif
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if (p != NULL)
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{
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bufferoffset = 0;
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for (q = p; q != NULL; q = q->next)
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{
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byteslefttocopy = q->len;
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payloadoffset = 0;
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/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
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while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE)
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{
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/* Copy data to pbuf */
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SMEMCPY((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
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byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
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payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
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bufferoffset = 0;
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}
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/* Copy remaining data in pbuf */
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SMEMCPY((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
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bufferoffset = bufferoffset + byteslefttocopy;
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}
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}
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#ifdef ETH_RX_DUMP
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if (p)
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{
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LOG_E("******p buf frame *********");
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for (q = p; q != NULL; q = q->next)
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{
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dump_hex(q->payload, q->len);
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}
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}
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#endif
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return p;
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}
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static void phy_linkchange()
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{
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static uint32_t phy_speed = 0;
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uint32_t phy_speed_new = 0;
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fsp_err_t res;
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uint32_t p_local_pause;
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uint32_t p_partner_pause;
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res = R_ETHER_LinkProcess(&g_ether0_ctrl);
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if (res != FSP_SUCCESS)
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LOG_D("R_ETHER_LinkProcess failed!, res = %d", res);
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res = R_ETHER_PHY_LinkStatusGet(&g_ether_phy0_ctrl);
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if (res != FSP_SUCCESS)
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LOG_D("R_ETHER_PHY_LinkStatusGet failed!, res = %d", res);
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if(res == FSP_ERR_ETHER_PHY_ERROR_LINK)
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{
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LOG_D("link down");
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eth_device_linkchange(&ra6m3_eth_device.parent, RT_FALSE);
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return;
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}
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res = R_ETHER_PHY_LinkPartnerAbilityGet(&g_ether_phy0_ctrl,
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&phy_speed_new,
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&p_local_pause,
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&p_partner_pause);
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if (res != FSP_SUCCESS)
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LOG_D("R_ETHER_PHY_LinkPartnerAbilityGet failed!, res = %d", res);
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if(res == FSP_ERR_ETHER_PHY_ERROR_LINK)
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{
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LOG_I("link down");
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eth_device_linkchange(&ra6m3_eth_device.parent, RT_FALSE);
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return;
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}
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if (phy_speed != phy_speed_new)
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{
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phy_speed = phy_speed_new;
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if (phy_speed != ETHER_PHY_LINK_SPEED_NO_LINK)
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{
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LOG_D("link up");
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if (phy_speed == ETHER_PHY_LINK_SPEED_100H || phy_speed == ETHER_PHY_LINK_SPEED_100F)
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{
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LOG_D("100Mbps");
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}
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else
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{
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LOG_D("10Mbps");
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}
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if (phy_speed == ETHER_PHY_LINK_SPEED_100F || phy_speed == ETHER_PHY_LINK_SPEED_10F)
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{
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LOG_D("full-duplex");
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}
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else
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{
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LOG_D("half-duplex");
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}
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/* send link up. */
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LOG_I("link up");
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eth_device_linkchange(&ra6m3_eth_device.parent, RT_TRUE);
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}
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else
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{
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LOG_D("link down");
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eth_device_linkchange(&ra6m3_eth_device.parent, RT_FALSE);
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}
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}
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}
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void user_ether0_callback(ether_callback_args_t * p_args)
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{
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rt_err_t result;
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result = eth_device_ready(&(ra6m3_eth_device.parent));
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if (result != RT_EOK)
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rt_kprintf("RX err =%d\n", result);
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}
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/* Register the EMAC device */
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static int rt_hw_ra6m3_eth_init(void)
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{
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rt_err_t state = RT_EOK;
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/* Prepare receive and send buffers */
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Rx_Buff = (rt_uint8_t *)rt_calloc(1, ETH_MAX_PACKET_SIZE);
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if (Rx_Buff == RT_NULL)
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{
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LOG_E("No memory");
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state = -RT_ENOMEM;
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goto __exit;
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}
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Tx_Buff = (rt_uint8_t *)rt_calloc(1, ETH_MAX_PACKET_SIZE);
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if (Tx_Buff == RT_NULL)
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{
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LOG_E("No memory");
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state = -RT_ENOMEM;
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goto __exit;
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}
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/* OUI 00-80-E1 STMICROELECTRONICS. */
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ra6m3_eth_device.dev_addr[0] = 0x00;
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ra6m3_eth_device.dev_addr[1] = 0x80;
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ra6m3_eth_device.dev_addr[2] = 0xE1;
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/* generate MAC addr from 96bit unique ID (only for test). */
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ra6m3_eth_device.dev_addr[3] = (10 + 4);
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ra6m3_eth_device.dev_addr[4] = (10 + 2);
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ra6m3_eth_device.dev_addr[5] = (10 + 0);
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ra6m3_eth_device.parent.parent.init = rt_ra6m3_eth_init;
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ra6m3_eth_device.parent.parent.open = rt_ra6m3_eth_open;
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ra6m3_eth_device.parent.parent.close = rt_ra6m3_eth_close;
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ra6m3_eth_device.parent.parent.read = rt_ra6m3_eth_read;
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ra6m3_eth_device.parent.parent.write = rt_ra6m3_eth_write;
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ra6m3_eth_device.parent.parent.control = rt_ra6m3_eth_control;
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ra6m3_eth_device.parent.parent.user_data = RT_NULL;
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ra6m3_eth_device.parent.eth_rx = rt_ra6m3_eth_rx;
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ra6m3_eth_device.parent.eth_tx = rt_ra6m3_eth_tx;
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/* register eth device */
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state = eth_device_init(&(ra6m3_eth_device.parent), "e0");
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if (RT_EOK == state)
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{
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LOG_D("emac device init success");
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}
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else
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{
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LOG_E("emac device init faild: %d", state);
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state = -RT_ERROR;
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goto __exit;
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}
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ra6m3_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
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NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
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if (!ra6m3_eth_device.poll_link_timer || rt_timer_start(ra6m3_eth_device.poll_link_timer) != RT_EOK)
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{
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LOG_E("Start link change detection timer failed");
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}
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__exit:
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if (state != RT_EOK)
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{
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if (Rx_Buff)
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{
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rt_free(Rx_Buff);
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}
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if (Tx_Buff)
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{
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rt_free(Tx_Buff);
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}
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}
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return state;
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}
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INIT_DEVICE_EXPORT(rt_hw_ra6m3_eth_init);
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@ -0,0 +1,106 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-25 zylx first version
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*/
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#ifndef __DRV_ETH_H__
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#define __DRV_ETH_H__
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#include <rtthread.h>
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#include <rthw.h>
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#include <rtdevice.h>
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||||
#include <board.h>
|
||||
|
||||
/* The PHY basic control register */
|
||||
#define PHY_BASIC_CONTROL_REG 0x00U
|
||||
#define PHY_RESET_MASK (1<<15)
|
||||
#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
|
||||
|
||||
/* The PHY basic status register */
|
||||
#define PHY_BASIC_STATUS_REG 0x01U
|
||||
#define PHY_LINKED_STATUS_MASK (1<<2)
|
||||
#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
|
||||
|
||||
/* The PHY ID one register */
|
||||
#define PHY_ID1_REG 0x02U
|
||||
/* The PHY ID two register */
|
||||
#define PHY_ID2_REG 0x03U
|
||||
/* The PHY auto-negotiate advertise register */
|
||||
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
|
||||
|
||||
|
||||
#ifdef PHY_USING_LAN8720A
|
||||
/* The PHY interrupt source flag register. */
|
||||
#define PHY_INTERRUPT_FLAG_REG 0x1DU
|
||||
/* The PHY interrupt mask register. */
|
||||
#define PHY_INTERRUPT_MASK_REG 0x1EU
|
||||
#define PHY_LINK_DOWN_MASK (1<<4)
|
||||
#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
|
||||
|
||||
/* The PHY status register. */
|
||||
#define PHY_Status_REG 0x1FU
|
||||
#define PHY_10M_MASK (1<<2)
|
||||
#define PHY_100M_MASK (1<<3)
|
||||
#define PHY_FULL_DUPLEX_MASK (1<<4)
|
||||
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
|
||||
#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
|
||||
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
||||
|
||||
#elif defined(PHY_USING_DM9161CEP)
|
||||
#define PHY_Status_REG 0x11U
|
||||
#define PHY_10M_MASK ((1<<12) || (1<<13))
|
||||
#define PHY_100M_MASK ((1<<14) || (1<<15))
|
||||
#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13))
|
||||
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
|
||||
#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
|
||||
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
||||
/* The PHY interrupt source flag register. */
|
||||
#define PHY_INTERRUPT_FLAG_REG 0x15U
|
||||
/* The PHY interrupt mask register. */
|
||||
#define PHY_INTERRUPT_MASK_REG 0x15U
|
||||
#define PHY_LINK_CHANGE_FLAG (1<<2)
|
||||
#define PHY_LINK_CHANGE_MASK (1<<9)
|
||||
#define PHY_INT_MASK 0
|
||||
|
||||
#elif defined(PHY_USING_DP83848C)
|
||||
#define PHY_Status_REG 0x10U
|
||||
#define PHY_10M_MASK (1<<1)
|
||||
#define PHY_FULL_DUPLEX_MASK (1<<2)
|
||||
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
|
||||
#define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr))
|
||||
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
||||
/* The PHY interrupt source flag register. */
|
||||
#define PHY_INTERRUPT_FLAG_REG 0x12U
|
||||
#define PHY_LINK_CHANGE_FLAG (1<<13)
|
||||
/* The PHY interrupt control register. */
|
||||
#define PHY_INTERRUPT_CTRL_REG 0x11U
|
||||
#define PHY_INTERRUPT_EN ((1<<0)|(1<<1))
|
||||
/* The PHY interrupt mask register. */
|
||||
#define PHY_INTERRUPT_MASK_REG 0x12U
|
||||
#define PHY_INT_MASK (1<<5)
|
||||
#endif
|
||||
|
||||
#ifdef PHY_USING_LAN8742A
|
||||
/* The PHY interrupt source flag register. */
|
||||
#define PHY_INTERRUPT_FLAG_REG 0x1DU
|
||||
/* The PHY interrupt mask register. */
|
||||
#define PHY_INTERRUPT_MASK_REG 0x1EU
|
||||
#define PHY_LINK_DOWN_MASK (1<<4)
|
||||
#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
|
||||
|
||||
/* The PHY status register. */
|
||||
#define PHY_Status_REG 0x1FU
|
||||
#define PHY_10M_MASK (1<<2)
|
||||
#define PHY_100M_MASK (1<<3)
|
||||
#define PHY_FULL_DUPLEX_MASK (1<<4)
|
||||
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
|
||||
#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
|
||||
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
||||
#endif /* PHY_USING_LAN8742A */
|
||||
|
||||
#endif /* __DRV_ETH_H__ */
|
||||
|
|
@ -122,6 +122,13 @@ menu "Hardware Drivers Config"
|
|||
select BSP_USING_SPI0
|
||||
default n
|
||||
|
||||
config BSP_USING_ETH
|
||||
bool "Enable Ethernet"
|
||||
select RT_USING_SAL
|
||||
select RT_USING_LWIP
|
||||
select RT_USING_NETDEV
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_LVGL
|
||||
bool "Enable LVGL for LCD"
|
||||
select PKG_USING_LVGL
|
||||
|
|
|
|||
Loading…
Reference in New Issue