Merge branch 'master' of https://github.com/RT-Thread/rt-thread
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README.md
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README.md
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[![Build Status](https://travis-ci.org/RT-Thread/rt-thread.png)](https://travis-ci.org/RT-Thread/rt-thread)
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RT-Thread is an open source real-time operating system for embedded devices.
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RT-Thread is an open source real-time operating system for embedded devices from China. RT-Thread RTOS is a scalable real-time operating system: a tiny kernel for ARM Cortex-M0, Cortex-M3/4, or a full feature system in ARM Cortex-A8, ARM Cortex-A9 DualCore etc.
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## Overview ##
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RT-Thread RTOS like a traditional real-time operating system. The kernel has real-time multi-task scheduling, semaphore, mutex, mail box, message queue etc. However, it has two different things:
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* Device Driver;
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* Component.
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The device driver is more like a driver framework, UART, SPI, USB device/host, EMAC, MTD NAND etc. The developer can easyly add low level driver and board configuration, then he/she can use lots of features.
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The Component is a software concept upon RT-Thread kernel, for example a shell (finsh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system).
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## Board Support Package ##
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RT-Thread RTOS can support many architectures:
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* ARM Cortex-M0
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* ARM Cortex-M3/M4
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* ARM Cortex-R4
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* ARM Cortex-A8/A9
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* ARM920T/ARM926 etc
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* MIPS
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* x86
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* PowerPC
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## License ##
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RT-Thread RTOS is released under GPLv2+ license, that means any modification of RT-Thread RTOS should be feed back to community, but it can be friendly used in commercial products when mention your product is using RT-Thread RTOS.
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## Usage ##
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RT-Thread RTOS uses [scons](http://www.scons.org) as its building system. Therefore, please install scons and Python 2.7 firstly.
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## Contribution ##
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Thank all of RT-Thread Developers.
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// </h>
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*/
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.equ Stack_Size, 0x00000100
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.equ Stack_Size, 0x00000200
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.equ Sign_Value, 0x5A5A5A5A
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.section ".stack", "w"
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.align 3
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@ -56,8 +56,8 @@ __cs3_heap_end:
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.type __cs3_interrupt_vector_cortex_m, %object
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__cs3_interrupt_vector_cortex_m:
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.long __cs3_stack /* Top of Stack */
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.long __cs3_reset /* Reset Handler */
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.long _estack /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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/* External Interrupts */
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.long DAC_IRQHandler /* 16 D/A Converter */
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.long 0 /* 17 Event Router */
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.long MX_CORE_IRQHandler /* 17 M0/M4 IRQ handler (LPC43XX ONLY) */
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.long DMA_IRQHandler /* 18 General Purpose DMA */
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.long 0 /* 19 Reserved */
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.long 0 /* 20 Reserved */
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.long UnHandled_Vector /* 19 Reserved */
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.long FLASHEEPROM_IRQHandler /* 20 ORed flash bank A, flash bank B, EEPROM interrupts */
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.long ETH_IRQHandler /* 21 Ethernet */
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.long SDIO_IRQHandler /* 22 SD/MMC */
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.long LCD_IRQHandler /* 23 LCD */
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.long ADC0_IRQHandler /* 33 A/D Converter 0*/
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.long I2C0_IRQHandler /* 34 I2C0*/
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.long I2C1_IRQHandler /* 35 I2C1*/
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.long 0 /* 36 Reserved*/
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.long SPI_IRQHandler /* 36 SPI (LPC43XX ONLY)*/
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.long ADC1_IRQHandler /* 37 A/D Converter 1*/
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.long SSP0_IRQHandler /* 38 SSP0*/
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.long SSP1_IRQHandler /* 39 SSP1*/
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.long GINT1_IRQHandler /* 57 GINT1*/
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.long EVRT_IRQHandler /* 58 Event Router*/
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.long CAN1_IRQHandler /* 59 C_CAN1*/
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.long 0 /* 60 Reserved*/
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.long UnHandled_Vector /* 60 Reserved*/
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.long VADC_IRQHandler /* 61 VADC*/
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.long ATIMER_IRQHandler /* 62 ATIMER*/
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.long RTC_IRQHandler /* 63 RTC*/
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.long 0 /* 64 Reserved*/
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.long UnHandled_Vector /* 64 Reserved*/
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.long WDT_IRQHandler /* 65 WDT*/
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.long 0 /* 66 M0s*/
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.long UnHandled_Vector /* 66 M0s*/
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.long CAN0_IRQHandler /* 67 C_CAN0*/
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.long QEI_IRQHandler /* 68 QEI*/
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/* Reset Handler */
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.section .cs3.reset,"x",%progbits
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.section .text.Reset_Handler
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.thumb_func
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.globl __cs3_reset_cortex_m
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.type __cs3_reset_cortex_m, %function
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__cs3_reset_cortex_m:
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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.fnstart
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/* .if (RAM_MODE) */
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.if 0
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.pool
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.cantunwind
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.fnend
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.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
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.size Reset_Handler,.-Reset_Handler
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.section ".text"
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B .
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.size Default_Handler, . - Default_Handler
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.globl UnHandled_Vector
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.type UnHandled_Vector, %function
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UnHandled_Vector:
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B .
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.size UnHandled_Vector, . - UnHandled_Vector
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.macro IRQ handler
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.weak \handler
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.set \handler, Default_Handler
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.endm
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IRQ DAC_IRQHandler
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IRQ MX_CORE_IRQHandler
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IRQ DMA_IRQHandler
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IRQ FLASHEEPROM_IRQHandler
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IRQ ETH_IRQHandler
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IRQ SDIO_IRQHandler
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IRQ LCD_IRQHandler
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IRQ ADC0_IRQHandler
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IRQ I2C0_IRQHandler
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IRQ I2C1_IRQHandler
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IRQ SPI_IRQHandler
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IRQ ADC1_IRQHandler
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IRQ SSP0_IRQHandler
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IRQ SSP1_IRQHandler
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