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【ci】添加 timer、irq 测试

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This commit is contained in:
guozhanxin 2021-08-24 17:18:15 +08:00
parent 0ab5affee9
commit fe4bec08a5
3 changed files with 8 additions and 0 deletions
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2
.github/workflows/action_utest.yml vendored
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@ -13,6 +13,8 @@ jobs:
legs:
- {UTEST: "kernel/mem", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/mem.conf", SD_FILE: "sd.bin"}
- {UTEST: "kernel/ipc", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/ipc.conf", SD_FILE: "sd.bin"}
- {UTEST: "kernel/irq", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/irq.conf", SD_FILE: "sd.bin"}
- {UTEST: "kernel/timer", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/timer.conf", SD_FILE: "sd.bin"}
- {UTEST: "components/utest", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "arm", QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "utest_self/self.conf", SD_FILE: "sd.bin"}
- {UTEST: "kernel/mem/riscv64", RTT_BSP: "bsp/qemu-riscv-virt64", QEMU_ARCH: "riscv64", QEMU_MACHINE: "virt", CONFIG_FILE: "kernel/mem.conf", SD_FILE: "None"}
env:

2
examples/utest/configs/kernel/irq.conf Normal file
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@ -0,0 +1,2 @@
CONFIG_UTEST_IRQ_TC=y
# dependencies

4
examples/utest/configs/kernel/timer.conf Normal file
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@ -0,0 +1,4 @@
CONFIG_UTEST_TIMER_TC=y
# dependencies
CONFIG_RT_USING_TIMER_SOFT=y