From fd3b4329157a3d57b3e09fd9f95bad925d2c1d2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E7=A8=8B=E8=92=99=E8=92=99?= Date: Fri, 30 Jun 2023 12:58:39 +0800 Subject: [PATCH] =?UTF-8?q?[STM32WL55]=E4=BF=AE=E5=A4=8Dscons=E7=BC=96?= =?UTF-8?q?=E8=AF=91=E4=B8=8D=E9=80=9A=E8=BF=87=EF=BC=8C=E5=AE=8C=E5=96=84?= =?UTF-8?q?link=E6=96=87=E4=BB=B6=EF=BC=8C=E7=A7=BB=E9=99=A4=E7=A1=AC?= =?UTF-8?q?=E4=BB=B6=E6=B5=AE=E7=82=B9=E6=94=AF=E6=8C=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: 程蒙蒙 --- .../stm32wl55-st-nucleo/board/SConscript | 2 +- .../board/linker_scripts/link.icf | 40 ++++ .../board/linker_scripts/link.lds | 178 ++++++++++++++++++ .../board/linker_scripts/link.sct | 12 +- bsp/stm32/stm32wl55-st-nucleo/rtconfig.py | 12 +- .../board/SConscript | 2 +- .../board/linker_scripts/link.icf | 40 ++++ .../board/linker_scripts/link.lds | 178 ++++++++++++++++++ .../board/linker_scripts/link.sct | 12 +- .../stm32wle5-yizhilian-lm401/rtconfig.py | 14 +- .../board/SConscript | 2 +- .../board/linker_scripts/link.icf | 40 ++++ .../board/linker_scripts/link.lds | 178 ++++++++++++++++++ .../board/linker_scripts/link.sct | 12 +- .../stm32wle5-yizhilian-lm402/rtconfig.py | 14 +- 15 files changed, 701 insertions(+), 35 deletions(-) create mode 100644 bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.icf create mode 100644 bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.lds create mode 100644 bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.icf create mode 100644 bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.lds create mode 100644 bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.icf create mode 100644 bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.lds diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/SConscript b/bsp/stm32/stm32wl55-st-nucleo/board/SConscript index 121fcacfe9..8913497b4b 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/board/SConscript +++ b/bsp/stm32/stm32wl55-st-nucleo/board/SConscript @@ -25,7 +25,7 @@ elif rtconfig.PLATFORM in ['armcc', 'armclang']: elif rtconfig.PLATFORM in ['iccarm']: src += [startup_path_prefix + '/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wle5xx.s'] -CPPDEFINES = ['STM32WLxx'] +CPPDEFINES = ['STM32WL55xx'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.icf b/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.icf new file mode 100644 index 0000000000..703e6948e5 --- /dev/null +++ b/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08020000; + +/*-Memory Regions-*/ +/***** FLASH part dedicated to M0+ *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08020000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +/***** SRAM1 dedicated to M0+ *****/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20004000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/***** SRAM2 dedicated to M0+ *****/ +define symbol __ICFEDIT_region_RAM2_start__ = 0x2000C000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in RAM2_region { }; diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.lds b/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.lds new file mode 100644 index 0000000000..26d8eae59e --- /dev/null +++ b/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.lds @@ -0,0 +1,178 @@ +/* +** LinkerScript +** Note: For specific memory allocation, linker and startup files must be customized. +** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script". +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* Flash memory dedicated to CM4 */ + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 16K /* Non-backup SRAM1 dedicated to CM4 */ + RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 16K /* Backup SRAM2 dedicated to CM4 */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "ROM" Rom type memory */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >ROM + + /* The program code and other data into "ROM" Rom type memory */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "ROM" Rom type memory */ + .rodata : + { + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >ROM + + .ARM.extab : { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >ROM + + .ARM : { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >ROM + + .preinit_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >ROM + + .init_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >ROM + + .fini_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "SRAM1" Ram type memory */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + + } >RAM1 AT> ROM + + /* Uninitialized data section into "SRAM1" Ram type memory */ + . = ALIGN(8); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(8); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */ + . = ALIGN(8); + RAM1_region : + { + _sRAM1_region = .; /* define a global symbol at section start */ + *(.RAM1_region) + + . = ALIGN(8); + _eRAM1_region = .; /* define a global symbol at section end */ + } >RAM1 + + /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */ + . = ALIGN(8); + RAM2_region : + { + _sRAM2_region = .; /* define a global symbol at section start */ + *(.RAM2_region) + + . = ALIGN(8); + _eRAM2_region = .; /* define a global symbol at section end */ + } >RAM2 + + /* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.sct b/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.sct index e68eea6daf..48345ff2ff 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32wl55-st-nucleo/board/linker_scripts/link.sct @@ -2,14 +2,18 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x08000000 0x40000 { ; load region size_region - ER_IROM1 0x08000000 0x40000 { ; load address = execution address +LR_IROM1 0x08000000 0x00020000 { ; load region size_region + ; FLASH part dedicated to M4 + ER_IROM1 0x08000000 0x00020000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM2 0x10000000 0x00008000 { ; RW data + ; Non-backup SRAM1 dedicated to M4 + RW_IRAM1 0x20000000 0x00004000 { ; RW data .ANY (+RW +ZI) } + ; Backup SRAM2 dedicated to M4 + RW_IRAM2 0x20008000 EMPTY 0x00004000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + } } - diff --git a/bsp/stm32/stm32wl55-st-nucleo/rtconfig.py b/bsp/stm32/stm32wl55-st-nucleo/rtconfig.py index c1cd204199..e80937205c 100644 --- a/bsp/stm32/stm32wl55-st-nucleo/rtconfig.py +++ b/bsp/stm32/stm32wl55-st-nucleo/rtconfig.py @@ -43,7 +43,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=soft -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -Dgcc' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' @@ -57,7 +57,7 @@ if PLATFORM == 'gcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' @@ -88,7 +88,7 @@ elif PLATFORM == 'armcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' @@ -105,7 +105,7 @@ elif PLATFORM == 'armclang': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -mfloat-abi=soft -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' CFLAGS += ' -gdwarf-3 -ffunction-sections ' AFLAGS = DEVICE + ' --apcs=interwork ' LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' @@ -121,7 +121,7 @@ elif PLATFORM == 'armclang': AFLAGS += ' -g' else: CFLAGS += ' -O2' - + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' @@ -170,7 +170,7 @@ elif PLATFORM == 'iccarm': LFLAGS = ' --config "board/linker_scripts/link.icf"' LFLAGS += ' --entry __iar_program_start' - + CXXFLAGS = CFLAGS EXEC_PATH = EXEC_PATH + '/arm/bin/' diff --git a/bsp/stm32/stm32wle5-yizhilian-lm401/board/SConscript b/bsp/stm32/stm32wle5-yizhilian-lm401/board/SConscript index 121fcacfe9..1138e4d56c 100644 --- a/bsp/stm32/stm32wle5-yizhilian-lm401/board/SConscript +++ b/bsp/stm32/stm32wle5-yizhilian-lm401/board/SConscript @@ -25,7 +25,7 @@ elif rtconfig.PLATFORM in ['armcc', 'armclang']: elif rtconfig.PLATFORM in ['iccarm']: src += [startup_path_prefix + '/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wle5xx.s'] -CPPDEFINES = ['STM32WLxx'] +CPPDEFINES = ['STM32WLE5xx'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.icf b/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.icf new file mode 100644 index 0000000000..5a03913be1 --- /dev/null +++ b/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; + +/*-Memory Regions-*/ +/***** FLASH *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +/***** Non-backup SRAM1 *****/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/***** Backup SRAM2 *****/ +define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in RAM2_region { }; diff --git a/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.lds b/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.lds new file mode 100644 index 0000000000..631b77d92a --- /dev/null +++ b/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.lds @@ -0,0 +1,178 @@ +/* +** LinkerScript +** Note: For specific memory allocation, linker and startup files must be customized. +** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script". +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 */ + RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "ROM" Rom type memory */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >ROM + + /* The program code and other data into "ROM" Rom type memory */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "ROM" Rom type memory */ + .rodata : + { + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >ROM + + .ARM.extab : { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >ROM + + .ARM : { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >ROM + + .preinit_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >ROM + + .init_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >ROM + + .fini_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "SRAM1" Ram type memory */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + + } >RAM1 AT> ROM + + /* Uninitialized data section into "SRAM1" Ram type memory */ + . = ALIGN(8); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(8); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */ + . = ALIGN(8); + RAM1_region : + { + _sRAM1_region = .; /* define a global symbol at section start */ + *(.RAM1_region) + + . = ALIGN(8); + _eRAM1_region = .; /* define a global symbol at section end */ + } >RAM1 + + /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */ + . = ALIGN(8); + RAM2_region : + { + _sRAM2_region = .; /* define a global symbol at section start */ + *(.RAM2_region) + + . = ALIGN(8); + _eRAM2_region = .; /* define a global symbol at section end */ + } >RAM2 + + /* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.sct b/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.sct index ff7e3c0efa..ec0e915dde 100644 --- a/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32wle5-yizhilian-lm401/board/linker_scripts/link.sct @@ -2,14 +2,18 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x08000000 0x20000 { ; load region size_region - ER_IROM1 0x08000000 0x20000 { ; load address = execution address +LR_IROM1 0x08000000 0x00040000 { ; load region size_region + ; FLASH + ER_IROM1 0x08000000 0x00040000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM2 0x10000000 0x00004000 { ; RW data + ; Non-backup SRAM1 + RW_IRAM1 0x20000000 0x00008000 { ; RW data .ANY (+RW +ZI) } + ; Backup SRAM2 + RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + } } - diff --git a/bsp/stm32/stm32wle5-yizhilian-lm401/rtconfig.py b/bsp/stm32/stm32wle5-yizhilian-lm401/rtconfig.py index ce02409e5d..9c6a4a7e01 100644 --- a/bsp/stm32/stm32wle5-yizhilian-lm401/rtconfig.py +++ b/bsp/stm32/stm32wle5-yizhilian-lm401/rtconfig.py @@ -43,7 +43,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=soft -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -Dgcc' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' @@ -57,7 +57,7 @@ if PLATFORM == 'gcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' @@ -88,7 +88,7 @@ elif PLATFORM == 'armcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' @@ -105,7 +105,7 @@ elif PLATFORM == 'armclang': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -mfloat-abi=soft -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' CFLAGS += ' -gdwarf-3 -ffunction-sections ' AFLAGS = DEVICE + ' --apcs=interwork ' LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' @@ -121,7 +121,7 @@ elif PLATFORM == 'armclang': AFLAGS += ' -g' else: CFLAGS += ' -O2' - + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' @@ -170,7 +170,7 @@ elif PLATFORM == 'iccarm': LFLAGS = ' --config "board/linker_scripts/link.icf"' LFLAGS += ' --entry __iar_program_start' - + CXXFLAGS = CFLAGS EXEC_PATH = EXEC_PATH + '/arm/bin/' @@ -181,4 +181,4 @@ def dist_handle(BSP_ROOT, dist_dir): cwd_path = os.getcwd() sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) \ No newline at end of file + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32wle5-yizhilian-lm402/board/SConscript b/bsp/stm32/stm32wle5-yizhilian-lm402/board/SConscript index 121fcacfe9..1138e4d56c 100644 --- a/bsp/stm32/stm32wle5-yizhilian-lm402/board/SConscript +++ b/bsp/stm32/stm32wle5-yizhilian-lm402/board/SConscript @@ -25,7 +25,7 @@ elif rtconfig.PLATFORM in ['armcc', 'armclang']: elif rtconfig.PLATFORM in ['iccarm']: src += [startup_path_prefix + '/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wle5xx.s'] -CPPDEFINES = ['STM32WLxx'] +CPPDEFINES = ['STM32WLE5xx'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) Return('group') diff --git a/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.icf b/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.icf new file mode 100644 index 0000000000..5a03913be1 --- /dev/null +++ b/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; + +/*-Memory Regions-*/ +/***** FLASH *****/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF; +/***** Non-backup SRAM1 *****/ +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/***** Backup SRAM2 *****/ +define symbol __ICFEDIT_region_RAM2_start__ = 0x20008000; +define symbol __ICFEDIT_region_RAM2_end__ = 0x2000FFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in RAM2_region { }; diff --git a/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.lds b/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.lds new file mode 100644 index 0000000000..631b77d92a --- /dev/null +++ b/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.lds @@ -0,0 +1,178 @@ +/* +** LinkerScript +** Note: For specific memory allocation, linker and startup files must be customized. +** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script". +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 256K + RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K /* Non-backup SRAM1 */ + RAM2 (xrw) : ORIGIN = 0x20008000, LENGTH = 32K /* Backup SRAM2 */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "ROM" Rom type memory */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >ROM + + /* The program code and other data into "ROM" Rom type memory */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "ROM" Rom type memory */ + .rodata : + { + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >ROM + + .ARM.extab : { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >ROM + + .ARM : { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >ROM + + .preinit_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >ROM + + .init_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >ROM + + .fini_array : + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "SRAM1" Ram type memory */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + + } >RAM1 AT> ROM + + /* Uninitialized data section into "SRAM1" Ram type memory */ + . = ALIGN(8); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(8); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */ + . = ALIGN(8); + RAM1_region : + { + _sRAM1_region = .; /* define a global symbol at section start */ + *(.RAM1_region) + + . = ALIGN(8); + _eRAM1_region = .; /* define a global symbol at section end */ + } >RAM1 + + /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */ + . = ALIGN(8); + RAM2_region : + { + _sRAM2_region = .; /* define a global symbol at section start */ + *(.RAM2_region) + + . = ALIGN(8); + _eRAM2_region = .; /* define a global symbol at section end */ + } >RAM2 + + /* User_heap_stack section, used to check that there is enough "SRAM1" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.sct b/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.sct index e68eea6daf..ec0e915dde 100644 --- a/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.sct +++ b/bsp/stm32/stm32wle5-yizhilian-lm402/board/linker_scripts/link.sct @@ -2,14 +2,18 @@ ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* -LR_IROM1 0x08000000 0x40000 { ; load region size_region - ER_IROM1 0x08000000 0x40000 { ; load address = execution address +LR_IROM1 0x08000000 0x00040000 { ; load region size_region + ; FLASH + ER_IROM1 0x08000000 0x00040000 { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } - RW_IRAM2 0x10000000 0x00008000 { ; RW data + ; Non-backup SRAM1 + RW_IRAM1 0x20000000 0x00008000 { ; RW data .ANY (+RW +ZI) } + ; Backup SRAM2 + RW_IRAM2 0x20008000 EMPTY 0x00008000 { ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc... + } } - diff --git a/bsp/stm32/stm32wle5-yizhilian-lm402/rtconfig.py b/bsp/stm32/stm32wle5-yizhilian-lm402/rtconfig.py index ce02409e5d..9c6a4a7e01 100644 --- a/bsp/stm32/stm32wle5-yizhilian-lm402/rtconfig.py +++ b/bsp/stm32/stm32wle5-yizhilian-lm402/rtconfig.py @@ -43,7 +43,7 @@ if PLATFORM == 'gcc': OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=soft -ffunction-sections -fdata-sections' CFLAGS = DEVICE + ' -Dgcc' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' @@ -57,7 +57,7 @@ if PLATFORM == 'gcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' @@ -88,7 +88,7 @@ elif PLATFORM == 'armcc': else: CFLAGS += ' -O2' - CXXFLAGS = CFLAGS + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' @@ -105,7 +105,7 @@ elif PLATFORM == 'armclang': DEVICE = ' --cpu Cortex-M4.fp ' CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 ' - CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -mfloat-abi=soft -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' CFLAGS += ' -gdwarf-3 -ffunction-sections ' AFLAGS = DEVICE + ' --apcs=interwork ' LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' @@ -121,7 +121,7 @@ elif PLATFORM == 'armclang': AFLAGS += ' -g' else: CFLAGS += ' -O2' - + CXXFLAGS = CFLAGS CFLAGS += ' -std=c99' @@ -170,7 +170,7 @@ elif PLATFORM == 'iccarm': LFLAGS = ' --config "board/linker_scripts/link.icf"' LFLAGS += ' --entry __iar_program_start' - + CXXFLAGS = CFLAGS EXEC_PATH = EXEC_PATH + '/arm/bin/' @@ -181,4 +181,4 @@ def dist_handle(BSP_ROOT, dist_dir): cwd_path = os.getcwd() sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) \ No newline at end of file + dist_do_building(BSP_ROOT, dist_dir)