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rt-thread-official
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fix cortex-a cahce

This commit is contained in:
ZYH 2019-06-19 10:29:56 +08:00
parent e1517a0981
commit fc155f8810
1 changed files with 6 additions and 0 deletions
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6
libcpu/arm/cortex-a/cache.c
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@ -30,6 +30,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size)
rt_uint32_t start_addr = (rt_uint32_t)addr; rt_uint32_t start_addr = (rt_uint32_t)addr;
rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
asm volatile ("dmb":::"memory");
start_addr &= ~(line_size-1); start_addr &= ~(line_size-1);
end_addr &= ~(line_size-1); end_addr &= ~(line_size-1);
while (start_addr < end_addr) while (start_addr < end_addr)
@ -37,6 +38,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size)
asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr)); /* icimvau */ asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr)); /* icimvau */
start_addr += line_size; start_addr += line_size;
} }
asm volatile ("dsb\n\tisb":::"memory");
} }
void rt_hw_cpu_dcache_invalidate(void *addr, int size) void rt_hw_cpu_dcache_invalidate(void *addr, int size)
@ -45,6 +47,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
rt_uint32_t start_addr = (rt_uint32_t)addr; rt_uint32_t start_addr = (rt_uint32_t)addr;
rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
asm volatile ("dmb":::"memory");
start_addr &= ~(line_size-1); start_addr &= ~(line_size-1);
end_addr &= ~(line_size-1); end_addr &= ~(line_size-1);
while (start_addr < end_addr) while (start_addr < end_addr)
@ -52,6 +55,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */ asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */
start_addr += line_size; start_addr += line_size;
} }
asm volatile ("dsb":::"memory");
} }
void rt_hw_cpu_dcache_clean(void *addr, int size) void rt_hw_cpu_dcache_clean(void *addr, int size)
@ -60,6 +64,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
rt_uint32_t start_addr = (rt_uint32_t)addr; rt_uint32_t start_addr = (rt_uint32_t)addr;
rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
asm volatile ("dmb":::"memory");
start_addr &= ~(line_size-1); start_addr &= ~(line_size-1);
end_addr &= ~(line_size-1); end_addr &= ~(line_size-1);
while (start_addr < end_addr) while (start_addr < end_addr)
@ -67,6 +72,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */ asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */
start_addr += line_size; start_addr += line_size;
} }
asm volatile ("dsb":::"memory");
} }
void rt_hw_cpu_icache_ops(int ops, void *addr, int size) void rt_hw_cpu_icache_ops(int ops, void *addr, int size)