diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index f6499505c3..8f3cf566a5 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -74,7 +74,7 @@ jobs: - {RTT_BSP: "stm32/stm32f103-dofly-M3S", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-fire-arbitrary", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-hw100k-ibox", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f103-mini-system", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f103-blue-pill", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-onenet-nbiot", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"} diff --git a/bsp/maxim/MAX32660_EVSYS/.config b/bsp/maxim/MAX32660_EVSYS/.config index 82e0a0d279..c2b026f742 100644 --- a/bsp/maxim/MAX32660_EVSYS/.config +++ b/bsp/maxim/MAX32660_EVSYS/.config @@ -14,7 +14,7 @@ CONFIG_RT_ALIGN_SIZE=4 CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y @@ -272,6 +272,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_PDULIB is not set # CONFIG_PKG_USING_BTSTACK is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set # # security packages @@ -300,6 +301,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_HELIX is not set # CONFIG_PKG_USING_AZUREGUIX is not set # CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_LVGL is not set # # tools packages @@ -311,6 +313,8 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set # CONFIG_PKG_USING_COREMARK is not set # CONFIG_PKG_USING_DHRYSTONE is not set @@ -324,6 +328,16 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_UMCN is not set # CONFIG_PKG_USING_LWRB2RTT is not set # CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set # # system packages @@ -361,6 +375,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set # # peripheral libraries and drivers @@ -369,6 +390,7 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -418,7 +440,10 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_SSD1306 is not set # CONFIG_PKG_USING_QKEY is not set # CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set # # miscellaneous packages @@ -468,6 +493,9 @@ CONFIG_RT_USING_PIN=y # CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_LWGPS is not set # CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set # # Hardware Drivers Config @@ -485,3 +513,4 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_UART1_RX_USING_DMA is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_I2C is not set diff --git a/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.peripherals.state.json b/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.peripherals.state.json new file mode 100644 index 0000000000..0637a088a0 --- /dev/null +++ b/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.peripherals.state.json @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.registers.state.json b/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.registers.state.json new file mode 100644 index 0000000000..0637a088a0 --- /dev/null +++ b/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.registers.state.json @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/bsp/maxim/MAX32660_EVSYS/.vscode/launch.json b/bsp/maxim/MAX32660_EVSYS/.vscode/launch.json new file mode 100644 index 0000000000..138d6ae360 --- /dev/null +++ b/bsp/maxim/MAX32660_EVSYS/.vscode/launch.json @@ -0,0 +1,24 @@ +{ + // 使用 IntelliSense 了解相关属性。 + // 悬停以查看现有属性的描述。 + // 欲了解更多信息，请访问: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "cwd": "${workspaceRoot}", + "executable": "rt-thread.elf", + "name": "Debug MAX", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "interface": "swd", + "svdFile": "max32660.svd", + "configFiles": [ + "interface/cmsis-dap.cfg", + "target/max32660.cfg" + ], + "runToMain": true, + //"preLaunchTask": "build" + }, + ] +} \ No newline at end of file diff --git a/bsp/maxim/MAX32660_EVSYS/.vscode/tasks.json b/bsp/maxim/MAX32660_EVSYS/.vscode/tasks.json new file mode 100644 index 0000000000..278b38cf33 --- /dev/null +++ b/bsp/maxim/MAX32660_EVSYS/.vscode/tasks.json @@ -0,0 +1,39 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "build", + "type": "shell", + "command": "scons", + "problemMatcher": [ + "$gcc" + ], + "presentation": { + "echo": true, + "reveal": "always", + "focus": true, + "panel": "shared", + "showReuseMessage": true + }, + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "clean", + "type": "shell", + "command": "scons -c", + "problemMatcher": [], + "presentation": { + "echo": true, + "reveal": "always", + "focus": true, + "panel": "shared", + "showReuseMessage": true + } + }, + ] +} \ No newline at end of file diff --git a/bsp/maxim/MAX32660_EVSYS/README.md b/bsp/maxim/MAX32660_EVSYS/README.md index 90fea40042..8559119b72 100644 --- a/bsp/maxim/MAX32660_EVSYS/README.md +++ b/bsp/maxim/MAX32660_EVSYS/README.md @@ -78,7 +78,7 @@ MAX32660-EVSYS开发板常用 **板载资源** 如下： | SPI | 支持 | SPI0, SPI1 | | RTC | | | | I2S | | | -| I2C | | | +| I2C | 支持 | I2C0, I2C1 | | TIMER | | | | Watchdog | | | @@ -92,11 +92,39 @@ MAX32660-EVSYS开发板常用 **板载资源** 如下： 2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 +4. 输入`scons --target=mdk5/vsc命令重新生成工程。 ## 注意事项 -目前仅支持keil5环境 +目前支持keil和GCC环境 + + + +## FAQ + +### GCC环境如何调试使用 + +第一步，需要配置arm-none-eabi-gcc路径到系統环境变量中去或者在rtconfig.py中EXEC_PATH 修改路径 + +第二步，添加openocd的路径，如果你安装了eclipse，添加以下路径到系统环境变量中 + +`C:\Maxim\Toolchain\bin` + +完成这两部就可以用vscode打开bsp目录了。 + +快捷键ctrl+shift+b可以执行scons编译命令 + +快捷键F5可以进入调试命令 + +如果需要调试之前执行build命令，在luanch.json里面打开注释 + +``` + //"preLaunchTask": "build" +``` + + + + ## 联系人信息 diff --git a/bsp/maxim/MAX32660_EVSYS/board/Kconfig b/bsp/maxim/MAX32660_EVSYS/board/Kconfig index fa4ec1d0cd..01d04ec0f6 100644 --- a/bsp/maxim/MAX32660_EVSYS/board/Kconfig +++ b/bsp/maxim/MAX32660_EVSYS/board/Kconfig @@ -66,6 +66,22 @@ menu "On-chip Peripheral Drivers" select PKG_USING_FAL bool "Enable on-chip FLASH" default n + config BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default n + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0 bus [SCL P0.8; SDA P0.9]" + default y + + config BSP_USING_I2C1 + bool "Enable I2C1 bus [SCL P0.2; SDA P0.3]" + default n + endif + + endmenu diff --git a/bsp/maxim/MAX32660_EVSYS/board/board.c b/bsp/maxim/MAX32660_EVSYS/board/board.c index fc9ff80ad2..5bc5a5f679 100644 --- a/bsp/maxim/MAX32660_EVSYS/board/board.c +++ b/bsp/maxim/MAX32660_EVSYS/board/board.c @@ -40,7 +40,7 @@ void rt_hw_systick_init(void) if (error != E_NO_ERROR) { - printf("ERROR: Ticks is not valid"); + rt_kprintf("ERROR: Ticks is not valid"); } } diff --git a/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds b/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds index 8931956648..4736a8d23f 100644 --- a/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds +++ b/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds @@ -19,6 +19,33 @@ SECTIONS { /* C++ Exception handling */ KEEP(*(.eh_frame*)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + _etext = .; } > FLASH diff --git a/bsp/maxim/MAX32660_EVSYS/max32660.svd b/bsp/maxim/MAX32660_EVSYS/max32660.svd new file mode 100644 index 0000000000..564a9c89ca --- /dev/null +++ b/bsp/maxim/MAX32660_EVSYS/max32660.svd @@ -0,0 +1,10650 @@ + + + Maxim Integrated + Maxim + max32660 + ARMCM4 + 1.0 + MAX32660 32-bit ARM Cortex-M4 microcontroller with 96KB of system RAM and 256KB of flash memory. + + CM4 + r2p1 + little + true + true + 3 + false + + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + BBFC + Battery-Backed Function Control. + 0x40005800 + + 0x00 + 0x400 + registers + + + + BBFCR0 + Function Control Register 0. + 0x00 + read-write + + + CKPDRV + Hyperbus CK Pad Driver Control. + 0 + 4 + + + CKNPDRV + Hyperbus CKN Pad Driver Control. + 4 + 4 + + + RDSDLLEN + Hyperbus RDS DLL Power Up Control. + 8 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + + + + + + BBSIR + Battery-Backed Registers. + 0x40005400 + + 0x00 + 0x400 + registers + + + + rsv0 + RFU + 0x00 + + + BB_SIR2 + System Init. Configuration Register 2. + 0x08 + read-only + + + BB_SIR3 + System Init. Configuration Register 3. + 0x0C + read-only + + + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0 + 28 + + + DMA1 + 29 + + + DMA2 + 30 + + + DMA3 + 31 + + + DMA4 + 68 + + + DMA5 + 69 + + + DMA6 + 70 + + + DMA7 + 71 + + + DMA8 + 72 + + + DMA9 + 73 + + + DMA10 + 74 + + + DMA11 + 75 + + + DMA12 + 76 + + + DMA13 + 77 + + + DMA14 + 78 + + + DMA15 + 79 + + + + CN + DMA Control Register. + 0x000 + + + CH0_IEN + Channel 0 Interrupt Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CH1_IEN + Channel 1 Interrupt Enable. + 1 + 1 + + + CH2_IEN + Channel 2 Interrupt Enable. + 2 + 1 + + + CH3_IEN + Channel 3 Interrupt Enable. + 3 + 1 + + + + + INTR + DMA Interrupt Register. + 0x004 + read-only + + + CH0_IPEND + Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. + 0 + 1 + + ch_ipend_enum + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CH1_IPEND + 1 + 1 + + + CH2_IPEND + 2 + 1 + + + CH3_IPEND + 3 + 1 + + + + + 4 + 4 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CFG + DMA Channel Configuration Register. + 0x100 + + + CHEN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQSEL + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPI0RX + SPI0 RX + 0x01 + + + SPI1RX + SPI1 RX + 0x02 + + + UART0RX + UART0 RX + 0x04 + + + UART1RX + UART1 RX + 0x05 + + + I2C0RX + I2C0 RX + 0x07 + + + I2C1RX + I2C1 RX + 0x08 + + + SPI0TX + SPI0 TX + 0x21 + + + SPI1TX + SPI1 TX + 0x22 + + + UART0TX + UART0 TX + 0x24 + + + UART1TX + UART1 TX + 0x25 + + + I2C0TX + I2C0 TX + 0x27 + + + I2C1TX + I2C1 TX + 0x28 + + + + + REQWAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOSEL + Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + PSSEL + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRCINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DSTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BRST + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + CHDIEN + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZIEN + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + ST + DMA Channel Status Register. + 0x104 + + + CH_ST + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_ST + Count-to-Zero (CTZ) Status + 2 + 1 + oneToClear + + ctz_st_enum_rd + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + ctz_st_enum_wr + write + + Clear + Clears the interrupt flag + 1 + + + + + RLD_ST + Reload Status. + 3 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + TO_ST + Time-Out Status. + 6 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x108 + + + ADDR + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x10C + + + ADDR + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x110 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRC_RLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x114 + + + SRC_RLD + Source Address Reload Value. + 0 + 31 + + + + + DST_RLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x118 + + + DST_RLD + Destination Address Reload Value. + 0 + 31 + + + + + CNT_RLD + DMA Channel Count Reload Register. + 0x11C + + + CNT_RLD + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + RLDEN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + + FLC + Flash Memory Control. + FLSH_ + 0x40029000 + + 0x00 + 0x1000 + registers + + + Flash_Controller + Flash Controller interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 + + + + + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 + + + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. + 0 + 8 + + + + + CN + Flash Control Register. + 0x08 + + + WR + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 + 1 + + + WDTH + Data Width. This bits selects write data width. + 4 + 1 + + + size128 + 128-bit. + 0 + + + size32 + 32-bit. + 1 + + + + + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 + + + nop + No operation. + 0 + + + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA + + + + + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + LVE + Low Voltage Read Enable + 25 + 1 + read-only + + lve_read + read + + dis + Disabled + 0 + + + en + Enabled + 1 + + + + + BRST + Burst Mode Enable. + 27 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 + + + unlocked + Flash Unlocked + 2 + + + locked + Flash Locked + 3 + + + + + + + INTR + Flash Interrupt Register. + 0x024 + + + DONE + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 + 1 + + + inactive + No interrupt is pending + 0 + + + pending + An interrupt is pending + 1 + + + + + AF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 + 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + + + + DONEIE + Flash Done Interrupt Enable. + 8 + 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + + + + AFIE + 9 + 1 + + + + + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 + + + DATA + Data next operation. + 0 + 32 + + + + + ACNTL + Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only + + + ACNTL + Access control. + 0 + 32 + + + + + + + + GCR + Global Control Registers. + 0x40000000 + + 0 + 0x400 + registers + + + + SCON + System Control. + 0x00 + 0xFFFFFFFE + + + SBUSARB + System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. + 1 + 2 + + + fix + Fixed Burst abritration. + 0 + + + round + Round-robin scheme. + 1 + + + + + FLASH_PAGE_FLIP + Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. + 4 + 1 + + + normal + Physical layout matches logical layout. + 0 + + + swapped + Bottom half mapped to logical top half and vice versa. + 1 + + + + + FPU_DIS + Floating Point Unit Disable + 5 + 1 + + + enable + enable Floating point unit + 0 + + + disable + disable floating point unit + 1 + + + + + CCACHE_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 + 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + + + + SWD_DIS + Serial Wire Debug Disable + 14 + 1 + + + enable + Enable JTAG SWD + 0 + + + disable + Disable JTAG SWD + 1 + + + + + + + RSTR0 + Reset. + 0x04 + + + DMA + DMA Reset. + 0 + 1 + + dma_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + dma_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + WDT + Watchdog Timer Reset. + 1 + 1 + + wdt_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + wdt_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 + + gpio0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + gpio0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + TIMER0 + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + 5 + 1 + + timer0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + timer0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + TIMER1 + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + 6 + 1 + + timer1_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + timer1_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + TIMER2 + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + 7 + 1 + + timer2_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + timer2_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + 11 + 1 + + uart0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + uart0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 + + uart1_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + uart1_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SPI0 + SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + 13 + 1 + + spi0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + spi0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 14 + 1 + + spi1_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + xpi1_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + I2C0 + I2C0 Reset. + 16 + 1 + + i2c0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + i2c0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + RTC + Real Time Clock Reset. + 17 + 1 + + rtc_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + rtc_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SRST + Soft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer. + 29 + 1 + + srst_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + srst_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + PRST + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + prst_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + prst_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SYSTEM + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 + + system_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + system_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + + + CLKCN + Clock Control. + 0x08 + 0x00000008 + + + PSC + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + CLKSEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + HIRC + The internal 96 MHz oscillator is used for the system clock. + 0 + + + nanoRing + The nano-ring output is used for the system clock. + 3 + + + hfxIn + HFXIN is used for the system clock. + 6 + + + + + CKRDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 + 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + + + + X32K_EN + 32kHz Crystal Oscillator Enable. + 17 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + HIRC_EN + 60MHz High Frequency Internal Reference Clock Enable. + 18 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + X32K_RDY + 32kHz Crystal Oscillator Ready + 25 + 1 + read-only + + + not + Not Ready + 0 + + + Ready + X32K Ready + 1 + + + + + HIRC_RDY + 60MHz HIRC Ready. + 26 + 1 + + + not + Not Ready + 0 + + + ready + HIRC Ready + 1 + + + + + LIRC8K_RDY + 8kHz Low Frequency Reference Clock Ready. + 29 + 1 + + + not + Not Ready + 0 + + + ready + Clock Ready + 1 + + + + + + + PM + Power Management. + 0x0C + + + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 + 3 + + + active + Active Mode. + 0 + + + shutdown + Shutdown Mode. + 3 + + + backup + Backup Mode. + 4 + + + + + GPIOWKEN + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + dis + Wake Up Disable. + 0 + + + en + Wake Up Enable. + 1 + + + + + RTCWKEN + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + dis + Wake Up Disable. + 0 + + + en + Wake Up Enable. + 1 + + + + + HIRCPD + HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode. + 15 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + + + PCKDIV + Peripheral Clock Divider. + 0x18 + 0x00000001 + + + AONCD + Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider. + 0 + 2 + + + div_4 + PCLK divide by 4. + 0 + + + div_8 + PCLK divide by 8. + 1 + + + div_16 + PCLK divide by 16. + 2 + + + div_32 + PCLK divide by 32. + 3 + + + + + + + PERCKCN0 + Peripheral Clock Disable. + 0x24 + + + GPIO0D + GPIO0 Disable. + 0 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + DMAD + DMA Disable. + 5 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + SPI0D + SPI 0 Disable. + 6 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + SPI1D + SPI 1 Disable. + 7 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + UART0D + UART 0 Disable. + 9 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + UART1D + UART 1 Disable. + 10 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + I2C0D + I2C 0 Disable. + 13 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + T0D + Timer 0 Disable. + 15 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + T1D + Timer 1 Disable. + 16 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + T2D + Timer 2 Disable. + 17 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + I2C1D + I2C 1 Disable. + 28 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + + + MEMCKCN + Memory Clock Control Register. + 0x28 + + + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + 0 + 3 + + + SYSRAM0LS + System RAM 0 Light Sleep Mode. + 8 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + SYSRAM1LS + System RAM 1 Light Sleep Mode. + 9 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + SYSRAM2LS + System RAM 2 Light Sleep Mode. + 10 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + SYSRAM3LS + System RAM 3 Light Sleep Mode. + 11 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + ICACHELS + ICache RAM Light Sleep Mode. + 12 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + + + MEMZCN + Memory Zeroize Control. + 0x2C + + + SRAM0Z + System RAM Block 0. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ICACHEZ + Instruction Cache. + 1 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + + + SCCK + Smart Card Clock Control. + 0x34 + 0x00001414 + + + MPRI0 + Master Priority Control Register 0. + 0x38 + 0x00001414 + + + MPRI1 + Mater Priority Control Register 1. + 0x3C + 0x00001414 + + + SYSST + System Status Register. + 0x40 + + + ICECLOCK + ARM ICE Lock Status. + 0 + 1 + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + CODEINTERR + Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. + 1 + 1 + + + norm + Normal Operating Condition. + 0 + + + code + Code Integrity Error. + 1 + + + + + SCMEMF + System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. + 5 + 1 + + + norm + Normal Operating Condition. + 0 + + + memory + Memory Fault. + 1 + + + + + + + RSTR1 + Reset 1. + 0x44 + + + I2C1 + I2C1 Reset. + 0 + 1 + + reset_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + reset_read + read + + reset_done + Reset complete. + 0 + + + busy + Reset in progress. + 1 + + + + + + + PERCKCN1 + Peripheral Clock Disable. + 0x48 + + + FLCD + Secure Flash Controller Disable. + 3 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + ICACHED + ICache Clock Disable. + 11 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + + + EVTEN + Event Enable Register. + 0x4C + + + DMAEVENT + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + RXEVENT + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + + + REVISION + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYSSIE + System Status Interrupt Enable Register. + 0x54 + + + ICEULIE + ARM ICE Unlock Interrupt Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + CIEIE + Code Integrity Error Interrupt Enable. + 1 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + SCMFIE + System Cache Memory Fault Interrupt Enable. + 5 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + + + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + + + EN + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 + + + GPIO_EN + Mask of all of the pins on the port. + 0 + 32 + + + alternate + Alternate function enabled. + 0 + + + GPIO + GPIO function is enabled. + 1 + + + + + + + EN_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT_EN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + GPIO_OUT_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Output Disable + 0 + + + en + GPIO Output Enable + 1 + + + + + + + OUT_EN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT_EN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + GPIO_OUT + Mask of all of the pins on the port. + 0 + 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + + + + + + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only + + + GPIO_OUT_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + + + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + + + GPIO_OUT_CLR + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + GPIO_IN + Mask of all of the pins on the port. + 0 + 32 + + + + + INT_MOD + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + GPIO_INT_MOD + Mask of all of the pins on the port. + 0 + 32 + + + level + Interrupts for this pin are level triggered. + 0 + + + edge + Interrupts for this pin are edge triggered. + 1 + + + + + + + INT_POL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + + + GPIO_INT_POL + Mask of all of the pins on the port. + 0 + 32 + + + falling + Interrupts are latched on a falling edge or low level condition for this pin. + 0 + + + rising + Interrupts are latched on a rising edge or high condition for this pin. + 1 + + + + + + + INT_EN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + + + GPIO_INT_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + Interrupts are disabled for this GPIO pin. + 0 + + + en + Interrupts are enabled for this GPIO pin. + 1 + + + + + + + INT_EN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + + + GPIO_INT_EN_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No effect. + 0 + + + set + Set GPIO_INT_EN bit in this position to '1' + 1 + + + + + + + INT_EN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + + + GPIO_INT_EN_CLR + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + clear + Clear GPIO_INT_EN bit in this position to '0' + 1 + + + + + + + INT_STAT + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + + + GPIO_INT_STAT + Mask of all of the pins on the port. + 0 + 32 + + + no + No Interrupt is pending on this GPIO pin. + 0 + + + pending + An Interrupt is pending on this GPIO pin. + 1 + + + + + + + INT_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WAKE_EN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + GPIO_WAKE_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + PMU wakeup for this GPIO is disabled. + 0 + + + en + PMU wakeup for this GPIO is enabled. + 1 + + + + + + + WAKE_EN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WAKE_EN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INT_DUAL_EDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + GPIO_INT_DUAL_EDGE + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. + 1 + + + + + + + PAD_CFG1 + GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x60 + + + GPIO_PAD_CFG1 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + PAD_CFG2 + GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x64 + + + GPIO_PAD_CFG2 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + + + GPIO_EN1 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + GPIO_EN2 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + IS + Input Hysteresis Enable Register + 0xA8 + + + SR + Slew Rate Select Register. + 0xAC + + + DS + GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + DS + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + + + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + PS + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + + I2C0 + Inter-Integrated Circuit. + I2C + 0x4001D000 + 32 + + 0x00 + 0x1000 + registers + + + I2C0 + I2C0 IRQ + 13 + + + + CTRL + Control Register0. + 0x00 + + + I2C_EN + I2C Enable. + [0:0] + read-write + + + dis + Disable I2C. + 0 + + + en + enable I2C. + 1 + + + + + MST + Master Mode Enable. + [1:1] + read-write + + + slave_mode + Slave Mode. + 0 + + + master_mode + Master Mode. + 1 + + + + + GEN_CALL_ADDR + General Call Address Enable. + [2:2] + read-write + + + dis + Ignore Gneral Call Address. + 0 + + + en + Acknowledge general call address. + 1 + + + + + RX_MODE + Interactive Receive Mode. + [3:3] + read-write + + + dis + Disable Interactive Receive Mode. + 0 + + + en + Enable Interactive Receive Mode. + 1 + + + + + RX_MODE_ACK + Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. + [4:4] + read-write + + + ack + return ACK (pulling SDA LOW). + 0 + + + nack + return NACK (leaving SDA HIGH). + 1 + + + + + SCL_OUT + SCL Output. This bits control SCL output when SWOE =1. + [6:6] + read-write + + + drive_scl_low + Drive SCL low. + 0 + + + release_scl + Release SCL. + 1 + + + + + SDA_OUT + SDA Output. This bits control SDA output when SWOE = 1. + [7:7] + read-write + + + drive_sda_low + Drive SDA low. + 0 + + + release_sda + Release SDA. + 1 + + + + + SCL + SCL status. This bit reflects the logic gate of SCL signal. + [8:8] + read-only + + + SDA + SDA status. THis bit reflects the logic gate of SDA signal. + [9:9] + read-only + + + SW_OUT_EN + Software Output Enable. + [10:10] + read-write + + + outputs_disable + I2C Outputs SCLO and SDAO disabled. + 0 + + + outputs_enable + I2C Outputs SCLO and SDAO enabled. + 1 + + + + + READ + Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. + [11:11] + read-only + + + write + Write. + 0 + + + read + Read. + 1 + + + + + SCL_CLK_STRECH_DIS + This bit will disable slave clock stretching when set. + [12:12] + read-write + + + en + Slave clock stretching enabled. + 0 + + + dis + Slave clock stretching disabled. + 1 + + + + + SCL_PP_MODE + SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. + [13:13] + read-write + + + dis + Standard open-drain operation: drive low for 0, Hi-Z for 1 + 0 + + + en + Non-standard push-pull operation: drive low for 0, drive high for 1 + 1 + + + + + HS_MODE + Hs-mode Enable. + 15 + 1 + + + dis + Hs-mode disabled. + 0 + + + en + Hs-mode enabled. + 1 + + + + + + + STATUS + Status Register. + 0x04 + + + BUS + Bus Status. + [0:0] + read-only + + + idle + I2C Bus Idle. + 0 + + + busy + I2C Bus Busy. + 1 + + + + + RX_EMPTY + RX empty. + [1:1] + read-only + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + RX_FULL + RX Full. + [2:2] + read-only + + + not_full + Not Full. + 0 + + + full + Full. + 1 + + + + + TX_EMPTY + TX Empty. + [3:3] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + TX_FULL + TX Full. + [4:4] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + CLK_MODE + Clock Mode. + [5:5] + read-only + + + not_actively_driving_scl_clock + Device not actively driving SCL clock cycles. + 0 + + + actively_driving_scl_clock + Device operating as master and actively driving SCL clock cycles. + 1 + + + + + STATUS + Controller Status. + [11:8] + + + idle + Controller Idle. + 0 + + + mtx_addr + master Transmit address. + 1 + + + mrx_addr_ack + Master Receive address ACK. + 2 + + + mtx_ex_addr + Master Transmit extended address. + 3 + + + mrx_ex_addr + Master Receive extended address ACK. + 4 + + + srx_addr + Slave Receive address. + 5 + + + stx_addr_ack + Slave Transmit address ACK. + 6 + + + srx_ex_addr + Slave Receive extended address. + 7 + + + stx_ex_addr_ack + Slave Transmit extended address ACK. + 8 + + + tx + Transmit data (master or slave). + 9 + + + rx_ack + Receive data ACK (master or slave). + 10 + + + rx + Receive data (master or slave). + 11 + + + tx_ack + Transmit data ACK (master or slave). + 12 + + + nack + NACK stage (master or slave). + 13 + + + by_st + Bystander state (ongoing transaction but not participant- another master addressing another slave). + 15 + + + + + + + INT_FL0 + Interrupt Status Register. + 0x08 + + + DONE + Transfer Done Interrupt. + [0:0] + + INT_FL0_Done + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RX_MODE + Interactive Receive Interrupt. + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + GEN_CALL_ADDR + Slave General Call Address Match Interrupt. + [2:2] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_MATCH + Slave Address Match Interrupt. + [3:3] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RX_THRESH + Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. + [4:4] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. RX_FIFO equal or more bytes than the threshold. + 1 + + + + + TX_THRESH + Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. + [5:5] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + STOP + STOP Interrupt. + [6:6] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + ADDR_ACK + Address Acknowledge Interrupt. + [7:7] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ARB_ER + Arbritation error Interrupt. + [8:8] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TO_ER + timeout Error Interrupt. + [9:9] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_NACK_ER + Address NACK Error Interrupt. + [10:10] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DATA_ER + Data NACK Error Interrupt. + [11:11] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DO_NOT_RESP_ER + Do Not Respond Error Interrupt. + [12:12] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START_ER + Start Error Interrupt. + [13:13] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + STOP_ER + Stop Error Interrupt. + [14:14] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_LOCK_OUT + Transmit Lock Out Interrupt. + [15:15] + + + + + INT_EN0 + Interrupt Enable Register. + 0x0C + read-write + + + DONE + Transfer Done Interrupt Enable. + [0:0] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when DONE = 1. + 1 + + + + + RX_MODE + Description not available. + [1:1] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when RX_MODE = 1. + 1 + + + + + GEN_CTRL_ADDR + Slave mode general call address match received input enable. + [2:2] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when GEN_CTRL_ADDR = 1. + 1 + + + + + ADDR_MATCH + Slave mode incoming address match interrupt. + [3:3] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when ADDR_MATCH = 1. + 1 + + + + + RX_THRESH + RX FIFO Above Treshold Level Interrupt Enable. + [4:4] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_THRESH + TX FIFO Below Treshold Level Interrupt Enable. + [5:5] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP + Stop Interrupt Enable + [6:6] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when STOP = 1. + 1 + + + + + ADDR_ACK + Received Address ACK from Slave Interrupt. + [7:7] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ARB_ER + Master Mode Arbitration Lost Interrupt. + [8:8] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TO_ER + Timeout Error Interrupt Enable. + [9:9] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ADDR_ER + Master Mode Address NACK Received Interrupt. + [10:10] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DATA_ER + Master Mode Data NACK Received Interrupt. + [11:11] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DO_NOT_RESP_ER + Slave Mode Do Not Respond Interrupt. + [12:12] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + START_ER + Out of Sequence START condition detected interrupt. + [13:13] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP_ER + Out of Sequence STOP condition detected interrupt. + [14:14] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_LOCK_OUT + TX FIFO Locked Out Interrupt. + [15:15] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when TXLOIE = 1. + 1 + + + + + + + INT_FL1 + Interrupt Status Register 1. + 0x10 + + + RX_OVERFLOW + Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + [0:0] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_UNDERFLOW + Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + + + INT_EN1 + Interrupt Staus Register 1. + 0x14 + read-write + + + RX_OVERFLOW + Receiver Overflow Interrupt Enable. + [0:0] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + TX_UNDERFLOW + Transmit Underflow Interrupt Enable. + [1:1] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + + + FIFO_LEN + FIFO Configuration Register. + 0x18 + + + RX_LEN + Receive FIFO Length. + [7:0] + read-only + + + TX_LEN + Transmit FIFO Length. + [15:8] + read-only + + + + + RX_CTRL0 + Receive Control Register 0. + 0x1C + + + DNR + Do Not Respond. + [0:0] + + + respond + Always respond to address match. + 0 + + + not_respond_rx_fifo_empty + Do not respond to address match when RX_FIFO is not empty. + 1 + + + + + RX_FLUSH + Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush RX_FIFO. + 1 + + + + + RX_THRESH + Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. + [11:8] + + + + + RX_CTRL1 + Receive Control Register 1. + 0x20 + + + RX_CNT + Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. + [7:0] + + + RX_FIFO + Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. + [11:8] + read-only + + + + + TX_CTRL0 + Transmit Control Register 0. + 0x24 + + + TX_PRELOAD + Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + [0:0] + + + TX_READY_MODE + Transmit FIFO Ready Manual Mode. + [1:1] + + + en + HW control of I2CTXRDY enabled. + 0 + + + dis + HW control of I2CTXRDY disabled. + 1 + + + + + TX_FLUSH + Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush TX_FIFO. + 1 + + + + + TX_THRESH + Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. + [11:8] + + + + + TX_CTRL1 + Transmit Control Register 1. + 0x28 + + + TX_READY + Transmit FIFO Preload Ready. + [0:0] + + + TX_LAST + Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware). + [1:1] + + + hold_scl_low + Hold SCL low on TX_FIFO empty. + 0 + + + end_transaction + End transaction on TX_FIFO empty. + 1 + + + + + TX_FIFO + Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. + [11:8] + read-only + + + + + FIFO + Data Register. + 0x2C + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + 0 + 8 + + + + + MASTER_CTRL + Master Control Register. + 0x30 + + + START + Setting this bit to 1 will start a master transfer. + [0:0] + + + RESTART + Setting this bit to 1 will generate a repeated START. + [1:1] + + + STOP + Setting this bit to 1 will generate a STOP condition. + [2:2] + + + SL_EX_ADDR + Slave Extend Address Select. + [7:7] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + MASTER_CODE + Master Code. These bits set the Master Code used in Hs-mode operation. + [10:8] + + + SCL_SPEED_UP + Serial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves. + [11:11] + + + en + Master monitors SCL state. + 0 + + + dis + SCL state monitoring disabled. + 1 + + + + + + + CLK_LO + Clock Low Register. + 0x34 + + + CLK_LO + Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. + [8:0] + + + + + CLK_HI + Clock high Register. + 0x38 + + + CKH + Clock High. In master mode, these bits define the SCL high period. + [8:0] + + + + + HS_CLK + HS-Mode Clock Control Register + 0x3C + + + HS_CLK_LO + Slave Address. + [7:0] + + + HS_CLK_HI + Slave Address. + [15:8] + + + + + TIMEOUT + Timeout Register + 0x40 + + + TO + Timeout + [15:0] + + + + + SLAVE_ADDR + Slave Address Register. + 0x44 + + + SLAVE_ADDR + Slave Address. + [9:0] + + + SLAVE_ADDR_DIS + Slave Address DIS. + [10:10] + + + SLAVE_ADDR_IDX + Slave Address Index. + [14:11] + + + EX_ADDR + Extended Address Select. + [15:15] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + + + DMA + DMA Register. + 0x48 + + + TX_EN + TX channel enable. + [0:0] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RX_EN + RX channel enable. + [1:1] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + I2C1 + Inter-Integrated Circuit. 1 + 0x4001E000 + + I2C1 + I2C1 IRQ + 36 + + + + + ICC0 + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x1000 + registers + + + + CACHE_ID + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + CCHID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + MEMCFG + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + + + CCHSZ + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEMSZ + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CACHE_CTRL + Cache Control and Status Register. + 0x0100 + + + CACHE_EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + CACHE_RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + + + + + + ICC1 + Instruction Cache Controller Registers 1 + 0x4002F000 + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x40006800 + + 0x00 + 0x800 + registers + + + + LP_CTRL + Low Power Control Register. + 0x00 + + + RAMRET_SEL0 + System RAM 0 Data retention in BACKUP mode. + 0 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RAMRET_SEL1 + System RAM 1 Data retention in BACKUP mode. + 1 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RAMRET_SEL2 + System RAM 2 Data retention in BACKUP mode. + 2 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RAMRET_SEL3 + System RAM 3 Data retention in BACKUP mode. + 3 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + OVR + Operating Voltage Range + 4 + 2 + + + 0_9V + 0.9V 24MHz + 0 + + + 1_0V + 1.0V 48MHz + 1 + + + 1_1V + 1.1V 96MHz + 2 + + + + + VCORE_DET_BYPASS + Bypass V CORE External Supply Detection + 6 + 1 + + + enabled + enable + 0 + + + Disable + disable + 1 + + + + + RETREG_EN + Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. + 8 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + FAST_WK_EN + Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. + 10 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + BG_OFF + Band Gap Disable for DEEPSLEEP and BACKUP Mode + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode(default). + 1 + + + + + VCORE_POR_DIS + V CORE POR Disable for DEEPSLEEP and BACKUP Mode + 12 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + LDO_DIS + LDO Disable + 16 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VCORE_SVM_DIS + V CORE Supply Voltage Monitor Disable + 20 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VDDIO_POR_DIS + VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. + 25 + 1 + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + + + LP_WAKEFL + Low Power Mode Wakeup Flags for GPIO0 + 0x04 + + + WAKEST + Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. + 0 + 14 + + + + + LPWK_EN + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + + + WAKEEN + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 14 + + + + + LPMEMSD + Low Power Memory Shutdown Control. + 0x40 + + + SRAM0_OFF + System RAM block 0 Shut Down. + 0 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM1_OFF + System RAM block 1 Shut Down. + 1 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM2_OFF + System RAM block 2 Shut Down. + 2 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM3_OFF + System RAM block 3 Shut Down. + 3 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + + + + + + RTC + Real Time Clock and Alarm. + 0x40006000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + RTSS + RTC Sub-second Counter. + 0 + 8 + + + + + RAS + Time-of-day Alarm. + 0x08 + 0x00000000 + + + RAS + Time-of-day Alarm. + 0 + 20 + + + + + RSSA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 + + + RSSA + This register contains the reload value for the sub-second alarm. + 0 + 32 + + + + + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + RTCE + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ADE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ASE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDYE + RTC Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ALDF + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + ALSF + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + SQE + Square Wave Output Enable. + 8 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + FT + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + + clkDiv8 + RTC Input Clock / 8. + 3 + + + + + X32KMD + 32KHz Oscillator Mode. + 11 + 2 + + + noiseImmuneMode + Always operate in Noise Immune Mode. Oscillator warm-up required. + 0 + + + quietMode + Always operate in Quiet Mode. No oscillator warm-up required. + 1 + + + quietInStopWithWarmup + Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit. + 2 + + + quietInStopNoWarmup + Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit. + 3 + + + + + WE + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + + + TRIM + RTC Trim Register. + 0x14 + 0x00000000 + + + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. + 0 + 8 + + + VBATTMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 + + + + + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 + + + FLITER_EN + RTC Oscillator Filter Enable + 0 + 1 + + + IBIAS_SEL + RTC Oscillator 4X Bias Current Select + 1 + 1 + + + 2X + Selects 2X bias current for RTC oscillator + 0 + + + 4X + Selects 4X bias current for RTC oscillator + 1 + + + + + HYST_EN + RTC Oscillator Hysteresis Buffer Enable + 2 + 1 + + + IBIAS_EN + RTC Oscillator Bias Current Enable + 3 + 1 + + + BYPASS + RTC Crystal Bypass + 4 + 1 + + + OUT32K + RTC 32kHz Square Wave Output + 5 + 1 + + + + + + + + SIR + System Initialization Registers. + 0x40000400 + read-only + + 0x00 + 0x400 + registers + + + + SISTAT + System Initialization Status Register. + 0x00 + read-only + + + MAGIC + Magic Word Validation. This bit is set by the system initialization block following power-up. + 0 + 1 + read-only + + read + + magicNotSet + Magic word was not set (OTP has not been initialized properly). + 0 + + + magicSet + Magic word was set (OTP contains valid settings). + 1 + + + + + CRCERR + CRC Error Status. This bit is set by the system initialization block following power-up. + 1 + 1 + read-only + + read + + noError + No CRC errors occurred during the read of the OTP memory block. + 0 + + + error + A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + 1 + + + + + + + ERRADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + 0x04 + read-only + + + ERRADDR + 0 + 32 + + + + + FSTAT + funcstat register. + 0x100 + read-only + + + FPU + FPU Function. + 0 + 1 + + + no + 0 + + + yes + 1 + + + + + USB + USB Device. + 1 + 1 + + + no + 0 + + + yes + 1 + + + + + ADC + 10-bit Sigma Delta ADC. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + XIP + XiP function. + 3 + 1 + + + no + 0 + + + yes + 1 + + + + + PBM + PBM function. + 4 + 1 + + + no + 0 + + + yes + 1 + + + + + HBC + HBC function. + 5 + 1 + + + no + 0 + + + yes + 1 + + + + + SDHC + SDHC function. + 6 + 1 + + + no + 0 + + + yes + 1 + + + + + SMPHR + SMPHR function. + 7 + 1 + + + no + 0 + + + yes + 1 + + + + + SCACHE + System Cache function. + 8 + 1 + + + no + 0 + + + yes + 1 + + + + + + + SFSTAT + secfuncstat register. + 0x104 + read-only + + + TRNG + TRNG function. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + AES + AES function. + 3 + 1 + + + no + 0 + + + yes + 1 + + + + + SHA + SHA function. + 4 + 1 + + + no + 0 + + + yes + 1 + + + + + MAA + MAA function. + 5 + 1 + + + no + 0 + + + yes + 1 + + + + + + + + + + SMON + The Security Monitor block used to monitor system threat conditions. + 0x40004000 + + 0x00 + 0x1000 + registers + + + + EXTSCN + External Sensor Control Register. + 0x00 + 0x3800FFC0 + + + EXTS_EN0 + External Sensor Enable for input/output pair 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN1 + External Sensor Enable for input/output pair 1. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN2 + External Sensor Enable for input/output pair 2. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN3 + External Sensor Enable for input/output pair 3. + 3 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN4 + External Sensor Enable for input/output pair 4. + 4 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTS_EN5 + External Sensor Enable for input/output pair 5. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + EXTCNT + External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered. + 16 + 5 + + + EXTFRQ + External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair. + 21 + 3 + + + freq2000Hz + Div 4 (2000Hz). + 0 + + + freq1000Hz + Div 8 (1000Hz). + 1 + + + freq500Hz + Div 16 (500Hz). + 2 + + + freq250Hz + Div 32 (250Hz). + 3 + + + freq125Hz + Div 64 (125Hz). + 4 + + + freq63Hz + Div 128 (63Hz). + 5 + + + freq31Hz + Div 256 (31Hz). + 6 + + + RFU + Reserved. Do not use. + 7 + + + + + DIVCLK + Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor. + 24 + 3 + + + div1 + Divide by 1 (8000 Hz). + 0 + + + div2 + Divide by 2 (4000 Hz). + 1 + + + div4 + Divide by 4 (2000 Hz). + 2 + + + div8 + Divide by 8 (1000 Hz). + 3 + + + div16 + Divide by 16 (500 Hz). + 4 + + + div32 + Divide by 32 (250 Hz). + 5 + + + div64 + Divide by 64 (125 Hz). + 6 + + + + + BUSY + Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain. + 30 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Update in Progress. + 1 + + + + + LOCK + Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. + 31 + 1 + + + unlocked + Unlocked. + 0 + + + locked + Locked. + 1 + + + + + + + INTSCN + Internal Sensor Control Register. + 0x04 + 0x7F00FFF7 + + + SHIELD_EN + Die Shield Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TEMP_EN + Temperature Sensor Enable. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VBAT_EN + Battery Monitor Enable. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + LOTEMP_SEL + Low Temperature Detection Select. + 16 + 1 + + + neg50C + -50 degrees C. + 0 + + + neg30C + -30 degrees C. + 1 + + + + + VCORELOEN + VCORE Undervoltage Detect Enable. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VCOREHIEN + VCORE Overvoltage Detect Enable. + 19 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VDDLOEN + VDD Undervoltage Detect Enable. + 20 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VDDHIEN + VDD Overvoltage Detect Enable. + 21 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + VGLEN + Voltage Glitch Detection Enable. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + LOCK + Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register. + 31 + 1 + + + unlocked + Unlocked. + 0 + + + locked + Locked. + 1 + + + + + + + SECALM + Security Alarm Register. + 0x08 + 0x00000000 + 0x00000000 + + + DRS + Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + KEYWIPE + Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped. + 1 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + SHIELDF + Die Shield Flag. + 2 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + LOTEMP + Low Temperature Detect. + 3 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + HITEMP + High Temperature Detect. + 4 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATLO + Battery Undervoltage Detect. + 5 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATHI + Battery Overvoltage Detect. + 6 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTF + External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. + 7 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VDDLO + VDD Undervoltage Detect Flag. + 8 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VCORELO + VCORE Undervoltage Detect Flag. + 9 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VCOREHI + VCORE Overvoltage Detect Flag. + 10 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VDDHI + VDD Overvoltage Flag. + 11 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + VGL + Voltage Glitch Detection Flag. + 12 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT0 + External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 16 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT1 + External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 17 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT2 + External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 18 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT3 + External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 19 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT4 + External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 20 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT5 + External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor. + 21 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN0 + External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 24 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN1 + External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 25 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN2 + External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 26 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN3 + External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 27 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN4 + External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 28 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSWARN5 + External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled. + 29 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + SECDIAG + Security Diagnostic Register. + 0x0C + read-only + 0x00000001 + 0xFFC0FE02 + + + BORF + Battery-On-Reset Flag. This bit is set once the back up battery is conneted. + 0 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + SHIELDF + Die Shield Flag. + 2 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + LOTEMP + Low Temperature Detect. + 3 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + HITEMP + High Temperature Detect. + 4 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATLO + Battery Undervoltage Detect. + 5 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + BATHI + Battery Overvoltage Detect. + 6 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + DYNF + Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set. + 7 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + AESKT + AES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR. + 8 + 1 + + + incomplete + Key has not been transferred. + 0 + + + complete + Key has been transferred. + 1 + + + + + EXTSTAT0 + External Sensor 0 Detect. + 16 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT1 + External Sensor 1 Detect. + 17 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT2 + External Sensor 2 Detect. + 18 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT3 + External Sensor 3 Detect. + 19 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT4 + External Sensor 4 Detect. + 20 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + EXTSTAT5 + External Sensor 5 Detect. + 21 + 1 + + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + DLRTC + DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred. + 0x10 + read-only + 0x00000000 + + + DLRTC + DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured. + 0 + 32 + + + + + SECST + Security Monitor Status Register. + 0x34 + read-only + + + EXTSRS + External Sensor Control Register Status. + 0 + 1 + + + allowed + Access authorized. + 0 + + + notAllowed + Access not authorized. + 1 + + + + + INTSRS + Internal Sensor Control Register Status. + 1 + 1 + + + allowed + Access authorized. + 0 + + + notAllowed + Access not authorized. + 1 + + + + + SECALRS + Security Alarm Register Status. + 2 + 1 + + + allowed + Access authorized. + 0 + + + notAllowed + Access not authorized. + 1 + + + + + + + + + + SPI17Y + SPI peripheral. + 0x40046000 + + 0x00 + 0x1000 + registers + + + SPI0 + 16 + + + + DATA32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + DATA16[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 16 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + DATA8[%s] + Register for reading and writing the FIFO. + DATA32 + 0x00 + 8 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL0 + Register for controlling SPI peripheral. + 0x04 + read-write + + + EN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + MASTER + Master Mode Enable. + 1 + 1 + + + dis + SPI is Slave mode. + 0 + + + en + SPI is Master mode. + 1 + + + + + SS_IO + Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + 4 + 1 + + + output + Slave select 0 is output. + 0 + + + input + Slave Select 0 is input, only valid if MMEN=1. + 1 + + + + + START + Start Transmit. + 5 + 1 + + + start + Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + 1 + + + + + SS_CTRL + Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + 8 + 1 + + + DEASSERT + SPI De-asserts Slave Select at the end of a transaction. + 0 + + + ASSERT + SPI leaves Slave Select asserted at the end of a transaction. + 1 + + + + + SS + Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + 16 + 4 + + + SS0 + SS0 is selected. + 0x1 + + + SS1 + SS1 is selected. + 0x2 + + + SS2 + SS2 is selected. + 0x4 + + + SS3 + SS3 is selected. + 0x8 + + + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CPHA + Clock Phase. + 0 + 1 + + + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 + 0 + + + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 + 1 + + + + + CPOL + Clock Polarity. + 1 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + SCLK_INV + Reserved - Must Always Be Cleared to 0. + 4 + 1 + + + NUMBITS + Number of Bits per character. + 8 + 4 + + + 0 + 16 bits per character. + 0 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + SS_POL + Slave Select Polarity, each Slave Select can have unique polarity. + 16 + 8 + + + SS0_high + SS0 active high. + 0x1 + + + SS1_high + SS1 active high. + 0x2 + + + SS2_high + SS2 active high. + 0x4 + + + SS3_high + SS3 active high. + 0x8 + + + + + SRPOL + Slave Ready Polarity, each Slave Ready can have unique polarity. + 24 + 8 + + + SR0_high + SR0 active high. + 0x1 + + + SR1_high + SR1 active high. + 0x2 + + + SR2_high + SR2 active high. + 0x4 + + + SR3_high + SR3 active high. + 0x8 + + + SR4_high + SR4 active high. + 0x10 + + + SR5_high + SR5 active high. + 0x20 + + + SR6_high + SR6 active high. + 0x40 + + + SR7_high + SR7 active high. + 0x80 + + + + + + + SS_TIME + Register for controlling SPI peripheral/Slave Select Timing. + 0x10 + read-write + + + PRE + Slave Select Pre delay 1. + 0 + 8 + + + 256 + 256 system clocks between SS active and first serial clock edge. + 0 + + + + + POST + Slave Select Post delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and SS inactive. + 0 + + + + + INACT + Slave Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + CLK_CFG + Register for controlling SPI clock rate. + 0x14 + read-write + + + LO + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + SCALE + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_FIFO_LEVEL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FIFO_CLEAR + Clear TX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + . + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_FIFO_CNT + Count of entries in TX FIFO. + 8 + 6 + read-only + + + TX_DMA_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_FIFO_LEVEL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FIFO_CLEAR + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. + 1 + + + + + RX_FIFO_CNT + Count of entries in RX FIFO. + 24 + 6 + read-only + + + RX_DMA_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + INT_FL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_THRESH + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THRESH + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSA + Slave Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSD + Slave Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + FAULT + Multi-Master Mode Fault. + 8 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Slave Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + M_DONE + Master Done, set when SPI Master has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OVR + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UND + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OVR + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UND + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + INT_EN + Register for enabling interrupts. + 0x24 + read-write + + + TX_THRESH + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EMPTY + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_THRESH + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSA + Slave Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSD + Slave Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Master Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Slave Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + M_DONE + Master Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OVR + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UND + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OVR + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UND + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WAKE_FL + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_THRESH + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THRESH + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WAKE_EN + Register for wake up enable. + 0x2C + read-write + + + TX_THRESH + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_THRESH + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STAT + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + + + + SPIMSS + Serial Peripheral Interface. + SPIMSS0_ + 0x40018000 + + 0x00 + 0x1000 + registers + + + + DATA16 + SPI 16-bit Data Access + 0x00 + 16 + read-write + + + DATA + SPI data. + 0 + 16 + + + + + 2 + 1 + DATA8[%s] + SPI Data 8-bit access + DATA16 + 0x00 + 8 + read-write + + + DATA + SPI data. + 0 + 8 + + + + + CTRL + SPI Control Register. + 0x04 + + + SPIEN + SPI Enable. + 0 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + MMEN + SPI Master Mode Enable. + 1 + 1 + + slv_mst_enum + + slave + 0 + + + master + 1 + + + + + WOR + Wired OR (open drain) Enable. + 2 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + CLKPOL + Clock Polarity. + 3 + 1 + + spi_pol_enum + + idleLo + SCLK idles Low (0) after character transmission/reception. + 0 + + + idleHi + SCLK idles High (1) after character transmission/reception. + 1 + + + + + PHASE + Phase Select. + 4 + 1 + + spi_phase_enum + + activeEdge + Transmit on active edge of SCLK. + 0 + + + inactiveEdge + Transmit on inactive edge of SCLK. + 1 + + + + + BIRQ + Baud Rate Generator Timer Interrupt Request. + 5 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + STR + Start SPI Interrupt. + 6 + 1 + + start_op_enum + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + IRQE + Interrupt Request Enable. + 7 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + + + STATUS + SPI Status Register. + 0x08 + 0x00000001 + + + SLAS + Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning. + 0 + 1 + read-only + + sel_enum + + selected + 0 + + + notSelected + 1 + + + + + TXST + Transmit Status. + 1 + 1 + read-only + + busy_enum + + idle + 0 + + + busy + 1 + + + + + TUND + Transmit Underrun. + 2 + 1 + oneToClear + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + ROVR + Receive Overrun. + 3 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + ABT + Slave Mode Transaction Abort. + 4 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + COL + Collision. + 5 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + TOVR + Transmit Overrun. + 6 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + IRQ + SPI Interrupt Request. + 7 + 1 + oneToClear + + flag_enum + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + + + MOD + SPI Mode Register. + 0x0C + + + SSV + Slave Select Value. + 0 + 1 + + lo_hi_enum + + lo + The SSEL pin will be driven low. + 0 + + + hi + The SSEL pin will be driven high. + 1 + + + + + SSIO + Slave Select I/O. + 1 + 1 + + input_output_enum + + input + 0 + + + output + 1 + + + + + NUMBITS + 2 + 4 + + spi_bits_enum + + bits16 + 0 + + + bits1 + 1 + + + bits2 + 2 + + + bits3 + 3 + + + bits4 + 4 + + + bits5 + 5 + + + bits6 + 6 + + + bits7 + 7 + + + bits8 + 8 + + + bits9 + 9 + + + bits10 + 10 + + + bits11 + 11 + + + bits12 + 12 + + + bits13 + 13 + + + bits14 + 14 + + + bits15 + 15 + + + + + TX_LJ + Transmit Left Justify. + 7 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + SSL1 + Slave Select 1. If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit. + 8 + 1 + + hi_lo_enum + + hi + High. + 0 + + + lo + Low. + 1 + + + + + SSL2 + Slave Select 2. If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit. + 9 + 1 + + hi_lo_enum + + hi + High. + 0 + + + lo + Low. + 1 + + + + + SSL3 + Slave Select 3. If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit. + 10 + 1 + + hi_lo_enum + + hi + High. + 0 + + + lo + Low. + 1 + + + + + + + BRG + Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4). + 0x14 + 0x0000FFFF + + + BRG + Baud Rate Reload Value. + 0 + 16 + + + + + DMA + SPI DMA Register. + 0x18 + 0x00070007 + + + TX_FIFO_LEVEL + Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs. + 0 + 3 + + fifo_level_enum + + entry1 + 0 + + + entries2 + 1 + + + entries3 + 2 + + + entries4 + 3 + + + entries5 + 4 + + + entries6 + 5 + + + entries7 + 6 + + + entries8 + 7 + + + + + TX_FIFO_CLEAR + Transmit FIFO Clear. + 4 + 1 + write-only + + start_op_enum + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + TX_FIFO_CNT + Transmit FIFO Count. + 8 + 4 + read-only + + + TX_DMA_EN + Transmit DMA Enable. + 15 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + RX_FIFO_LEVEL + Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request. + 16 + 3 + + fifo_level_enum + + entry1 + 0 + + + entries2 + 1 + + + entries3 + 2 + + + entries4 + 3 + + + entries5 + 4 + + + entries6 + 5 + + + entries7 + 6 + + + entries8 + 7 + + + + + RX_FIFO_CLEAR + Receive FIFO Clear. + 20 + 1 + + start_op_enum + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + RX_FIFO_CNT + Receive FIFO Count. + 24 + 4 + read-only + + + RX_DMA_EN + Receive DMA Enable. + 31 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + + + I2S_CTRL + I2S Control Register. + 0x1C + + + I2S_EN + I2S Mode Enable. + 0 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + I2S_MUTE + I2S Mute transmit. + 1 + 1 + + + normal + Normal Transmit. + 0 + + + replaced + Transmit data is replaced with 0. + 1 + + + + + I2S_PAUSE + I2S Pause transmit/receive. + 2 + 1 + + + normal + Normal Transmit. + 0 + + + halt + Halt transmit and receive FIFO and DMA access, transmit 0's. + 1 + + + + + I2S_MONO + I2S Monophonic Audio Mode. + 3 + 1 + + + stereophonic + Stereophonic audio. + 0 + + + monophonic + Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored. + 1 + + + + + I2S_LJ + I2S Left Justify. + 4 + 1 + + + normal + Normal I2S audio protocol. + 0 + + + replaced + Audio data is synchronized with SSEL. + 1 + + + + + + + + + + TMR0 + 32-bit reloadable timer that can be used for timing and event counting. + Timers + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR0 + TMR0 IRQ + 5 + + + + CNT + Count. This register stores the current timer count. + 0x00 + 0x00000001 + + + CMP + Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + 0x04 + 0x0000FFFF + + + PWM + PWM. This register stores the value that is compared to the current timer count. + 0x08 + + + INTR + Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + 0x0C + oneToClear + + + IRQ_CLR + Clear Interrupt. + 0 + 1 + + + + + CN + Timer Control Register. + 0x10 + + + TMODE + Timer Mode. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + pwm + PWM Mode. + 3 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + PRES + Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + TPOL + Timer input/output polarity bit. + 6 + 1 + + + activeHi + Active High. + 0 + + + activeLo + Active Low. + 1 + + + + + TEN + Timer Enable. + 7 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRES3 + MSB of prescaler value. + 8 + 1 + + + PWMSYNC + Timer PWM Synchronization Mode Enable. + 9 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLHPOL + Timer PWM output 0A polarity bit. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLLPOL + Timer PWM output 0A' polarity bit. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PWMCKBD + Timer PWM output 0A Mode Disable. + 12 + 1 + + + dis + Disable. + 1 + + + en + Enable. + 0 + + + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + + + NOLLCMP + Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + 0 + 8 + + + NOLHCMP + Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + 8 + 8 + + + + + + + + TMR1 + 32-bit reloadable timer that can be used for timing and event counting. 1 + 0x40011000 + + TMR1 + TMR1 IRQ + 6 + + + + + TMR2 + 32-bit reloadable timer that can be used for timing and event counting. 2 + 0x40012000 + + TMR2 + TMR2 IRQ + 7 + + + + + UART0 + UART + 0x40042000 + + 0 + 0x1000 + registers + + + UART0 + UART0 IRQ + 14 + + + + CTRL + Control Register. + 0x00 + 32 + + + ENABLE + UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled. + 0 + 1 + + + dis + UART disabled. FIFOs are flushed. Clock is gated off for power savings. + 0 + + + en + UART enabled. + 1 + + + + + PARITY_EN + Enable/disable Parity bit (9th character). + 1 + 1 + + + dis + No Parity + 0 + + + en + Parity enabled as 9th bit + 1 + + + + + PARITY + When PARITY_EN=1, selects odd, even, Mark or Space parity. + Mark parity = always 1; Space parity = always 0. + 2 + 2 + + + Even + Even parity selected. + 0 + + + ODD + Odd parity selected. + 1 + + + MARK + Mark parity selected. + 2 + + + SPACE + Space parity selected. + 3 + + + + + PARMD + Selects parity based on 1s or 0s count (when PARITY_EN=1). + 4 + 1 + + + 1 + Parity calculation is based on number of 1s in frame. + 0 + + + 0 + Parity calculation is based on number of 0s in frame. + 1 + + + + + TX_FLUSH + Flushes the TX FIFO buffer. + 5 + 1 + + + RX_FLUSH + Flushes the RX FIFO buffer. + 6 + 1 + + + BITACC + If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation. + 7 + 1 + + + FRAME + Frame accuracy. + 0 + + + BIT + Bit accuracy. + 1 + + + + + CHAR_SIZE + Selects UART character size. + 8 + 2 + + + 5 + 5 bits. + 0 + + + 6 + 6 bits. + 1 + + + 7 + 7 bits. + 2 + + + 8 + 8 bits. + 3 + + + + + STOPBITS + Selects the number of stop bits that will be generated. + 10 + 1 + + + 1 + 1 stop bit. + 0 + + + 1_5 + 1.5 stop bits. + 1 + + + + + FLOW_CTRL + Enables/disables hardware flow control. + 11 + 1 + + + en + HW Flow Control with RTS/CTS enabled + 1 + + + dis + HW Flow Control disabled + 0 + + + + + FLOW_POL + RTS/CTS polarity. + 12 + 1 + + + 0 + RTS/CTS asserted is logic 0. + 0 + + + 1 + RTS/CTS asserted is logic 1. + 1 + + + + + NULL_MODEM + NULL Modem Support (RTS/CTS and TXD/RXD swap). + 13 + 1 + + + DIS + Direct convention. + 0 + + + EN + Null Modem Mode. + 1 + + + + + BREAK + Break control bit. It causes a break condition to be transmitted to receiving UART. + 14 + 1 + + + DIS + Break characters are not generated. + 0 + + + EN + Break characters are sent(all the bits are at '0' including start/parity/stop). + 1 + + + + + CLKSEL + Baud Rate Clock Source Select. Selects the baud rate clock. + 15 + 1 + + + SYSTEM + System clock. + 0 + + + ALTERNATE + Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. + 1 + + + + + RX_TO + RX Time Out. RX time out interrupt will occur after RXTO Uart + characters if RX-FIFO is not empty and RX FIFO has not been read. + 16 + 8 + + + + + THRESH_CTRL + Threshold Control register. + 0x04 + 32 + + + RX_FIFO_THRESH + RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. + 0 + 6 + + + TX_FIFO_THRESH + TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. + 8 + 6 + + + RTS_FIFO_THRESH + RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. + 16 + 6 + + + + + STATUS + Status Register. + 0x08 + 32 + read-only + + + TX_BUSY + Read-only flag indicating the UART transmit status. + 0 + 1 + read-only + + + RX_BUSY + Read-only flag indicating the UARTreceiver status. + 1 + 1 + read-only + + + PARITY + 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. + 2 + 1 + read-only + + + BREAK + Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). + 3 + 1 + read-only + + + RX_EMPTY + Read-only flag indicating the RX FIFO state. + 4 + 1 + read-only + + + RX_FULL + Read-only flag indicating the RX FIFO state. + 5 + 1 + read-only + + + TX_EMPTY + Read-only flag indicating the TX FIFO state. + 6 + 1 + read-only + + + TX_FULL + Read-only flag indicating the TX FIFO state. + 7 + 1 + read-only + + + RX_FIFO_CNT + Indicates the number of bytes currently in the RX FIFO. + 8 + 6 + read-only + + + TX_FIFO_CNT + Indicates the number of bytes currently in the TX FIFO. + 16 + 6 + read-only + + + RX_TO + RX Timeout status. + 24 + 1 + read-only + + + + + INT_EN + Interrupt Enable Register. + 0x0C + 32 + + + RX_FRAME_ERROR + Enable for RX Frame Error Interrupt. + 0 + 1 + + + RX_PARITY_ERROR + Enable for RX Parity Error interrupt. + 1 + 1 + + + CTS_CHANGE + Enable for CTS signal change interrupt. + 2 + 1 + + + RX_OVERRUN + Enable for RX FIFO OVerrun interrupt. + 3 + 1 + + + RX_FIFO_THRESH + Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + 4 + 1 + + + TX_FIFO_ALMOST_EMPTY + Enable for interrupt when TX FIFO has only one byte remaining. + 5 + 1 + + + TX_FIFO_THRESH + Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. + 6 + 1 + + + BREAK + Enable for received BREAK character interrupt. + 7 + 1 + + + RX_TIMEOUT + Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). + 8 + 1 + + + LAST_BREAK + Enable for Last break character interrupt. + 9 + 1 + + + + + INT_FL + Interrupt Status Flags. + 0x10 + 32 + oneToClear + + + RX_FRAME_ERROR + FLAG for RX Frame Error Interrupt. + 0 + 1 + + + RX_PARITY_ERROR + FLAG for RX Parity Error interrupt. + 1 + 1 + + + CTS_CHANGE + FLAG for CTS signal change interrupt. + 2 + 1 + + + RX_OVERRUN + FLAG for RX FIFO Overrun interrupt. + 3 + 1 + + + RX_FIFO_THRESH + FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + 4 + 1 + + + TX_FIFO_ALMOST_EMPTY + FLAG for interrupt when TX FIFO has only one byte remaining. + 5 + 1 + + + TX_FIFO_THRESH + FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. + 6 + 1 + + + BREAK + FLAG for received BREAK character interrupt. + 7 + 1 + + + RX_TIMEOUT + FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). + 8 + 1 + + + LAST_BREAK + FLAG for Last break character interrupt. + 9 + 1 + + + + + BAUD0 + Baud rate register. Integer portion. + 0x14 + 32 + + + IBAUD + Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). + 0 + 12 + + + FACTOR + FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR. + 16 + 2 + + + 128 + Baud Factor 128 + 0 + + + 64 + Baud Factor 64 + 1 + + + 32 + Baud Factor 32 + 2 + + + 16 + Baud Factor 16 + 3 + + + + + + + BAUD1 + Baud rate register. Decimal Setting. + 0x18 + 32 + + + DBAUD + Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128. + 0 + 12 + + + + + FIFO + FIFO Data buffer. + 0x1C + 32 + + + FIFO + Load/unload location for TX and RX FIFO buffers. + 0 + 8 + + + + + DMA + DMA Configuration. + 0x20 + 32 + + + TDMA_EN + TX DMA channel enable. + 0 + 1 + + + dis + DMA is disabled + 0 + + + en + DMA is enabled + 1 + + + + + RXDMA_EN + RX DMA channel enable. + 1 + 1 + + + dis + DMA is disabled + 0 + + + en + DMA is enabled + 1 + + + + + TXDMA_LEVEL + TX threshold for DMA transmission. + 8 + 6 + + + RXDMA_LEVEL + RX threshold for DMA transmission. + 16 + 6 + + + + + TX_FIFO + Transmit FIFO Status register. + 0x24 + 32 + + + DATA + Reading from this field returns the next character available at the + output of the TX FIFO (if one is available, otherwise 00h is returned). + 0 + 7 + + + + + + + + UART1 + UART 1 + 0x40043000 + + UART1 + UART1 IRQ + 15 + + + + + WDT0 + Watchdog Timer 0 + 0x40003000 + + 0x00 + 0x0400 + registers + + + WDT0 + 1 + + + + CTRL + Watchdog Timer Control Register. + 0x00 + 0x7FFFF000 + + + INT_PERIOD + Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 0 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_PERIOD + Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 4 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + WDT_EN + Watchdog Timer Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_FLAG + Watchdog Timer Interrupt Flag. + 9 + 1 + oneToClear + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + INT_EN + Watchdog Timer Interrupt Enable. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_EN + Watchdog Timer Reset Enable. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_FLAG + Watchdog Timer Reset Flag. + 31 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + RST + Watchdog Timer Reset Register. + 0x04 + write-only + + + WDT_RST + Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled. + 0 + 8 + + + seq0 + The first value to be written to reset the WDT. + 0x000000A5 + + + seq1 + The second value to be written to reset the WDT. + 0x0000005A + + + + + + + + + + diff --git a/bsp/maxim/MAX32660_EVSYS/project.uvoptx b/bsp/maxim/MAX32660_EVSYS/project.uvoptx index ff7f9de14e..a8359d025b 100644 --- a/bsp/maxim/MAX32660_EVSYS/project.uvoptx +++ b/bsp/maxim/MAX32660_EVSYS/project.uvoptx @@ -117,26 +117,6 @@ BIN\CMSIS_AGDI.dll - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - - 0 CMSIS_AGDI @@ -155,12 +135,12 @@ 0 0 - 1 + 0 0 0 0 0 - 1 + 0 0 0 0 @@ -223,7 +203,7 @@ CPU - 1 + 0 0 0 0 @@ -291,7 +271,7 @@ DeviceDrivers - 1 + 0 0 0 0 @@ -407,7 +387,7 @@ Drivers - 1 + 0 0 0 0 @@ -463,7 +443,7 @@ finsh - 1 + 0 0 0 0 @@ -507,7 +487,7 @@ Kernel - 1 + 0 0 0 0 diff --git a/bsp/maxim/MAX32660_EVSYS/project.uvprojx b/bsp/maxim/MAX32660_EVSYS/project.uvprojx index 7b23a65cbc..5f53b9696b 100644 --- a/bsp/maxim/MAX32660_EVSYS/project.uvprojx +++ b/bsp/maxim/MAX32660_EVSYS/project.uvprojx @@ -188,7 +188,7 @@ 0 0 8 - 1 + 0 0 0 0 diff --git a/bsp/maxim/MAX32660_EVSYS/rtconfig.h b/bsp/maxim/MAX32660_EVSYS/rtconfig.h index a15112c1b2..a2f3204096 100644 --- a/bsp/maxim/MAX32660_EVSYS/rtconfig.h +++ b/bsp/maxim/MAX32660_EVSYS/rtconfig.h @@ -10,7 +10,7 @@ #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_USING_IDLE_HOOK diff --git a/bsp/maxim/MAX32660_EVSYS/rtconfig.py b/bsp/maxim/MAX32660_EVSYS/rtconfig.py index 3d7c28a68c..97130e34f5 100644 --- a/bsp/maxim/MAX32660_EVSYS/rtconfig.py +++ b/bsp/maxim/MAX32660_EVSYS/rtconfig.py @@ -13,7 +13,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' + EXEC_PATH = r'.' elif CROSS_TOOL == 'keil': PLATFORM = 'armcc' EXEC_PATH = 'C:/Keil_v5' @@ -34,13 +34,14 @@ if PLATFORM == 'gcc': CC = PREFIX + 'gcc' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' LINK = PREFIX + 'gcc' TARGET_EXT = 'elf' SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + DEVICE = ' -mcpu=cortex-m4 -mthumb' CFLAGS = DEVICE AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' diff --git a/bsp/maxim/MAX32660_EVSYS/template.uvprojx b/bsp/maxim/MAX32660_EVSYS/template.uvprojx index 1ea2e5a7ba..47b809b51d 100644 --- a/bsp/maxim/MAX32660_EVSYS/template.uvprojx +++ b/bsp/maxim/MAX32660_EVSYS/template.uvprojx @@ -188,7 +188,7 @@ 0 0 8 - 1 + 0 0 0 0 diff --git a/bsp/maxim/libraries/HAL_Drivers/SConscript b/bsp/maxim/libraries/HAL_Drivers/SConscript index f6262f54da..ae053a38d5 100644 --- a/bsp/maxim/libraries/HAL_Drivers/SConscript +++ b/bsp/maxim/libraries/HAL_Drivers/SConscript @@ -20,6 +20,9 @@ if GetDepend(['RT_USING_PWM']): if GetDepend(['RT_USING_SPI']): src += ['drv_spi.c'] +if GetDepend(['RT_USING_I2C']): + src += ['drv_i2c.c'] + if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): src += ['drv_soft_i2c.c'] diff --git a/bsp/maxim/libraries/HAL_Drivers/drv_i2c.c b/bsp/maxim/libraries/HAL_Drivers/drv_i2c.c new file mode 100644 index 0000000000..ddacdf0a12 --- /dev/null +++ b/bsp/maxim/libraries/HAL_Drivers/drv_i2c.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-26 Jackistang first version + * + */ + +#include "drv_i2c.h" +#include "i2c.h" +#include +#include +#include "board.h" + +#ifdef RT_USING_I2C + +#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1) + #error "Please define at least one BSP_USING_I2Cx" + /* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable I2C */ +#endif + +#define DBG_LEVEL DBG_LOG +#include +#define LOG_TAG "drv.i2c" + +/* mxc config class */ +struct mxc_i2c_config +{ + const char *name; + mxc_i2c_regs_t *i2c_periph; + i2c_speed_t speed; + IRQn_Type irq_type; +}; + +struct mxc_i2c +{ + struct rt_i2c_bus_device bus; + struct mxc_i2c_config *config; +}; + +static struct mxc_i2c_config i2c_config[] = +{ +#ifdef BSP_USING_I2C0 + { + .name = "i2c0", + .i2c_periph = MXC_I2C_GET_I2C(0), + .irq_type = MXC_I2C_GET_IRQ(0), + .speed = I2C_STD_MODE, + /*I2C_STD_MODE: 100KHz, I2C_FAST_MODE: 400KHz, I2C_FASTPLUS_MODE: 1MHz, I2C_HS_MODE: 3.4MHz */ + }, +#endif +#ifdef BSP_USING_I2C1 + { + .name = "i2c1", + .i2c_periph = MXC_I2C_GET_I2C(1), + .irq_type = MXC_I2C_GET_IRQ(1), + .speed = I2C_STD_MODE, + /*I2C_STD_MODE: 100KHz, I2C_FAST_MODE: 400KHz, I2C_FASTPLUS_MODE: 1MHz, I2C_HS_MODE: 3.4MHz */ + }, +#endif +}; + +static struct mxc_i2c i2c_obj[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0}; + + +static rt_size_t mxc_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + rt_uint32_t i, ret; + rt_uint16_t addr; + int error; + int restart = 0; + struct rt_i2c_msg *msg; + struct mxc_i2c *obj = (struct mxc_i2c *)bus; + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + + if (msg->flags & RT_I2C_ADDR_10BIT || msg->flags & RT_I2C_NO_START || msg->flags & RT_I2C_IGNORE_NACK || msg->flags & RT_I2C_NO_READ_ACK) + { + LOG_E("Not support RT_I2C_ADDR_10BIT or RT_I2C_NO_START or RT_I2C_IGNORE_NACK or RT_I2C_NO_READ_ACK"); + return 0; + } + + if (msg->flags & RT_I2C_NO_STOP) + { + restart = 1; + } + + if (msg->flags & RT_I2C_RD) + { + addr = msg->addr << 1; + if ((error = I2C_MasterRead(obj->config->i2c_periph, (uint8_t)addr, msg->buf, msg->len, restart)) != msg->len) + { + LOG_E("Error writing %d", error); + return 0; + } + } + else /* RT_I2C_WR */ + { + addr = msg->addr << 1; + if ((error = I2C_MasterWrite(obj->config->i2c_periph, (uint8_t)addr, msg->buf, msg->len, restart)) != msg->len) + { + LOG_E("Error writing %d", error); + return 0; + } + } + } + ret = i; + + return ret; +} + +static const struct rt_i2c_bus_device_ops mxc_i2c_ops = +{ + mxc_i2c_mst_xfer, + RT_NULL, + RT_NULL, +}; + +int rt_hw_i2c_init(void) +{ + rt_size_t obj_num; + int index; + rt_err_t result = 0; + +#ifdef BSP_USING_I2C0 + NVIC_EnableIRQ(I2C0_IRQn); +#endif +#ifdef BSP_USING_I2C1 + NVIC_EnableIRQ(I2C1_IRQn); +#endif + + obj_num = sizeof(i2c_obj) / sizeof(struct mxc_i2c); + for (index = 0; index < obj_num; index++) + { + /* init i2c object */ + i2c_obj[index].config = &i2c_config[index]; + i2c_obj[index].bus.ops = &mxc_i2c_ops; + + /* init i2c device */ + I2C_Shutdown(i2c_config[index].i2c_periph); + I2C_Init(i2c_config[index].i2c_periph, i2c_config[index].speed, RT_NULL); + + /* register i2c device */ + result = rt_i2c_bus_device_register(&i2c_obj[index].bus, + i2c_obj[index].config->name + ); + RT_ASSERT(result == RT_EOK); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#ifdef BSP_USING_I2C0 +void I2C0_IRQHandler(void) +{ + rt_interrupt_enter(); + I2C_Handler(MXC_I2C0); + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_I2C1 +void I2C1_IRQHandler(void) +{ + rt_interrupt_enter(); + I2C_Handler(MXC_I2C1); + rt_interrupt_leave(); +} +#endif + +#endif /* RT_USING_I2C */ diff --git a/bsp/maxim/libraries/HAL_Drivers/drv_i2c.h b/bsp/maxim/libraries/HAL_Drivers/drv_i2c.h new file mode 100644 index 0000000000..f1be28755c --- /dev/null +++ b/bsp/maxim/libraries/HAL_Drivers/drv_i2c.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-02-26 Jackistang first version + * + */ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + + +#endif /* __DRV_I2C_H__ */ diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S index c7ca195d79..9b9c71de9b 100644 --- a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S @@ -223,7 +223,7 @@ Reset_Handler: blx r0 /* Transfer control to users main program */ - ldr r0, =main + ldr r0, =entry blx r0 .SPIN: diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c index 1d404cc48d..0f3b061e8a 100644 --- a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c +++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c @@ -95,6 +95,9 @@ __weak void SystemCoreClockUpdate(void) __weak int PreInit(void) { /* Do nothing */ +#if defined ( __CC_ARM ) + SystemInit(); +#endif return 0; } @@ -145,23 +148,23 @@ __weak void SystemInit(void) Board_Init(); } -#if defined ( __CC_ARM ) -/* Global variable initialization does not occur until post scatterload in Keil tools.*/ +//#if defined ( __CC_ARM ) +///* Global variable initialization does not occur until post scatterload in Keil tools.*/ -/* External function called after our post scatterload function implementation. */ -extern void $Super$$__main_after_scatterload(void); +///* External function called after our post scatterload function implementation. */ +//extern void $Super$$__main_after_scatterload(void); -/** - * @brief Initialization function for SystemCoreClock and Board_Init. - * @details $Sub$$__main_after_scatterload is called during system startup in the Keil - * toolset. Global variable and static variable space must be set up by the compiler - * prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init - * require global memory for variable storage and are called from this function in - * the Keil tool chain. - */ -void $Sub$$__main_after_scatterload(void) -{ - SystemInit(); - $Super$$__main_after_scatterload(); -} -#endif /* __CC_ARM */ +///** +// * @brief Initialization function for SystemCoreClock and Board_Init. +// * @details $Sub$$__main_after_scatterload is called during system startup in the Keil +// * toolset. Global variable and static variable space must be set up by the compiler +// * prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init +// * require global memory for variable storage and are called from this function in +// * the Keil tool chain. +// */ +//void $Sub$$__main_after_scatterload(void) +//{ +// SystemInit(); +// $Super$$__main_after_scatterload(); +//} +//#endif /* __CC_ARM */ diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index 68920bbb93..ffdf1668f2 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -17,7 +17,6 @@ STM32 系列 BSP 目前支持情况如下表所示： | [stm32f103-fire-arbitrary](stm32f103-fire-arbitrary/) | 野火 F103 霸道开发板 | | [stm32f103-gizwits-gokitv21](stm32f103-gizwits-gokitv21) | GoKit V2.1开发板 | | [stm32f103-hw100k-ibox](stm32f103-hw100k-ibox) | 硬件十万个为什么 STM32F103 iBox 开发板 | -| [stm32f103-mini-system](stm32f103-mini-system) | STM32F103C8T6最小系统板 | | [stm32f103-onenet-nbiot](stm32f103-onenet-nbiot) | STM32F103 OneNET NB-IoT 开发板 | | [stm32f103-yf-ufun](stm32f103-yf-ufun) | STM32F103 yf-ufun 开发板 | | [stm32f107-uc-eval](stm32f107-uc-eval) | uC/Eval STM32F107 评估板（中国版） | diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript index a991e588d0..ce482829bd 100644 --- a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript +++ b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript @@ -119,6 +119,10 @@ if GetDepend(['BSP_USING_CRYP']): src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp.c'] src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp_ex.c'] +if GetDepend(['BSP_USING_RTC']): + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc.c'] + src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc_ex.c'] + path = [cwd + '/STM32MP1xx_HAL_Driver/Inc', cwd + '/CMSIS/Device/ST/STM32MP1xx/Include', cwd + '/CMSIS/Core/Include', diff --git a/bsp/stm32/stm32f103-mini-system/.config b/bsp/stm32/stm32f103-mini-system/.config deleted file mode 100644 index 7f2ef00287..0000000000 --- a/bsp/stm32/stm32f103-mini-system/.config +++ /dev/null @@ -1,341 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMTRACE is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40001 -CONFIG_ARCH_ARM=y -CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M3=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -CONFIG_FINSH_USING_MSH_ONLY=y -CONFIG_FINSH_ARG_MAX=10 - -# -# Device virtual file system -# -# CONFIG_RT_USING_DFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_PIPE_BUFSZ=512 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set - -# -# Using WiFi -# -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -# CONFIG_RT_USING_LIBC is not set -# CONFIG_RT_USING_PTHREADS is not set - -# -# Network -# - -# -# Socket abstraction layer -# -# CONFIG_RT_USING_SAL is not set - -# -# light weight TCP/IP stack -# -# CONFIG_RT_USING_LWIP is not set - -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set - -# -# AT commands -# -# CONFIG_RT_USING_AT is not set - -# -# VBUS(Virtual Software BUS) -# -# CONFIG_RT_USING_VBUS is not set - -# -# Utilities -# -# CONFIG_RT_USING_LOGTRACE is not set -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_LWP is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_AT_DEVICE is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_libsodium is not set -# CONFIG_PKG_USING_TINYCRYPT is not set - -# -# language packages -# -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set - -# -# multimedia packages -# -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set - -# -# system packages -# -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_STM32_SDIO is not set - -# -# miscellaneous packages -# -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# -# CONFIG_PKG_USING_HELLO is not set -CONFIG_SOC_FAMILY_STM32=y -CONFIG_SOC_SERIES_STM32F1=y - -# -# Hardware Drivers Config -# -CONFIG_SOC_STM32F103C8=y - -# -# Onboard Peripheral Drivers -# -CONFIG_BSP_USING_USB_TO_USART=y - -# -# On-chip Peripheral Drivers -# -CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART1=y -CONFIG_BSP_UART1_RX_USING_DMA=y -# CONFIG_BSP_USING_SPI is not set -# CONFIG_BSP_USING_ADC is not set - -# -# Board extended module Drivers -# diff --git a/bsp/stm32/stm32f103-mini-system/.gitignore b/bsp/stm32/stm32f103-mini-system/.gitignore deleted file mode 100644 index 7221bde019..0000000000 --- a/bsp/stm32/stm32f103-mini-system/.gitignore +++ /dev/null @@ -1,42 +0,0 @@ -*.pyc -*.map -*.dblite -*.elf -*.bin -*.hex -*.axf -*.exe -*.pdb -*.idb -*.ilk -*.old -build -Debug -documentation/html -packages/ -*~ -*.o -*.obj -*.out -*.bak -*.dep -*.lib -*.i -*.d -.DS_Stor* -.config 3 -.config 4 -.config 5 -Midea-X1 -*.uimg -GPATH -GRTAGS -GTAGS -.vscode -JLinkLog.txt -JLinkSettings.ini -DebugConfig/ -RTE/ -settings/ -*.uvguix* -cconfig.h diff --git a/bsp/stm32/stm32f103-mini-system/Kconfig b/bsp/stm32/stm32f103-mini-system/Kconfig deleted file mode 100644 index 7a400db91f..0000000000 --- a/bsp/stm32/stm32f103-mini-system/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "../libraries/Kconfig" -source "board/Kconfig" - diff --git a/bsp/stm32/stm32f103-mini-system/README.md b/bsp/stm32/stm32f103-mini-system/README.md deleted file mode 100644 index ee163c4beb..0000000000 --- a/bsp/stm32/stm32f103-mini-system/README.md +++ /dev/null @@ -1,110 +0,0 @@ -# STM32F103C8T6最小系统板 BSP 说明 - -## 简介 - -本文档为 STM32F103C8T6最小系统板 的 BSP (板级支持包) 说明。 - -主要内容如下： - -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 - -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 - -## 开发板介绍 - -STM32F103C8T6最小系统，采用SWD调试接口，可以用3个接口就能完成调试下载的任务，采用了官方建议的负载RTC晶振方案，小体积高频率的STM32实验板 - -开发板外观如下图所示： - -![board](figures/board.png) - -该开发板常用 **板载资源** 如下： - -- MCU：STM32F103C8T6，主频 72MHz，64KB FLASH ，20KB RAM -- 外部 RAM：无 -- 外部 FLASH：无 -- 常用外设 - - LED：1个，DS0（黄色，PC13） -- 常用接口：无 -- 调试接口，SWD调试接口 - -开发板更多详细信息请参考[STM32F103C8T6最小系统板介绍] - -## 外设支持 - -本 BSP 目前对外设的支持情况如下： - -| **板载外设** | **支持情况** | **备注** | -| :----------------- | :----------: | :------------------------------------- | -| 黄色LED | 支持 | PC13 | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PC15 ---> PIN: 0, 1...47 | -| UART | 支持 | UART1 | -| **扩展模块** | **支持情况** | **备注** | -| | | | - -## 使用说明 - -使用说明分为如下两个章节： - -- 快速上手 - - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，LED 闪烁 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.1 build Mar 10 2019 - 2006 - 2019 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 ADC、PWM等更多高级功能，再用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -- 只能用USB转TTL连接PC机 ; - -## 联系人信息 - -维护人: - -- [obito0](https://github.com/obito0), 邮箱：<496420502@qq.com> \ No newline at end of file diff --git a/bsp/stm32/stm32f103-mini-system/SConscript b/bsp/stm32/stm32f103-mini-system/SConscript deleted file mode 100644 index 20f7689c53..0000000000 --- a/bsp/stm32/stm32f103-mini-system/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/stm32/stm32f103-mini-system/SConstruct b/bsp/stm32/stm32f103-mini-system/SConstruct deleted file mode 100644 index 1a9f419db5..0000000000 --- a/bsp/stm32/stm32f103-mini-system/SConstruct +++ /dev/null @@ -1,60 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rt-thread.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') - -Export('RTT_ROOT') -Export('rtconfig') - -SDK_ROOT = os.path.abspath('./') - -if os.path.exists(SDK_ROOT + '/libraries'): - libraries_path_prefix = SDK_ROOT + '/libraries' -else: - libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' - -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -stm32_library = 'STM32F1xx_HAL' -rtconfig.BSP_LIBRARY_TYPE = stm32_library - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) - -# include drivers -objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f103-mini-system/applications/SConscript b/bsp/stm32/stm32f103-mini-system/applications/SConscript deleted file mode 100644 index ef1c39fd83..0000000000 --- a/bsp/stm32/stm32f103-mini-system/applications/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd, ] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/stm32/stm32f103-mini-system/applications/main.c b/bsp/stm32/stm32f103-mini-system/applications/main.c deleted file mode 100644 index c5fa5a5958..0000000000 --- a/bsp/stm32/stm32f103-mini-system/applications/main.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-08 obito0 first version - */ - -#include -#include -#include - -/* defined the LED0 pin: PC13 */ -#define LED0_PIN GET_PIN(C, 13) - -int main(void) -{ - int count = 1; - /* set LED0 pin mode to output */ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - - while (count++) - { - rt_pin_write(LED0_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED0_PIN, PIN_LOW); - rt_thread_mdelay(500); - } - - return RT_EOK; -} diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/.mxproject deleted file mode 100644 index 934c2d572a..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/.mxproject +++ /dev/null @@ -1,14 +0,0 @@ -[PreviousGenFiles] -HeaderPath=F:/rt-thread/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc -HeaderFiles=stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h; -SourcePath=F:/rt-thread/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src -SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c; - -[PreviousLibFiles] -LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; - -[PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null; -HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc; -CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;STM32F103xB; - diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/CubeMX_Config.ioc deleted file mode 100644 index 6dfacfbd4b..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/CubeMX_Config.ioc +++ /dev/null @@ -1,140 +0,0 @@ -#MicroXplorer Configuration settings - do not modify -ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1 -ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag -ADC1.NbrOfConversionFlag=1 -ADC1.Rank-0\#ChannelRegularConversion=1 -ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5 -ADC1.master=1 -File.Version=6 -KeepUserPlacement=false -Mcu.Family=STM32F1 -Mcu.IP0=ADC1 -Mcu.IP1=NVIC -Mcu.IP2=RCC -Mcu.IP3=SPI1 -Mcu.IP4=SYS -Mcu.IP5=USART1 -Mcu.IPNb=6 -Mcu.Name=STM32F103C(8-B)Tx -Mcu.Package=LQFP48 -Mcu.Pin0=PC14-OSC32_IN -Mcu.Pin1=PC15-OSC32_OUT -Mcu.Pin10=PA13 -Mcu.Pin11=PA14 -Mcu.Pin12=VP_SYS_VS_Systick -Mcu.Pin2=PD0-OSC_IN -Mcu.Pin3=PD1-OSC_OUT -Mcu.Pin4=PA1 -Mcu.Pin5=PA5 -Mcu.Pin6=PA6 -Mcu.Pin7=PA7 -Mcu.Pin8=PA9 -Mcu.Pin9=PA10 -Mcu.PinsNb=13 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32F103C8Tx -MxCube.Version=5.2.1 -MxDb.Version=DB.5.0.21 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -PA1.Signal=ADCx_IN1 -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA13.Mode=Serial_Wire -PA13.Signal=SYS_JTMS-SWDIO -PA14.Mode=Serial_Wire -PA14.Signal=SYS_JTCK-SWCLK -PA5.Mode=Full_Duplex_Master -PA5.Signal=SPI1_SCK -PA6.Mode=Full_Duplex_Master -PA6.Signal=SPI1_MISO -PA7.Mode=Full_Duplex_Master -PA7.Signal=SPI1_MOSI -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX -PC14-OSC32_IN.Mode=LSE-External-Oscillator -PC14-OSC32_IN.Signal=RCC_OSC32_IN -PC15-OSC32_OUT.Mode=LSE-External-Oscillator -PC15-OSC32_OUT.Signal=RCC_OSC32_OUT -PCC.Checker=false -PCC.Line=STM32F103 -PCC.MCU=STM32F103C(8-B)Tx -PCC.PartNumber=STM32F103C8Tx -PCC.Seq0=0 -PCC.Series=STM32F1 -PCC.Temperature=25 -PCC.Vdd=3.3 -PD0-OSC_IN.Mode=HSE-External-Oscillator -PD0-OSC_IN.Signal=RCC_OSC_IN -PD1-OSC_OUT.Mode=HSE-External-Oscillator -PD1-OSC_OUT.Signal=RCC_OSC_OUT -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32F103C8Tx -ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.7.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=0 -ProjectManager.MainLocation=Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=CubeMX_Config.ioc -ProjectManager.ProjectName=CubeMX_Config -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=MDK-ARM V5 -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true -RCC.ADCFreqValue=8000000 -RCC.AHBFreq_Value=16000000 -RCC.APB1CLKDivider=RCC_HCLK_DIV2 -RCC.APB1Freq_Value=8000000 -RCC.APB1TimFreq_Value=16000000 -RCC.APB2Freq_Value=16000000 -RCC.APB2TimFreq_Value=16000000 -RCC.FCLKCortexFreq_Value=16000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=16000000 -RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value -RCC.MCOFreq_Value=16000000 -RCC.PLLCLKFreq_Value=16000000 -RCC.PLLMCOFreq_Value=8000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.SYSCLKFreq_VALUE=16000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.TimSysFreq_Value=16000000 -RCC.USBFreq_Value=16000000 -RCC.VCOOutput2Freq_Value=8000000 -SH.ADCx_IN1.0=ADC1_IN1,IN1 -SH.ADCx_IN1.ConfNb=1 -SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8 -SPI1.CalculateBaudRate=2.0 MBits/s -SPI1.Direction=SPI_DIRECTION_2LINES -SPI1.IPParameters=VirtualType,Mode,Direction,BaudRatePrescaler,CalculateBaudRate -SPI1.Mode=SPI_MODE_MASTER -SPI1.VirtualType=VM_MASTER -USART1.IPParameters=VirtualMode -USART1.VirtualMode=VM_ASYNC -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -board=custom diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/main.h deleted file mode 100644 index 75cb6f9a15..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/main.h +++ /dev/null @@ -1,71 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H -#define __MAIN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f1xx_hal.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void Error_Handler(void); - -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -/* Private defines -----------------------------------------------------------*/ -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MAIN_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h deleted file mode 100644 index 467a07d1ca..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h +++ /dev/null @@ -1,370 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f1xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_CONF_H -#define __STM32F1xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ - -#define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_CAN_MODULE_ENABLED */ -/*#define HAL_CEC_MODULE_ENABLED */ -/*#define HAL_CORTEX_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -/*#define HAL_DMA_MODULE_ENABLED */ -/*#define HAL_ETH_MODULE_ENABLED */ -/*#define HAL_FLASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/*#define HAL_I2C_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_NOR_MODULE_ENABLED */ -/*#define HAL_NAND_MODULE_ENABLED */ -/*#define HAL_PCCARD_MODULE_ENABLED */ -/*#define HAL_PCD_MODULE_ENABLED */ -/*#define HAL_HCD_MODULE_ENABLED */ -/*#define HAL_PWR_MODULE_ENABLED */ -/*#define HAL_RCC_MODULE_ENABLED */ -/*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SD_MODULE_ENABLED */ -/*#define HAL_MMC_MODULE_ENABLED */ -/*#define HAL_SDRAM_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -#define HAL_SPI_MODULE_ENABLED -/*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ -/*#define HAL_EXTI_MODULE_ENABLED */ - -#define HAL_CORTEX_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ - -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2 -#define MAC_ADDR1 0 -#define MAC_ADDR2 0 -#define MAC_ADDR3 0 -#define MAC_ADDR4 0 -#define MAC_ADDR5 0 - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FF) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) - -#define PHY_READ_TO ((uint32_t)0x0000FFFF) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f1xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f1xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f1xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f1xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f1xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f1xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f1xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f1xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f1xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f1xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f1xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f1xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f1xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f1xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f1xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f1xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f1xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f1xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f1xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f1xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f1xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f1xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f1xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f1xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f1xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f1xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f1xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f1xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f1xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f1xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f1xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f1xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_it.h b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_it.h deleted file mode 100644 index 101d8aa728..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_it.h +++ /dev/null @@ -1,69 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f1xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_IT_H -#define __STM32F1xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/main.c deleted file mode 100644 index 0fb8a9747d..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/main.c +++ /dev/null @@ -1,325 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN PTD */ - -/* USER CODE END PTD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -ADC_HandleTypeDef hadc1; - -SPI_HandleTypeDef hspi1; - -UART_HandleTypeDef huart1; - -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -static void MX_GPIO_Init(void); -static void MX_USART1_UART_Init(void); -static void MX_ADC1_Init(void); -static void MX_SPI1_Init(void); -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_USART1_UART_Init(); - MX_ADC1_Init(); - MX_SPI1_Init(); - /* USER CODE BEGIN 2 */ - - /* USER CODE END 2 */ - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ -} - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; - PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } -} - -/** - * @brief ADC1 Initialization Function - * @param None - * @retval None - */ -static void MX_ADC1_Init(void) -{ - - /* USER CODE BEGIN ADC1_Init 0 */ - - /* USER CODE END ADC1_Init 0 */ - - ADC_ChannelConfTypeDef sConfig = {0}; - - /* USER CODE BEGIN ADC1_Init 1 */ - - /* USER CODE END ADC1_Init 1 */ - /** Common config - */ - hadc1.Instance = ADC1; - hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; - hadc1.Init.ContinuousConvMode = DISABLE; - hadc1.Init.DiscontinuousConvMode = DISABLE; - hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc1.Init.NbrOfConversion = 1; - if (HAL_ADC_Init(&hadc1) != HAL_OK) - { - Error_Handler(); - } - /** Configure Regular Channel - */ - sConfig.Channel = ADC_CHANNEL_1; - sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ADC1_Init 2 */ - - /* USER CODE END ADC1_Init 2 */ - -} - -/** - * @brief SPI1 Initialization Function - * @param None - * @retval None - */ -static void MX_SPI1_Init(void) -{ - - /* USER CODE BEGIN SPI1_Init 0 */ - - /* USER CODE END SPI1_Init 0 */ - - /* USER CODE BEGIN SPI1_Init 1 */ - - /* USER CODE END SPI1_Init 1 */ - /* SPI1 parameter configuration*/ - hspi1.Instance = SPI1; - hspi1.Init.Mode = SPI_MODE_MASTER; - hspi1.Init.Direction = SPI_DIRECTION_2LINES; - hspi1.Init.DataSize = SPI_DATASIZE_8BIT; - hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; - hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; - hspi1.Init.NSS = SPI_NSS_SOFT; - hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; - hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; - hspi1.Init.TIMode = SPI_TIMODE_DISABLE; - hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - hspi1.Init.CRCPolynomial = 10; - if (HAL_SPI_Init(&hspi1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SPI1_Init 2 */ - - /* USER CODE END SPI1_Init 2 */ - -} - -/** - * @brief USART1 Initialization Function - * @param None - * @retval None - */ -static void MX_USART1_UART_Init(void) -{ - - /* USER CODE BEGIN USART1_Init 0 */ - - /* USER CODE END USART1_Init 0 */ - - /* USER CODE BEGIN USART1_Init 1 */ - - /* USER CODE END USART1_Init 1 */ - huart1.Instance = USART1; - huart1.Init.BaudRate = 115200; - huart1.Init.WordLength = UART_WORDLENGTH_8B; - huart1.Init.StopBits = UART_STOPBITS_1; - huart1.Init.Parity = UART_PARITY_NONE; - huart1.Init.Mode = UART_MODE_TX_RX; - huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart1.Init.OverSampling = UART_OVERSAMPLING_16; - if (HAL_UART_Init(&huart1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART1_Init 2 */ - - /* USER CODE END USART1_Init 2 */ - -} - -/** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) -{ - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - - /* USER CODE END Error_Handler_Debug */ -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t *file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c deleted file mode 100644 index 663b3021fa..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c +++ /dev/null @@ -1,286 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : stm32f1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN Define */ - -/* USER CODE END Define */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN Macro */ - -/* USER CODE END Macro */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* External functions --------------------------------------------------------*/ -/* USER CODE BEGIN ExternalFunctions */ - -/* USER CODE END ExternalFunctions */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_AFIO_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); - - /* System interrupt init*/ - - /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled - */ - __HAL_AFIO_REMAP_SWJ_NOJTAG(); - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - -/** -* @brief ADC MSP Initialization -* This function configures the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspInit 0 */ - - /* USER CODE END ADC1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_ADC1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA1 ------> ADC1_IN1 - */ - GPIO_InitStruct.Pin = GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN ADC1_MspInit 1 */ - - /* USER CODE END ADC1_MspInit 1 */ - } - -} - -/** -* @brief ADC MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspDeInit 0 */ - - /* USER CODE END ADC1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA1 ------> ADC1_IN1 - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1); - - /* USER CODE BEGIN ADC1_MspDeInit 1 */ - - /* USER CODE END ADC1_MspDeInit 1 */ - } - -} - -/** -* @brief SPI MSP Initialization -* This function configures the hardware resources used in this example -* @param hspi: SPI handle pointer -* @retval None -*/ -void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hspi->Instance==SPI1) - { - /* USER CODE BEGIN SPI1_MspInit 0 */ - - /* USER CODE END SPI1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_SPI1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**SPI1 GPIO Configuration - PA5 ------> SPI1_SCK - PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI - */ - GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_6; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN SPI1_MspInit 1 */ - - /* USER CODE END SPI1_MspInit 1 */ - } - -} - -/** -* @brief SPI MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hspi: SPI handle pointer -* @retval None -*/ -void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) -{ - if(hspi->Instance==SPI1) - { - /* USER CODE BEGIN SPI1_MspDeInit 0 */ - - /* USER CODE END SPI1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_SPI1_CLK_DISABLE(); - - /**SPI1 GPIO Configuration - PA5 ------> SPI1_SCK - PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); - - /* USER CODE BEGIN SPI1_MspDeInit 1 */ - - /* USER CODE END SPI1_MspDeInit 1 */ - } - -} - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspInit(UART_HandleTypeDef* huart) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(huart->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspInit 0 */ - - /* USER CODE END USART1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_USART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration - PA9 ------> USART1_TX - PA10 ------> USART1_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN USART1_MspInit 1 */ - - /* USER CODE END USART1_MspInit 1 */ - } - -} - -/** -* @brief UART MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) -{ - if(huart->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspDeInit 0 */ - - /* USER CODE END USART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration - PA9 ------> USART1_TX - PA10 ------> USART1_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); - - /* USER CODE BEGIN USART1_MspDeInit 1 */ - - /* USER CODE END USART1_MspDeInit 1 */ - } - -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_it.c b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_it.c deleted file mode 100644 index 6a95ce4bae..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_it.c +++ /dev/null @@ -1,203 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f1xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "stm32f1xx_it.h" -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ - -/* USER CODE BEGIN EV */ - -/* USER CODE END EV */ - -/******************************************************************************/ -/* Cortex-M3 Processor Interruption and Exception Handlers */ -/******************************************************************************/ -/** - * @brief This function handles Non maskable interrupt. - */ -void NMI_Handler(void) -{ - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - - /* USER CODE END NonMaskableInt_IRQn 1 */ -} - -/** - * @brief This function handles Hard fault interrupt. - */ -void HardFault_Handler(void) -{ - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Memory management fault. - */ -void MemManage_Handler(void) -{ - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } -} - -/** - * @brief This function handles Prefetch fault, memory access fault. - */ -void BusFault_Handler(void) -{ - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Undefined instruction or illegal state. - */ -void UsageFault_Handler(void) -{ - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } -} - -/** - * @brief This function handles System service call via SWI instruction. - */ -void SVC_Handler(void) -{ - /* USER CODE BEGIN SVCall_IRQn 0 */ - - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ - - /* USER CODE END SVCall_IRQn 1 */ -} - -/** - * @brief This function handles Debug monitor. - */ -void DebugMon_Handler(void) -{ - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - - /* USER CODE END DebugMonitor_IRQn 1 */ -} - -/** - * @brief This function handles Pendable request for system service. - */ -void PendSV_Handler(void) -{ - /* USER CODE BEGIN PendSV_IRQn 0 */ - - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ - - /* USER CODE END PendSV_IRQn 1 */ -} - -/** - * @brief This function handles System tick timer. - */ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32F1xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32f1xx.s). */ -/******************************************************************************/ - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/system_stm32f1xx.c b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/system_stm32f1xx.c deleted file mode 100644 index af3759a3b6..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/system_stm32f1xx.c +++ /dev/null @@ -1,448 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f1xx.c - * @author MCD Application Team - * @version V4.2.0 - * @date 31-March-2017 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * factors, AHB/APBx prescalers and Flash settings). - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f1xx_xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to - * configure the system clock before to branch to main program. - * - * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on - * the product used), refer to "HSE_VALUE". - * When HSE is used as system clock source, directly or through PLL, and you - * are using different crystal you have to adapt the HSE value to your own - * configuration. - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f1xx_system - * @{ - */ - -/** @addtogroup STM32F1xx_System_Private_Includes - * @{ - */ - -#include "stm32f1xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F1xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F1xx_System_Private_Defines - * @{ - */ - -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI_VALUE */ - -/*!< Uncomment the following line if you need to use external SRAM */ -#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) -/* #define DATA_IN_ExtSRAM */ -#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/** - * @} - */ - -/** @addtogroup STM32F1xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F1xx_System_Private_Variables - * @{ - */ - -/******************************************************************************* -* Clock Definitions -*******************************************************************************/ -#if defined(STM32F100xB) ||defined(STM32F100xE) - uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = 72000000U; /*!< System Clock Frequency (Core Clock) */ -#endif - -const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; - -/** - * @} - */ - -/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes - * @{ - */ - -#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ - -/** - * @} - */ - -/** @addtogroup STM32F1xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= 0x00000001U; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#if !defined(STM32F105xC) && !defined(STM32F107xC) - RCC->CFGR &= 0xF8FF0000U; -#else - RCC->CFGR &= 0xF0FF0000U; -#endif /* STM32F105xC */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= 0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= 0xFF80FFFFU; - -#if defined(STM32F105xC) || defined(STM32F107xC) - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= 0xEBFFFFFFU; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000U; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000U; -#elif defined(STM32F100xB) || defined(STM32F100xE) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000U; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000U; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000U; -#endif /* STM32F105xC */ - -#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) - #ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); - #endif /* DATA_IN_ExtSRAM */ -#endif - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz or 25 MHz, depending on the product used), user has to ensure - * that HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; - -#if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; -#endif /* STM32F105xC */ - -#if defined(STM32F100xB) || defined(STM32F100xE) - uint32_t prediv1factor = 0U; -#endif /* STM32F100xB or STM32F100xE */ - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00U: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04U: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08U: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - -#if !defined(STM32F105xC) && !defined(STM32F107xC) - pllmull = ( pllmull >> 18U) + 2U; - - if (pllsource == 0x00U) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; - } - else - { - #if defined(STM32F100xB) || defined(STM32F100xE) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18U; - - if (pllmull != 0x0DU) - { - pllmull += 2U; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13U / 2U; - } - - if (pllsource == 0x00U) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; - - if (prediv1source == 0U) - { - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; - SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F105xC */ - break; - - default: - SystemCoreClock = HSI_VALUE; - break; - } - - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) -/** - * @brief Setup the external memory controller. Called in startup_stm32f1xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f1xx_xx.s/.c before jump to main. - * This function configures the external SRAM mounted on STM3210E-EVAL - * board (STM32 High density devices). This SRAM will be used as program - * data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ - __IO uint32_t tmpreg; - /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is - required, then adjust the Register Addresses */ - - /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114U; - - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0U; - - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); - - (void)(tmpreg); - -/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ -/*---------------- SRAM Address lines configuration -------------------------*/ -/*---------------- NOE and NWE configuration --------------------------------*/ -/*---------------- NE3 configuration ----------------------------------------*/ -/*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CRL = 0x44BB44BBU; - GPIOD->CRH = 0xBBBBBBBBU; - - GPIOE->CRL = 0xB44444BBU; - GPIOE->CRH = 0xBBBBBBBBU; - - GPIOF->CRL = 0x44BBBBBBU; - GPIOF->CRH = 0xBBBB4444U; - - GPIOG->CRL = 0x44BBBBBBU; - GPIOG->CRH = 0x444B4B44U; - -/*---------------- FSMC Configuration ---------------------------------------*/ -/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - - FSMC_Bank1->BTCR[4U] = 0x00001091U; - FSMC_Bank1->BTCR[5U] = 0x00110212U; -} -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f103-mini-system/board/Kconfig b/bsp/stm32/stm32f103-mini-system/board/Kconfig deleted file mode 100644 index fe4bec029d..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/Kconfig +++ /dev/null @@ -1,81 +0,0 @@ -menu "Hardware Drivers Config" - -config SOC_STM32F103C8 - bool - select SOC_SERIES_STM32F1 - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -menu "Onboard Peripheral Drivers" - - config BSP_USING_USB_TO_USART - bool "Enable USB TO USART (uart1)" - select BSP_USING_UART - select BSP_USING_UART1 - default y - -endmenu - -menu "On-chip Peripheral Drivers" - - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - menuconfig BSP_USING_UART - bool "Enable UART" - default y - select RT_USING_SERIAL - if BSP_USING_UART - config BSP_USING_UART1 - bool "Enable UART1" - default y - - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default n - endif - - menuconfig BSP_USING_SPI - bool "Enable SPI BUS" - default n - select RT_USING_SPI - if BSP_USING_SPI - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" - default n - - config BSP_SPI1_TX_USING_DMA - bool "Enable SPI1 TX DMA" - depends on BSP_USING_SPI1 - default n - - config BSP_SPI1_RX_USING_DMA - bool "Enable SPI1 RX DMA" - depends on BSP_USING_SPI1 - select BSP_SPI1_TX_USING_DMA - default n - endif - - menuconfig BSP_USING_ADC - bool "Enable ADC" - default n - select RT_USING_ADC - if BSP_USING_ADC - config BSP_USING_ADC1 - bool "Enable ADC1" - default n - - endif - source "../libraries/HAL_Drivers/Kconfig" - -endmenu - -menu "Board extended module Drivers" - -endmenu - -endmenu diff --git a/bsp/stm32/stm32f103-mini-system/board/SConscript b/bsp/stm32/stm32f103-mini-system/board/SConscript deleted file mode 100644 index 713a0e4b8f..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/SConscript +++ /dev/null @@ -1,35 +0,0 @@ -import os -import rtconfig -from building import * - -Import('SDK_LIB') - -cwd = GetCurrentDir() - -# add general drivers -src = Split(''' -board.c -CubeMX_Config/Src/stm32f1xx_hal_msp.c -''') - -path = [cwd] -path += [cwd + '/CubeMX_Config/Inc'] - -startup_path_prefix = SDK_LIB - -if rtconfig.CROSS_TOOL == 'gcc': - src += [startup_path_prefix + '/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xb.s'] -elif rtconfig.CROSS_TOOL == 'keil': - src += [startup_path_prefix + '/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xb.s'] -elif rtconfig.CROSS_TOOL == 'iar': - src += [startup_path_prefix + '/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103xb.s'] - -# STM32F100xB || STM32F100xE || STM32F101x6 -# STM32F101xB || STM32F101xE || STM32F101xG -# STM32F102x6 || STM32F102xB || STM32F103x6 -# STM32F103xB || STM32F103xE || STM32F103xG -# STM32F105xC || STM32F107xC) -# You can select chips from the list above -CPPDEFINES = ['STM32F103xB'] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) -Return('group') diff --git a/bsp/stm32/stm32f103-mini-system/board/board.c b/bsp/stm32/stm32f103-mini-system/board/board.c deleted file mode 100644 index b7ca2b8461..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/board.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-08 obito0 first version - */ - -#include "board.h" - -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - { - Error_Handler(); - } -} diff --git a/bsp/stm32/stm32f103-mini-system/board/board.h b/bsp/stm32/stm32f103-mini-system/board/board.h deleted file mode 100644 index 7f0ae67d48..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/board.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-5 SummerGift first version - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include -#include -#include "drv_common.h" -#include "drv_gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) -#define STM32_FLASH_SIZE (64 * 1024) -#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) - -/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/ -#define STM32_SRAM_SIZE 20 -#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) - -#if defined(__CC_ARM) || defined(__CLANG_ARM) -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="CSTACK" -#define HEAP_BEGIN (__segment_end("CSTACK")) -#else -extern int __bss_end; -#define HEAP_BEGIN ((void *)&__bss_end) -#endif - -#define HEAP_END STM32_SRAM_END - -void SystemClock_Config(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __BOARD_H__ */ diff --git a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.icf b/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.icf deleted file mode 100644 index 72eeb0ba65..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.icf +++ /dev/null @@ -1,28 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x0400; -define symbol __ICFEDIT_size_heap__ = 0x0000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; diff --git a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.lds b/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.lds deleted file mode 100644 index 22e29d2ed7..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.lds +++ /dev/null @@ -1,156 +0,0 @@ -/* - * linker script for STM32F10x with GNU ld - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 64k /* 64KB flash */ - RAM (rw) : ORIGIN = 0x20000000, LENGTH = 20k /* 20K sram */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - - . = ALIGN(4); - - PROVIDE(__ctors_start__ = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(4); - - _etext = .; - } > ROM = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > ROM - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >RAM - - .stack : - { - . = ALIGN(4); - _sstack = .; - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >RAM - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > RAM - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.sct b/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.sct deleted file mode 100644 index 6930ff4b50..0000000000 --- a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00010000 { ; load region size_region - ER_IROM1 0x08000000 0x00010000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00005000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/stm32/stm32f103-mini-system/figures/board1.jpg b/bsp/stm32/stm32f103-mini-system/figures/board1.jpg deleted file mode 100644 index 47c7221cf7..0000000000 Binary files a/bsp/stm32/stm32f103-mini-system/figures/board1.jpg and /dev/null differ diff --git a/bsp/stm32/stm32f103-mini-system/figures/board2.jpg b/bsp/stm32/stm32f103-mini-system/figures/board2.jpg deleted file mode 100644 index f14ba5689b..0000000000 Binary files a/bsp/stm32/stm32f103-mini-system/figures/board2.jpg and /dev/null differ diff --git a/bsp/stm32/stm32f103-mini-system/figures/board3.jpg b/bsp/stm32/stm32f103-mini-system/figures/board3.jpg deleted file mode 100644 index ac5bb43f74..0000000000 Binary files a/bsp/stm32/stm32f103-mini-system/figures/board3.jpg and /dev/null differ diff --git a/bsp/stm32/stm32f103-mini-system/project.ewd b/bsp/stm32/stm32f103-mini-system/project.ewd deleted file mode 100644 index 5c652a809d..0000000000 --- a/bsp/stm32/stm32f103-mini-system/project.ewd +++ /dev/null @@ -1,2834 +0,0 @@ - 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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- - 2.1 -
### uVision Project, (C) Keil Software
- - - rt-thread - 0x4 - ARM-ADS - - - STM32F103C8 - STMicroelectronics - Keil.STM32F1xx_DFP.1.0.5 - http://www.keil.com/pack/ - IROM(0x08000000,0x10000) IRAM(0x20000000,0x5000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)) - 0 - $$Device:STM32F103C8$Device\Include\stm32f10x.h - - - - - - - - - - $$Device:STM32F103C8$SVD\STM32F103xx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\Obj\ - rt-thread - 1 - 0 - 1 - 1 - 0 - .\build\keil\List\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 1 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x5000 - - - 1 - 0x8000000 - 0x10000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x10000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x5000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - - - STM32F103xB, USE_HAL_DRIVER, __RTTHREAD__ - - applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Include;..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Inc;..\libraries\STM32F1xx_HAL\CMSIS\Include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - .\board\linker_scripts\link.sct - - - - - - - - - - - Applications - - - main.c - 1 - applications\main.c - - - - - CPU - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - - - - div0.c - 1 - ..\..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\..\libcpu\arm\common\showmem.c - - - - - cpuport.c - 1 - ..\..\..\libcpu\arm\cortex-m3\cpuport.c - - - - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m3\context_rvds.S - - - - - DeviceDrivers - - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - - - completion.c - 1 - ..\..\..\components\drivers\src\completion.c - - - - - dataqueue.c - 1 - ..\..\..\components\drivers\src\dataqueue.c - - - - - pipe.c - 1 - ..\..\..\components\drivers\src\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\src\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\..\components\drivers\src\ringbuffer.c - - - - - waitqueue.c - 1 - ..\..\..\components\drivers\src\waitqueue.c - - - - - workqueue.c - 1 - ..\..\..\components\drivers\src\workqueue.c - - - - - Drivers - - - board.c - 1 - board\board.c - - - - - stm32f1xx_hal_msp.c - 1 - board\CubeMX_Config\Src\stm32f1xx_hal_msp.c - - - - - startup_stm32f103xb.s - 2 - ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xb.s - - - - - drv_gpio.c - 1 - ..\libraries\HAL_Drivers\drv_gpio.c - - - - - drv_usart.c - 1 - ..\libraries\HAL_Drivers\drv_usart.c - - - - - drv_common.c - 1 - ..\libraries\HAL_Drivers\drv_common.c - - - - - finsh - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - - - - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - - - components.c - 1 - ..\..\..\src\components.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - - - idle.c - 1 - ..\..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - - - object.c - 1 - ..\..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - - - signal.c - 1 - ..\..\..\src\signal.c - - - - - thread.c - 1 - ..\..\..\src\thread.c - - - - - timer.c - 1 - ..\..\..\src\timer.c - - - - - Libraries - - - system_stm32f1xx.c - 1 - ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c - - - - - stm32f1xx_hal_dma.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c - - - - - stm32f1xx_hal_cortex.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c - - - - - stm32f1xx_hal_crc.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_crc.c - - - - - stm32f1xx_hal_pwr.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c - - - - - stm32f1xx_hal_rcc.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c - - - - - stm32f1xx_hal_rcc_ex.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c - - - - - stm32f1xx_hal.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c - - - - - stm32f1xx_hal_cec.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cec.c - - - - - stm32f1xx_hal_gpio.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c - - - - - stm32f1xx_hal_gpio_ex.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c - - - - - stm32f1xx_hal_uart.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c - - - - - stm32f1xx_hal_usart.c - 1 - ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_usart.c - - - - - - - diff --git a/bsp/stm32/stm32f103-mini-system/rtconfig.h b/bsp/stm32/stm32f103-mini-system/rtconfig.h deleted file mode 100644 index ad9281a5d4..0000000000 --- a/bsp/stm32/stm32f103-mini-system/rtconfig.h +++ /dev/null @@ -1,178 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_DEBUG - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40001 -#define ARCH_ARM -#define ARCH_ARM_CORTEX_M -#define ARCH_ARM_CORTEX_M3 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 - -/* C++ features */ - - -/* Command shell */ - -#define RT_USING_FINSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_USING_MSH_ONLY -#define FINSH_ARG_MAX 10 - -/* Device virtual file system */ - - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_PIPE_BUFSZ 512 -#define RT_USING_SERIAL -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN - -/* Using WiFi */ - - -/* Using USB */ - - -/* POSIX layer and C standard library */ - - -/* Network */ - -/* Socket abstraction layer */ - - -/* light weight TCP/IP stack */ - - -/* Modbus master and slave stack */ - - -/* AT commands */ - - -/* VBUS(Virtual Software BUS) */ - - -/* Utilities */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - - -/* multimedia packages */ - - -/* tools packages */ - - -/* system packages */ - - -/* peripheral libraries and drivers */ - - -/* miscellaneous packages */ - - -/* sample package */ - -/* samples: kernel and components samples */ - - -/* example package: hello */ - -#define SOC_FAMILY_STM32 -#define SOC_SERIES_STM32F1 - -/* Hardware Drivers Config */ - -#define SOC_STM32F103C8 - -/* Onboard Peripheral Drivers */ - -#define BSP_USING_USB_TO_USART - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_GPIO -#define BSP_USING_UART -#define BSP_USING_UART1 -#define BSP_UART1_RX_USING_DMA - -/* Board extended module Drivers */ - - -#endif diff --git a/bsp/stm32/stm32f103-mini-system/rtconfig.py b/bsp/stm32/stm32f103-mini-system/rtconfig.py deleted file mode 100644 index b363b752f5..0000000000 --- a/bsp/stm32/stm32f103-mini-system/rtconfig.py +++ /dev/null @@ -1,151 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m3' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M3 ' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M3' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M3' - AFLAGS += ' --fpu None' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32f103-mini-system/template.ewp b/bsp/stm32/stm32f103-mini-system/template.ewp deleted file mode 100644 index 3280a547c0..0000000000 --- a/bsp/stm32/stm32f103-mini-system/template.ewp +++ /dev/null @@ -1,2032 +0,0 @@ - - - 3 - - rt-thread - - ARM - - 1 - - General - 3 - - 29 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 34 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 10 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 20 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 29 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 34 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 10 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 20 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - diff --git a/bsp/stm32/stm32f103-mini-system/template.eww b/bsp/stm32/stm32f103-mini-system/template.eww deleted file mode 100644 index bd036bb4c9..0000000000 --- a/bsp/stm32/stm32f103-mini-system/template.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\template.ewp - - - - - diff --git a/bsp/stm32/stm32f103-mini-system/template.uvopt b/bsp/stm32/stm32f103-mini-system/template.uvopt deleted file mode 100644 index 7946319ef9..0000000000 --- a/bsp/stm32/stm32f103-mini-system/template.uvopt +++ /dev/null @@ -1,162 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 8000000 - - 1 - 1 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\keil\List\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 0 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - 1 - 0 - 0 - 0 - 6 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U30000299 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 - - - 0 - UL2CM3 - UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - diff --git a/bsp/stm32/stm32f103-mini-system/template.uvoptx b/bsp/stm32/stm32f103-mini-system/template.uvoptx deleted file mode 100644 index 2a5ee7712d..0000000000 --- a/bsp/stm32/stm32f103-mini-system/template.uvoptx +++ /dev/null @@ -1,199 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\keil\List\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 18 - - - 0 - Base Board Schematics (MCBSTM32E) - I:\MDK5\MDK5\ARM\PACK\Keil\STM32F1xx_DFP\1.0.5\Documents\mcbstm32e-base-board-schematics.pdf - - - 1 - Display Board Schematics (MCBSTM32E) - I:\MDK5\MDK5\ARM\PACK\Keil\STM32F1xx_DFP\1.0.5\Documents\mcbstm32e-display-board-schematics.pdf - - - 2 - User Manual (MCBSTM32E) - I:\MDK5\MDK5\ARM\PACK\Keil\STM32F1xx_DFP\1.0.5\Documents\mcbstm32e.chm - - - 3 - MCBSTM32E Evaluation Board Web Page (MCBSTM32E) - http://www.keil.com/mcbstm32e/ - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - - - - - - - - - - - BIN\UL2CM3.DLL - - - - 0 - JL2CM3 - -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN0 - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F10x_128 -FL020000 -FS08000000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - 1 - 0 - 2 - 10000000 - - - - - - Source Group 1 - 0 - 0 - 0 - 0 - - - diff --git a/bsp/stm32/stm32f103-mini-system/template.uvproj b/bsp/stm32/stm32f103-mini-system/template.uvproj deleted file mode 100644 index 99e58d3b30..0000000000 --- a/bsp/stm32/stm32f103-mini-system/template.uvproj +++ /dev/null @@ -1,407 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread - 0x4 - ARM-ADS - - - STM32F103RB - STMicroelectronics - IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") - - "STARTUP\ST\STM32F10x\startup_stm32f10x_md.s" ("STM32 Medium Density Line Startup Code") - UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) - 4231 - stm32f10x.h - - - - - - - - - - SFD\ST\STM32F1xx\STM32F103xx.sfr - 0 - 0 - - - - ST\STM32F10x\ - ST\STM32F10x\ - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\Obj\ - rt-thread - 1 - 0 - 0 - 1 - 0 - .\build\keil\List\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - - DARMSTM.DLL - -pSTM32F103RB - SARMCM3.DLL - - TARMSTM.DLL - -pSTM32F103RB - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - 0 - - 0 - 6 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x5000 - - - 1 - 0x8000000 - 0x20000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x20000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x5000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - .\board\linker_scripts\link.sct - - - - - - - - - - - - diff --git a/bsp/stm32/stm32f103-mini-system/template.uvprojx b/bsp/stm32/stm32f103-mini-system/template.uvprojx deleted file mode 100644 index 3f668488e9..0000000000 --- a/bsp/stm32/stm32f103-mini-system/template.uvprojx +++ /dev/null @@ -1,415 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread - 0x4 - ARM-ADS - - - STM32F103C8 - STMicroelectronics - Keil.STM32F1xx_DFP.1.0.5 - http://www.keil.com/pack/ - IROM(0x08000000,0x10000) IRAM(0x20000000,0x5000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)) - 0 - $$Device:STM32F103C8$Device\Include\stm32f10x.h - - - - - - - - - - $$Device:STM32F103C8$SVD\STM32F103xx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\Obj\ - rt-thread - 1 - 0 - 1 - 1 - 0 - .\build\keil\List\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 1 - - - - - - - - - - - - - - BIN\UL2CM3.DLL - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x5000 - - - 1 - 0x8000000 - 0x10000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x10000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x5000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - .\board\linker_scripts\link.sct - - - - - - - - - - - Source Group 1 - - - - - - diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c index e1af109455..76272c8de2 100644 --- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c +++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-12-14 balanceTWK add sdcard port file + * 2021-02-26 Meco Man fix a bug that cannot use fatfs in the main thread at starting up */ #include @@ -46,16 +47,24 @@ int stm32_sdcard_mount(void) { rt_thread_t tid; - tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, - 1024, RT_THREAD_PRIORITY_MAX - 2, 20); - if (tid != RT_NULL) + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) { - rt_thread_startup(tid); + LOG_I("sd card mount to '/'"); } else { - LOG_E("create sd_mount thread err!"); + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } } + return RT_EOK; } INIT_APP_EXPORT(stm32_sdcard_mount); diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h index 3ba077b0b5..b7fd4ce81f 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h @@ -60,7 +60,7 @@ #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED /*#define HAL_MMC_MODULE_ENABLED */ -/*#define HAL_RTC_MODULE_ENABLED */ +#define HAL_RTC_MODULE_ENABLED /*#define HAL_SMBUS_MODULE_ENABLED */ /*#define HAL_SPDIFRX_MODULE_ENABLED */ #define HAL_SPI_MODULE_ENABLED diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c index 3a6fac25d7..5ca08fbbd0 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c @@ -1003,7 +1003,66 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) /* USER CODE END SDMMC1_MspInit 1 */ } + if(hsd->Instance==SDMMC2) + { + /* USER CODE BEGIN SDMMC2_MspInit 0 */ + if (IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC12; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + /* USER CODE END SDMMC2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDMMC2_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**SDMMC2 GPIO Configuration + PB14 ------> SDMMC2_D0 + PB15 ------> SDMMC2_D1 + PB3 ------> SDMMC2_D2 + PB4 ------> SDMMC2_D3 + PE3 ------> SDMMC2_CK + PG6 ------> SDMMC2_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_SDIO2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_SDIO2; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_SDIO2; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + __HAL_RCC_SDMMC2_FORCE_RESET(); + __HAL_RCC_SDMMC2_RELEASE_RESET(); + + /* SDMMC2 interrupt Init */ + HAL_NVIC_SetPriority(SDMMC2_IRQn, 2, 0); + HAL_NVIC_EnableIRQ(SDMMC2_IRQn); + /* USER CODE BEGIN SDMMC2_MspInit 1 */ + + /* USER CODE END SDMMC2_MspInit 1 */ + } } /** @@ -1312,6 +1371,65 @@ void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef* hcryp) } #endif + +/** +* @brief RTC MSP Initialization +* This function configures the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN SDMMC1_MspInit 0 */ + if (IS_ENGINEERING_BOOT_MODE()) + { + /** Initializes the peripherals clock + */ + PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } + } + /* USER CODE BEGIN RTC_MspInit 0 */ + + /* USER CODE END RTC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_RTC_ENABLE(); + + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } + +} + +/** +* @brief RTC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrtc: RTC handle pointer +* @retval None +*/ +void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +{ + if(hrtc->Instance==RTC) + { + /* USER CODE BEGIN RTC_MspDeInit 0 */ + + /* USER CODE END RTC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RTC_DISABLE(); + + /* USER CODE BEGIN RTC_MspDeInit 1 */ + + /* USER CODE END RTC_MspDeInit 1 */ + } + +} /** * @brief This function is executed in case of error occurrence. * @retval None diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig index 9191443847..36ba61a584 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig +++ b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig @@ -58,10 +58,23 @@ menu "Onboard Peripheral Drivers" select RT_USING_LWIP config BSP_USING_SDMMC - bool "Enable SDMMC (SD card)" + bool "Enable SDMMC (sd card or sdio wifi)" + default n select RT_USING_SDIO select RT_USING_DFS select RT_USING_DFS_ELMFAT + if BSP_USING_SDMMC + config BSP_USING_SDIO1 + bool "Enable SDIO1 (sd card)" + default n + config BSP_USING_SDIO2 + select BSP_USING_RTC + bool "Enable SDIO2 (sdio wifi)" + default n + endif + + config BSP_USING_RTC + bool "Enable RTC" default n menuconfig BSP_USING_AUDIO diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c index 3e5085c3cd..45de04328f 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c @@ -10,11 +10,17 @@ #include "board.h" #include "drv_sdio.h" + +#ifdef BSP_USING_SDIO1 #include +#endif #ifdef BSP_USING_SDMMC -//#define DRV_DEBUG +#ifdef BSP_USING_SDIO2 +#define DRV_DEBUG +#endif + #define DBG_TAG "drv.sdio" #ifdef DRV_DEBUG #define DBG_LVL DBG_LOG @@ -23,8 +29,9 @@ #endif /* DRV_DEBUG */ #include -static SD_HandleTypeDef hsd; -static struct rt_mmcsd_host *host; +static struct rt_mmcsd_host *host1; +static struct rt_mmcsd_host *host2; + #define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000) #define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER) @@ -47,13 +54,14 @@ struct rthw_sdio }; /* SYSRAM SDMMC1/2 accesses */ +#define SDCARD_ADDR 0x2FFC0000 #if defined(__CC_ARM) || defined(__CLANG_ARM) -rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((at(0x2FFC0000))); +__attribute__((at(SDCARD_ADDR))) static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; +#elif defined ( __GNUC__ ) +static rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((section(".SdCardSection"))); #elif defined(__ICCARM__) -#pragma location=0x2FFC0000 -rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; -#elif defined(__GNUC__) -rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((at(0x2FFC0000))); +#pragma location = SDCARD_ADDR +__no_init static rt_uint8_t cache_buf[SDIO_BUFF_SIZE]; #endif /** @@ -461,10 +469,20 @@ struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des) rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des)); - sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO_BASE_ADDRESS; + if(sdio_des->hsd.Instance == SDMMC1) + { + sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO1_BASE_ADDRESS; + rt_event_init(&sdio->event, "sdio1", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio1", RT_IPC_FLAG_FIFO); + } + + if(sdio_des->hsd.Instance == SDMMC2) + { + sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO2_BASE_ADDRESS; + rt_event_init(&sdio->event, "sdio2", RT_IPC_FLAG_FIFO); + rt_mutex_init(&sdio->mutex, "sdio2", RT_IPC_FLAG_FIFO); + } - rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO); - rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO); /* set host default attributes */ host->ops = &ops; host->freq_min = 400 * 1000; @@ -503,29 +521,83 @@ void SDMMC1_IRQHandler(void) { rt_interrupt_enter(); /* Process All SDIO Interrupt Sources */ - rthw_sdio_irq_process(host); + rthw_sdio_irq_process(host1); rt_interrupt_leave(); } +void SDMMC2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + /* Process All SDIO Interrupt Sources */ + rthw_sdio_irq_process(host2); + /* leave interrupt */ + rt_interrupt_leave(); +} + +#ifdef BSP_USING_SDIO2 +static RTC_HandleTypeDef hrtc; +static void MX_RTC_Init(void) +{ + hrtc.Instance = RTC; + hrtc.Init.HourFormat = RTC_HOURFORMAT_24; + hrtc.Init.AsynchPrediv = 127; + hrtc.Init.SynchPrediv = 255; + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + hrtc.Instance->CFGR = 0x02 << 1; + if (HAL_RTC_Init(&hrtc) != HAL_OK) + { + Error_Handler(); + } +} +static int LBEE5KL1DX_init(void) +{ +#define LBEE5KL1DX_WL_REG_ON GET_PIN(H, 4) + + /* enable the WLAN REG pin */ + rt_pin_mode(LBEE5KL1DX_WL_REG_ON, PIN_MODE_OUTPUT); + rt_pin_write(LBEE5KL1DX_WL_REG_ON, PIN_HIGH); + + return 0; +} +#endif + int rt_hw_sdio_init(void) { - struct stm32_sdio_des sdio_des; - - hsd.Instance = SDMMC1; - HAL_SD_MspInit(&hsd); +#ifdef BSP_USING_SDIO1 + struct stm32_sdio_des sdio_des1; + sdio_des1.hsd.Instance = SDMMC1; + HAL_SD_MspInit(&sdio_des1.hsd); - host = sdio_host_create(&sdio_des); - if (host == RT_NULL) + host1 = sdio_host_create(&sdio_des1); + if (host1 == RT_NULL) { LOG_E("host create fail"); return RT_NULL; } +#endif +#ifdef BSP_USING_SDIO2 + MX_RTC_Init(); + LBEE5KL1DX_init(); + + struct stm32_sdio_des sdio_des2; + sdio_des2.hsd.Instance = SDMMC2; + HAL_SD_MspInit(&sdio_des2.hsd); + + host2 = sdio_host_create(&sdio_des2); + if (host2 == RT_NULL) + { + LOG_E("host2 create fail"); + return RT_NULL; + } +#endif return RT_EOK; } INIT_DEVICE_EXPORT(rt_hw_sdio_init); +#ifdef BSP_USING_SDIO1 int mnt_init(void) { rt_device_t sd = RT_NULL; @@ -552,4 +624,6 @@ int mnt_init(void) } INIT_ENV_EXPORT(mnt_init); +#endif /* BSP_USING_SDIO1 */ + #endif /* BSP_USING_SDMMC */ diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h index a4428e4e71..da70bf1257 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h +++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h @@ -19,11 +19,12 @@ #include #include -#define SDIO_BUFF_SIZE 4096 -#define SDIO_ALIGN_LEN 32 +#ifndef SDIO1_BASE_ADDRESS +#define SDIO1_BASE_ADDRESS (SDMMC1) +#endif -#ifndef SDIO_BASE_ADDRESS -#define SDIO_BASE_ADDRESS (SDMMC1) +#ifndef SDIO2_BASE_ADDRESS +#define SDIO2_BASE_ADDRESS (SDMMC2) #endif #ifndef SDIO_CLOCK_FREQ @@ -39,7 +40,7 @@ #endif #ifndef SDIO_MAX_FREQ -#define SDIO_MAX_FREQ (50 * 1000 * 1000) +#define SDIO_MAX_FREQ (25 * 1000 * 1000) #endif #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) @@ -102,6 +103,7 @@ struct stm32_sdio_des { struct stm32_sdio *hw_sdio; sdio_clk_get clk_get; + SD_HandleTypeDef hsd; }; /* stm32 sdio dirver class */ diff --git a/bsp/stm32/stm32mp157a-st-discovery/project.ewp b/bsp/stm32/stm32mp157a-st-discovery/project.ewp index 3547891da5..3f12a28dbe 100644 --- a/bsp/stm32/stm32mp157a-st-discovery/project.ewp +++ b/bsp/stm32/stm32mp157a-st-discovery/project.ewp @@ -232,6 +232,8 @@ STM32MP157Axx __LOG_TRACE_IO_ __RTTHREAD__ + RT_USING_DLIBC + _DLIB_FILE_DESCRIPTOR USE_HAL_DRIVER + + Filesystem + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\poll.c + + + $PROJ_DIR$\..\..\..\components\dfs\src\select.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\devfs\devfs.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ff.c + + + $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ffunicode.c + + finsh @@ -2243,6 +2308,9 @@ $PROJ_DIR$\..\..\..\components\finsh\msh.c + + $PROJ_DIR$\..\..\..\components\finsh\msh_file.c + $PROJ_DIR$\..\..\..\components\finsh\finsh_compiler.c @@ -2309,9 +2377,6 @@ $PROJ_DIR$\..\..\..\src\scheduler.c - - $PROJ_DIR$\..\..\..\src\signal.c - $PROJ_DIR$\..\..\..\src\thread.c @@ -2319,6 +2384,54 @@ $PROJ_DIR$\..\..\..\src\timer.c + + libc + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\stdlib.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\unistd.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\libc.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\rmtx.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\stdio.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + + Libraries @@ -2393,5 +2506,20 @@ $PROJ_DIR$\..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_uart_ex.c + + $PROJ_DIR$\..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_ll_sdmmc.c + + + $PROJ_DIR$\..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_sd.c + + + $PROJ_DIR$\..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_ll_delayblock.c + + + $PROJ_DIR$\..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_rtc.c + + + $PROJ_DIR$\..\libraries\STM32MPxx_HAL\STM32MP1xx_HAL_Driver\Src\stm32mp1xx_hal_rtc_ex.c + diff --git a/components/drivers/i2c/i2c-bit-ops.c b/components/drivers/i2c/i2c-bit-ops.c index 96af567a1e..3a9b4efeb3 100644 --- a/components/drivers/i2c/i2c-bit-ops.c +++ b/components/drivers/i2c/i2c-bit-ops.c @@ -375,6 +375,8 @@ static rt_size_t i2c_bit_xfer(struct rt_i2c_bus_device *bus, rt_int32_t i, ret; rt_uint16_t ignore_nack; + if (num == 0) return 0; + for (i = 0; i < num; i++) { msg = &msgs[i]; diff --git a/components/libc/Kconfig b/components/libc/Kconfig index 65c8d44225..49b97481d1 100644 --- a/components/libc/Kconfig +++ b/components/libc/Kconfig @@ -54,9 +54,9 @@ if RT_USING_LIBC endif if RT_USING_LIBC != y - config RT_LIBC_USING_TIME - bool "Enable TIME FUNCTIONS WITHOUT COMPILER'S LIBC" - default y + config RT_LIBC_USING_TIME + bool "Enable TIME FUNCTIONS WITHOUT COMPILER'S LIBC" + default y endif endmenu diff --git a/components/libc/compilers/newlib/minilib.c b/components/libc/compilers/newlib/minilib.c index 2d07eabe5a..ca1bea0f91 100644 --- a/components/libc/compilers/newlib/minilib.c +++ b/components/libc/compilers/newlib/minilib.c @@ -11,8 +11,58 @@ #include #include -void * _sbrk_r(struct _reent *ptr, ptrdiff_t incr) +#ifdef RT_USING_HEAP /* Memory routine */ +void * +_malloc_r (struct _reent *ptr, size_t size) +{ + void* result; + + result = (void*)rt_malloc (size); + if (result == RT_NULL) + { + ptr->_errno = ENOMEM; + } + + return result; +} + +void * +_realloc_r (struct _reent *ptr, void *old, size_t newlen) +{ + void* result; + + result = (void*)rt_realloc (old, newlen); + if (result == RT_NULL) + { + ptr->_errno = ENOMEM; + } + + return result; +} + +void *_calloc_r (struct _reent *ptr, size_t size, size_t len) +{ + void* result; + + result = (void*)rt_calloc (size, len); + if (result == RT_NULL) + { + ptr->_errno = ENOMEM; + } + + return result; +} + +void +_free_r (struct _reent *ptr, void *addr) +{ + rt_free (addr); +} + +#else +void * +_sbrk_r(struct _reent *ptr, ptrdiff_t incr) { - /* no use this routine to get memory */ return RT_NULL; } +#endif /*RT_USING_HEAP*/ diff --git a/components/libc/compilers/newlib/syscalls.c b/components/libc/compilers/newlib/syscalls.c index 949d8a61de..e54d7583cb 100644 --- a/components/libc/compilers/newlib/syscalls.c +++ b/components/libc/compilers/newlib/syscalls.c @@ -189,13 +189,6 @@ _rename_r(struct _reent *ptr, const char *old, const char *new) #endif } -void * -_sbrk_r(struct _reent *ptr, ptrdiff_t incr) -{ - /* no use this routine to get memory */ - return RT_NULL; -} - int _stat_r(struct _reent *ptr, const char *file, struct stat *pstat) { @@ -258,7 +251,7 @@ _write_r(struct _reent *ptr, int fd, const void *buf, size_t nbytes) #endif } -/* Memory routine */ +#ifdef RT_USING_HEAP /* Memory routine */ void * _malloc_r (struct _reent *ptr, size_t size) { @@ -306,6 +299,14 @@ _free_r (struct _reent *ptr, void *addr) rt_free (addr); } +#else +void * +_sbrk_r(struct _reent *ptr, ptrdiff_t incr) +{ + return RT_NULL; +} +#endif /*RT_USING_HEAP*/ + /* for exit() and abort() */ __attribute__ ((noreturn)) void _exit (int status) diff --git a/components/libc/getline/README.md b/components/libc/getline/README.md index 0b279755d3..ef3c19deae 100644 --- a/components/libc/getline/README.md +++ b/components/libc/getline/README.md @@ -18,13 +18,3 @@ For more details, see [Open Group Base Specification for getdelim/getline][openg This code is unlicensed -- free and released into the public domain. See `UNLICENSE` file for more information. [opengroup-spec]: http://pubs.opengroup.org/onlinepubs/9699919799/functions/getline.html - - - - -## 联系&维护 -Meco Man - -jiantingman@foxmail.com - -https://github.com/mysterywolf/getline diff --git a/components/libc/getline/posix_getline.c b/components/libc/getline/posix_getline.c index e2ac278242..99bcf5363e 100644 --- a/components/libc/getline/posix_getline.c +++ b/components/libc/getline/posix_getline.c @@ -5,9 +5,8 @@ * https://man7.org/linux/man-pages/man3/getline.3.html * Authors: * https://github.com/ivanrad/getline - * https://github.com/mysterywolf/getline/ * - * Meco Man 2020-09-03 First Version + * Meco Man 2020-09-03 porting to RT-Thread */ #include "posix_getline.h" diff --git a/components/libc/getline/posix_getline.h b/components/libc/getline/posix_getline.h index c7d6021af3..e9e0bf9c2b 100644 --- a/components/libc/getline/posix_getline.h +++ b/components/libc/getline/posix_getline.h @@ -5,9 +5,8 @@ * https://man7.org/linux/man-pages/man3/getline.3.html * Authors: * https://github.com/ivanrad/getline - * https://github.com/mysterywolf/getline/ * - * Meco Man 2020-09-03 First Version + * Meco Man 2020-09-03 porting to RT-Thread */ diff --git a/src/thread.c b/src/thread.c index 18b5227f5a..beef93f46a 100644 --- a/src/thread.c +++ b/src/thread.c @@ -358,8 +358,6 @@ RTM_EXPORT(rt_thread_startup); */ rt_err_t rt_thread_detach(rt_thread_t thread) { - rt_base_t lock; - /* thread check */ RT_ASSERT(thread != RT_NULL); RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread); diff --git a/src/timer.c b/src/timer.c index 747c28c8bd..2eaca225bc 100644 --- a/src/timer.c +++ b/src/timer.c @@ -201,7 +201,7 @@ void rt_timer_init(rt_timer_t timer, RT_ASSERT(timer != RT_NULL); /* timer object initialization */ - rt_object_init((rt_object_t)timer, RT_Object_Class_Timer, name); + rt_object_init(&(timer->parent), RT_Object_Class_Timer, name); _rt_timer_init(timer, timeout, parameter, time, flag); } @@ -298,7 +298,7 @@ rt_err_t rt_timer_delete(rt_timer_t timer) /* enable interrupt */ rt_hw_interrupt_enable(level); - rt_object_delete((rt_object_t)timer); + rt_object_delete(&(timer->parent)); return RT_EOK; }