add sdram driver
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1754 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong
parent
c17931ad60
commit
f9a41a9686
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@ -2,7 +2,7 @@ import rtconfig
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Import('RTT_ROOT')
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from building import *
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src_bsp = ['application.c', 'startup.c', 'board.c']
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src_bsp = ['application.c', 'startup.c', 'sdram.c', 'board.c']
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src_drv = []
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if GetDepend('RT_USING_DFS'):
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@ -58,9 +58,16 @@ void rt_hw_timer_handler(void)
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void rt_hw_eth_handler(void)
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{
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#ifdef RT_USING_LWIP
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/* luminary ethernet interface */
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extern void luminaryif_isr(void);
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/* enter interrupt */
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rt_interrupt_enter();
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/* luminary ethernet interface */
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luminaryif_isr();
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/* leave interrupt */
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rt_interrupt_leave();
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#endif
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}
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@ -81,6 +88,10 @@ void rt_hw_board_init()
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/* enable ssio */
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//SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
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#if LM3S_EXT_SRAM == 1
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/* init SDRAM */
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rt_hw_sdram_init();
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#endif
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/* init console */
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rt_hw_console_init();
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@ -17,9 +17,21 @@
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#ifndef __BOARD_H__
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#define __BOARD_H__
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/* whether use board external SRAM memory */
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// <e>Use external SRAM memory on the board
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// <i>Enable External SRAM memory
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#define LM3S_EXT_SRAM 0
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// <o>Begin Address of External SRAM
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// <i>Default: 0x60000000
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#define LM3S_EXT_SRAM_BEGIN 0x60000000 /* the begining address of external SRAM */
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// <o>End Address of External SRAM
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// <i>Default: 0x60000000
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#define LM3S_EXT_SRAM_END 0x607FFFFF /* the end address of external SRAM */
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// </e>
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// <o> Internal SRAM memory size[Kbytes] <8-64>
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// <i>Default: 64
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#define LM3S_SRAM_SIZE 64
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#define LM3S_SRAM_SIZE 96
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#define LM3S_SRAM_END (0x20000000 + LM3S_SRAM_SIZE * 1024)
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// For lm3s8962, it should be SYSCTL_XTAL_8MHZ
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@ -13,6 +13,7 @@ Group (library)
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File 1,1,<.\application.c><application.c>
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File 1,1,<.\startup.c><startup.c>
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File 1,1,<.\board.c><board.c>
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File 1,1,<.\sdram.c><sdram.c>
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File 1,1,<.\luminaryif.c><luminaryif.c>
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File 2,1,<..\..\src\clock.c><clock.c>
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File 2,1,<..\..\src\device.c><device.c>
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@ -202,7 +203,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s'
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ADSLDIF ()
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ADSLDDW ()
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OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S9B96)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S9B96)
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OPTDBG 48118,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()()
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OPTDBG 49142,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
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FLASH1 { 1,0,0,0,1,0,0,0,1,16,0,0,0,0,0,0,0,0,0,0 }
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FLASH2 (BIN\lmidk-agdi.dll)
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FLASH3 ("" ())
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@ -113,9 +113,6 @@
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/* Ethernet padding size */
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#define RT_LWIP_ETH_PAD_SIZE 2
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/* TCP sender buffer space*/
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#define RT_LWIP_TCP_SND_BUF 1024*8
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/* Enable SNMP protocol*/
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#define RT_LWIP_SNMP
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@ -143,12 +140,19 @@
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#define RT_LWIP_MSKADDR3 0
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/* tcp thread options */
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#define RT_LWIP_TCPTHREAD_PRIORITY 22
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#define RT_LWIP_TCPTHREAD_PRIORITY 12
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#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
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#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
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/* ethernet if thread options */
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#define RT_LWIP_ETHTHREAD_PRIORITY 23
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#define RT_LWIP_ETHTHREAD_PRIORITY 15
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
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#define RT_LWIP_ETHTHREAD_STACKSIZE 512
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/* TCP sender buffer space */
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#define RT_LWIP_TCP_SND_BUF 8192
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/* TCP receive window. */
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#define RT_LWIP_TCP_WND 8192
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#endif
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@ -0,0 +1,256 @@
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//*****************************************************************************
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//
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// sdram.c - Example demonstrating how to configure the EPI bus in SDRAM
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// mode.
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//
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// Copyright (c) 2010 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 5961 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#include <rthw.h>
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#include <rtthread.h>
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#include <board.h>
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#include "inc/hw_memmap.h"
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#include "inc/hw_types.h"
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#include "inc/hw_epi.h"
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#include "inc/hw_gpio.h"
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#include "driverlib/epi.h"
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#include "driverlib/gpio.h"
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#include "driverlib/sysctl.h"
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//*****************************************************************************
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//
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//! \addtogroup epi_examples_list
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//! <h1>EPI SDRAM Mode (sdram)</h1>
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//!
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//! This example shows how to configure the EPI bus in SDRAM mode. This
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//! example has been written to be compatible with the Texas Instruments 8MB
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//! SDRAM expansion card for the DK-LM3S9B96.
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//!
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//! For the EPI SDRAM mode, the pinout is as follows:
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//! Address11:0 - EPI0S11:0
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//! Bank1:0 - EPI0S14:13
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//! Data15:0 - EPI0S15:0
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//! DQML - EPI0S16
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//! DQMH - EPI0S17
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//! /CAS - EPI0S18
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//! /RAS - EPI0S19
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//! /WE - EPI0S28
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//! /CS - EPI0S29
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//! SDCKE - EPI0S30
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//! SDCLK - EPI0S31
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//!
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//! This example uses the following peripherals and I/O signals. You must
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//! review these and change as needed for your own board:
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//! - EPI0 peripheral
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//! - GPIO Port C peripheral (for EPI0 pins)
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//! - GPIO Port E peripheral (for EPI0 pins)
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//! - GPIO Port F peripheral (for EPI0 pins)
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//! - GPIO Port G peripheral (for EPI0 pins)
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//! - GPIO Port H peripheral (for EPI0 pins)
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//! - GPIO Port J peripheral (for EPI0 pins)
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//! - EPI0S0 - PH3
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//! - EPI0S1 - PH2
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//! - EPI0S2 - PC4
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//! - EPI0S3 - PC5
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//! - EPI0S4 - PC6
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//! - EPI0S5 - PC7
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//! - EPI0S6 - PH0
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//! - EPI0S7 - PH1
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//! - EPI0S8 - PE0
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//! - EPI0S9 - PE1
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//! - EPI0S10 - PH4
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//! - EPI0S11 - PH5
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//! - EPI0S12 - PF4
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//! - EPI0S13 - PG0
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//! - EPI0S14 - PG1
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//! - EPI0S15 - PF5
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//! - EPI0S16 - PJ0
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//! - EPI0S17 - PJ1
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//! - EPI0S18 - PJ2
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//! - EPI0S19 - PJ3
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//! - EPI0S28 - PJ4
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//! - EPI0S29 - PJ5
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//! - EPI0S30 - PJ6
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//! - EPI0S31 - PG7
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//!
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//! The following UART signals are configured only for displaying console
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//! messages for this example. These are not required for operation of EPI0.
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//! - UART0 peripheral
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//! - GPIO Port A peripheral (for UART0 pins)
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//! - UART0RX - PA0
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//! - UART0TX - PA1
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//!
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//! This example uses the following interrupt handlers. To use this example
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//! in your own application you must add these interrupt handlers to your
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//! vector table.
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//! - None.
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//!
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Use the following to specify the GPIO pins used by the SDRAM EPI bus.
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//
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//*****************************************************************************
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#define EPI_PORTC_PINS (GPIO_PIN_7 | GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4)
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#define EPI_PORTE_PINS (GPIO_PIN_1 | GPIO_PIN_0)
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#define EPI_PORTF_PINS (GPIO_PIN_5 | GPIO_PIN_4)
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#define EPI_PORTG_PINS (GPIO_PIN_7 | GPIO_PIN_1 | GPIO_PIN_0)
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#define EPI_PORTH_PINS (GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2 | \
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GPIO_PIN_1 | GPIO_PIN_0)
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#define EPI_PORTJ_PINS (GPIO_PIN_6 | GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | \
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GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0)
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//*****************************************************************************
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//
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// The starting and ending address for the 8MB SDRAM chip (4Meg x 16bits) on
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// the SDRAM daughter board.
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//
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//*****************************************************************************
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#define SDRAM_START_ADDRESS 0x000000
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#define SDRAM_END_ADDRESS 0x3FFFFF
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//*****************************************************************************
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//
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//*****************************************************************************
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//
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// Configure EPI0 in SDRAM mode. The EPI memory space is setup using an a
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// simple C array. This example shows how to read and write to an SDRAM card
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// using the EPI bus in SDRAM mode.
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//
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//*****************************************************************************
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void rt_hw_sdram_init(void)
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{
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//
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// The EPI0 peripheral must be enabled for use.
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//
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SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
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//
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// For this example EPI0 is used with multiple pins on PortC, E, F, G, H,
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// and J. The actual port and pins used may be different on your part,
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// consult the data sheet for more information.
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// TODO: change this to whichever GPIO port you are using.
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//
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
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//
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// This step configures the internal pin muxes to set the EPI pins for use
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// with EPI. This step is only required because the default function of
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// these pins may not be to function in EPI mode. Please reference the
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// datasheet for more information about pin muxing. Note that EPI0S27:20
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// are not used for the EPI SDRAM implementation.
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// TODO: change this to select the port/pin you are using.
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//
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GPIOPinConfigure(GPIO_PH3_EPI0S0);
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GPIOPinConfigure(GPIO_PH2_EPI0S1);
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GPIOPinConfigure(GPIO_PC4_EPI0S2);
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GPIOPinConfigure(GPIO_PC5_EPI0S3);
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GPIOPinConfigure(GPIO_PC6_EPI0S4);
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GPIOPinConfigure(GPIO_PC7_EPI0S5);
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GPIOPinConfigure(GPIO_PH0_EPI0S6);
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GPIOPinConfigure(GPIO_PH1_EPI0S7);
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GPIOPinConfigure(GPIO_PE0_EPI0S8);
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GPIOPinConfigure(GPIO_PE1_EPI0S9);
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GPIOPinConfigure(GPIO_PH4_EPI0S10);
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GPIOPinConfigure(GPIO_PH5_EPI0S11);
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GPIOPinConfigure(GPIO_PF4_EPI0S12);
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GPIOPinConfigure(GPIO_PG0_EPI0S13);
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GPIOPinConfigure(GPIO_PG1_EPI0S14);
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GPIOPinConfigure(GPIO_PF5_EPI0S15);
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GPIOPinConfigure(GPIO_PJ0_EPI0S16);
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GPIOPinConfigure(GPIO_PJ1_EPI0S17);
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GPIOPinConfigure(GPIO_PJ2_EPI0S18);
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GPIOPinConfigure(GPIO_PJ3_EPI0S19);
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GPIOPinConfigure(GPIO_PJ4_EPI0S28);
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GPIOPinConfigure(GPIO_PJ5_EPI0S29);
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GPIOPinConfigure(GPIO_PJ6_EPI0S30);
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GPIOPinConfigure(GPIO_PG7_EPI0S31);
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//
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// Configure the GPIO pins for EPI mode. All the EPI pins require 8mA
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// drive strength in push-pull operation. This step also gives control of
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// pins to the EPI module.
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// TODO: change this to select the port/pin you are using.
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//
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GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
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GPIOPinTypeEPI(GPIO_PORTE_BASE, EPI_PORTE_PINS);
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GPIOPinTypeEPI(GPIO_PORTF_BASE, EPI_PORTF_PINS);
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GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
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GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);
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GPIOPinTypeEPI(GPIO_PORTJ_BASE, EPI_PORTJ_PINS);
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//
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// Sets the clock divider for the EPI module. In this case set the
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// divider to 0, making the EPIClock = SysClk.
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//
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EPIDividerSet(EPI0_BASE, 1);
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//
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// Sets the usage mode of the EPI module. For this example we will use
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// the SDRAM mode to talk to the external 8MB SDRAM daughter card.
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//
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EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);
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//
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// Configure the SDRAM mode. We configure the SDRAM according to our core
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// clock frequency, in this case we are in the 15 MHz < clk <= 30 MHz
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// range (i.e 16Mhz crystal). We will use the normal (or full power)
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// operating state which means we will not use the low power self-refresh
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// state. Set the SDRAM size to 8MB (or 64Mb) with a refresh counter of
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// 1024 clock ticks.
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// TODO: change this to select the proper clock frequency and SDRAM
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// refresh counter.
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//
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EPIConfigSDRAMSet(EPI0_BASE, EPI_SDRAM_CORE_FREQ_15_30 |
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EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT, 1024);
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//
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// Set the address map. The EPI0 is mapped from 0x60000000 to 0xCFFFFFFF.
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// For this example, we will start from a base address of 0x60000000 with
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// a size of 16MB. We use 16MB so we have the ability to access the
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// entire 8MB SDRAM daughter card. Since there is no 8MB option, so we
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// use the next closest one. If you attempt to access an address higher
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// than 4Meg (since SDRAM mode uses 16-bit data, you have 4Meg of
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// of addresses by 16-bits of data) a fault will not occur since we
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// configured the EPI for 16MB addressability. In the case that you do
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// access an address higher than 0x3FFFFF, the MSb of the address gets
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// ignored.
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//
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EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6);
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//
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// Wait for the SDRAM wake-up to complete by polling the SDRAM
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// initialization sequence bit. This bit is true when the SDRAM interface
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// is going through the initialization and false when the SDRAM interface
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// it is not in a wake-up period.
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//
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while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
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{
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}
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}
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@ -56,7 +56,7 @@ extern int __bss_end;
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* Output : None
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* Return : None
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*******************************************************************************/
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void assert_failed(u8* file, u32 line)
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void __error__(char* file, unsigned long line)
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{
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rt_kprintf("\n\r Wrong parameter value detected on\r\n");
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rt_kprintf(" file %s\r\n", file);
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@ -87,6 +87,10 @@ void rtthread_startup(void)
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rt_system_timer_init();
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#ifdef RT_USING_HEAP
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#if LM3S_EXT_SRAM == 1
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/* init sdram */
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rt_system_heap_init((void*)LM3S_EXT_SRAM_BEGIN, (void*)LM3S_EXT_SRAM_END);
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#else
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#ifdef __CC_ARM
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rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)LM3S_SRAM_END);
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#elif __ICCARM__
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@ -95,6 +99,7 @@ void rtthread_startup(void)
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/* init memory system */
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rt_system_heap_init((void*)&__bss_end, (void*)LM3S_SRAM_END);
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#endif
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#endif
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#endif
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/* init scheduler system */
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@ -139,10 +144,9 @@ void rtthread_startup(void)
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int main(void)
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{
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rt_uint32_t level UNUSED;
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/* disable interrupt first */
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level = rt_hw_interrupt_disable();
|
||||
rt_hw_interrupt_disable();
|
||||
|
||||
rtthread_startup();
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ Options 1,0,0 // Target 'RT-Thread-lm3s'
|
|||
OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
|
||||
OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,128,1,0,0,0,0,0,0,0,0,0,0 }
|
||||
RV_STAVEC ()
|
||||
ADSCCFLG { 9,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
ADSCCFLG { 13,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
ADSCMISC ()
|
||||
ADSCDEFN ()
|
||||
ADSCUDEF ()
|
||||
|
|
|
|||
Loading…
Reference in New Issue