From f7111cd965a397ac85d51090451829eee2134ff5 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 31 Oct 2017 14:45:49 +0800 Subject: [PATCH] =?UTF-8?q?iar=20=E7=B1=BB=E5=9E=8B=E6=A3=80=E6=9F=A5?= =?UTF-8?q?=E4=B8=A5=E6=A0=BC=20=E4=BF=AE=E6=94=B9=E5=87=BD=E6=95=B0?= =?UTF-8?q?=E5=AE=9A=E4=B9=89=E7=B1=BB=E5=9E=8B=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32f429-apollo/drivers/drv_mpu.c | 6 ++++-- bsp/stm32f429-apollo/drivers/drv_mpu.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/bsp/stm32f429-apollo/drivers/drv_mpu.c b/bsp/stm32f429-apollo/drivers/drv_mpu.c index c7f7037b68..148a9526e6 100644 --- a/bsp/stm32f429-apollo/drivers/drv_mpu.c +++ b/bsp/stm32f429-apollo/drivers/drv_mpu.c @@ -20,7 +20,7 @@ -void mpu_init(void) +int mpu_init(void) { /* Disable MPU */ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; @@ -32,7 +32,7 @@ void mpu_init(void) MPU->RNR = 0;//indicate MPU region 0 MPU->RBAR = 0x00000000; // update the base address for the region 0 MPU->RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS) //full access - | MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_1MB) //512Kb size + | MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_1MB) //512Kb size | MPU_REGION_ENABLE; //region enable /* - Region 1:0x20000000 - 0x20007FFF --- on chip SRAM @@ -92,5 +92,7 @@ void mpu_init(void) /* Enable MPU */ MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk; + + return 0; } INIT_BOARD_EXPORT(mpu_init); diff --git a/bsp/stm32f429-apollo/drivers/drv_mpu.h b/bsp/stm32f429-apollo/drivers/drv_mpu.h index 80c3ad6313..f4fbc032bc 100644 --- a/bsp/stm32f429-apollo/drivers/drv_mpu.h +++ b/bsp/stm32f429-apollo/drivers/drv_mpu.h @@ -2,7 +2,7 @@ #define __DRV_MPU_H /* Initialize Cortex M4 MPU */ -void mpu_init(void); +int mpu_init(void); void mpu_enable(int enable); #endif