From 96ba787e252c38abe08f039c052a4be378dfa42c Mon Sep 17 00:00:00 2001 From: Fan Yang <93824713+helloeagleyang@users.noreply.github.com> Date: Mon, 15 Jul 2024 17:51:32 +0800 Subject: [PATCH 01/14] Bugfix/fix weak handle trap in riscv common crash rv64 trap handling (#9189) * [bsp][hpmicro] add weak handle_trap implementation - added weak handle_trap implementation Signed-off-by: Fan YANG * [libcpu][risc-v][common] remove weak handle_trap function - removed weak handle_trap function from trap_common.c Signed-off-by: Fan YANG --------- Signed-off-by: Fan YANG --- bsp/hpmicro/hpm5300evk/startup/HPM5361/trap.c | 7 +++++++ bsp/hpmicro/hpm5301evklite/startup/HPM5301/trap.c | 7 +++++++ bsp/hpmicro/hpm6200evk/startup/HPM6280/trap.c | 7 +++++++ bsp/hpmicro/hpm6300evk/startup/HPM6360/trap.c | 7 +++++++ bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c | 7 +++++++ bsp/hpmicro/hpm6750evk2/startup/HPM6750/trap.c | 7 +++++++ bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c | 7 +++++++ bsp/hpmicro/hpm6800evk/startup/HPM6880/trap.c | 7 +++++++ libcpu/risc-v/common/trap_common.c | 7 ------- 9 files changed, 56 insertions(+), 7 deletions(-) diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/trap.c b/bsp/hpmicro/hpm5300evk/startup/HPM5361/trap.c index b87eaee524..d041d4785a 100644 --- a/bsp/hpmicro/hpm5300evk/startup/HPM5361/trap.c +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/trap.c @@ -302,3 +302,10 @@ void trap_entry(void) write_fcsr(fcsr); #endif } + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/trap.c b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/trap.c index b87eaee524..d9c7ce6d47 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/trap.c +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/trap.c @@ -302,3 +302,10 @@ void trap_entry(void) write_fcsr(fcsr); #endif } + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/startup/HPM6280/trap.c b/bsp/hpmicro/hpm6200evk/startup/HPM6280/trap.c index b87eaee524..d9c7ce6d47 100644 --- a/bsp/hpmicro/hpm6200evk/startup/HPM6280/trap.c +++ b/bsp/hpmicro/hpm6200evk/startup/HPM6280/trap.c @@ -302,3 +302,10 @@ void trap_entry(void) write_fcsr(fcsr); #endif } + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6300evk/startup/HPM6360/trap.c b/bsp/hpmicro/hpm6300evk/startup/HPM6360/trap.c index b87eaee524..d9c7ce6d47 100644 --- a/bsp/hpmicro/hpm6300evk/startup/HPM6360/trap.c +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/trap.c @@ -302,3 +302,10 @@ void trap_entry(void) write_fcsr(fcsr); #endif } + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c b/bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c index b87eaee524..d9c7ce6d47 100644 --- a/bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c @@ -302,3 +302,10 @@ void trap_entry(void) write_fcsr(fcsr); #endif } + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/trap.c b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/trap.c index b87eaee524..d9c7ce6d47 100644 --- a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/trap.c +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/trap.c @@ -302,3 +302,10 @@ void trap_entry(void) write_fcsr(fcsr); #endif } + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c index b87eaee524..d9c7ce6d47 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c @@ -302,3 +302,10 @@ void trap_entry(void) write_fcsr(fcsr); #endif } + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/trap.c b/bsp/hpmicro/hpm6800evk/startup/HPM6880/trap.c index b87eaee524..d9c7ce6d47 100644 --- a/bsp/hpmicro/hpm6800evk/startup/HPM6880/trap.c +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/trap.c @@ -302,3 +302,10 @@ void trap_entry(void) write_fcsr(fcsr); #endif } + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/libcpu/risc-v/common/trap_common.c b/libcpu/risc-v/common/trap_common.c index 3cbbfeb008..6f7352cd56 100644 --- a/libcpu/risc-v/common/trap_common.c +++ b/libcpu/risc-v/common/trap_common.c @@ -109,10 +109,3 @@ rt_weak void rt_show_stack_frame(void) rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); #endif } - -/** - * Trap Handler - */ -rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) -{ -} \ No newline at end of file From 14fb55933b173811467159df3e80e314b2e4415c Mon Sep 17 00:00:00 2001 From: rcitachi Date: Mon, 15 Jul 2024 17:58:29 +0800 Subject: [PATCH 02/14] [lwp][vdso] Add VDSO functionality under the aarch64 architecture (#9176) Add VDSO functionality under the aarch64 architecture --- .gitignore | 4 + components/lwp/Kconfig | 1 + components/lwp/SConscript | 10 +- components/lwp/arch/aarch64/common/vdso.c | 110 +++++++++++++ .../lwp/arch/aarch64/common/vdso_data.c | 34 ++++ components/lwp/lwp.h | 5 + components/lwp/lwp_elf.c | 15 ++ components/lwp/vdso/Kconfig | 5 + components/lwp/vdso/SConscript | 48 ++++++ components/lwp/vdso/kernel/vdso.h | 39 +++++ components/lwp/vdso/kernel/vdso_data.h | 48 ++++++ components/lwp/vdso/kernel/vdso_text.S | 21 +++ components/lwp/vdso/user/SConstruct | 39 +++++ components/lwp/vdso/user/vdso.lds.S | 60 +++++++ components/lwp/vdso/user/vdso_sys.c | 95 +++++++++++ components/lwp/vdso/user/vdso_sys.h | 153 ++++++++++++++++++ components/lwp/vdso/user/xmake.lua | 58 +++++++ components/lwp/vdso/vdso_config.h | 38 +++++ components/lwp/vdso/vdso_datapage.h | 75 +++++++++ components/lwp/vdso/vdso_weak.c | 23 +++ libcpu/aarch64/cortex-a/entry_point.S | 4 + src/clock.c | 8 + 22 files changed, 891 insertions(+), 2 deletions(-) create mode 100644 components/lwp/arch/aarch64/common/vdso.c create mode 100644 components/lwp/arch/aarch64/common/vdso_data.c create mode 100644 components/lwp/vdso/Kconfig create mode 100644 components/lwp/vdso/SConscript create mode 100644 components/lwp/vdso/kernel/vdso.h create mode 100644 components/lwp/vdso/kernel/vdso_data.h create mode 100644 components/lwp/vdso/kernel/vdso_text.S create mode 100644 components/lwp/vdso/user/SConstruct create mode 100644 components/lwp/vdso/user/vdso.lds.S create mode 100644 components/lwp/vdso/user/vdso_sys.c create mode 100644 components/lwp/vdso/user/vdso_sys.h create mode 100644 components/lwp/vdso/user/xmake.lua create mode 100644 components/lwp/vdso/vdso_config.h create mode 100644 components/lwp/vdso/vdso_datapage.h create mode 100644 components/lwp/vdso/vdso_weak.c diff --git a/.gitignore b/.gitignore index 9ddfece39e..cff9ff536b 100644 --- a/.gitignore +++ b/.gitignore @@ -50,3 +50,7 @@ tags CMakeLists.txt cmake-build-debug *.mk + +# vDSO +vdso_sys.os +vdso.lds diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig index 22cfbea47c..d88a0b6a9d 100644 --- a/components/lwp/Kconfig +++ b/components/lwp/Kconfig @@ -81,5 +81,6 @@ if RT_USING_LWP endif rsource "terminal/Kconfig" +rsource "vdso/Kconfig" endif diff --git a/components/lwp/SConscript b/components/lwp/SConscript index 5f4a618d48..be7b4f7b64 100644 --- a/components/lwp/SConscript +++ b/components/lwp/SConscript @@ -26,11 +26,16 @@ if platform in platform_file.keys(): # support platforms if arch in support_arch.keys() and cpu in support_arch[arch]: asm_path = 'arch/' + arch + '/' + cpu + '/*_' + platform_file[platform] arch_common = 'arch/' + arch + '/' + 'common/*.c' + if not GetDepend('RT_USING_VDSO'): + vdso_files = ['vdso_data.c', 'vdso.c'] + src += [f for f in Glob(arch_common) if os.path.basename(str(f)) not in vdso_files] + else: + src += Glob(arch_common) if not GetDepend('ARCH_MM_MMU'): excluded_files = ['ioremap.c', 'lwp_futex.c', 'lwp_mm_area.c', 'lwp_pmutex.c', 'lwp_shm.c', 'lwp_user_mm.c'] - src += [f for f in Glob('*.c') if os.path.basename(str(f)) not in excluded_files] + Glob(asm_path) + Glob(arch_common) + src += [f for f in Glob('*.c') if os.path.basename(str(f)) not in excluded_files] + Glob(asm_path) else: - src += Glob('*.c') + Glob(asm_path) + Glob(arch_common) + src += Glob('*.c') + Glob(asm_path) src += Glob('arch/' + arch + '/' + cpu + '/*.c') CPPPATH = [cwd] CPPPATH += [cwd + '/arch/' + arch + '/' + cpu] @@ -43,4 +48,5 @@ CPPPATH += ['./terminal/'] group = DefineGroup('lwP', src, depend = ['RT_USING_SMART'], CPPPATH = CPPPATH) +group = group + SConscript(os.path.join('vdso', 'SConscript')) Return('group') diff --git a/components/lwp/arch/aarch64/common/vdso.c b/components/lwp/arch/aarch64/common/vdso.c new file mode 100644 index 0000000000..41b0a6d8f0 --- /dev/null +++ b/components/lwp/arch/aarch64/common/vdso.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#include +#include +#include +#include + +#include "vdso.h" +#include "vdso_datapage.h" +#define DBG_TAG "vdso" +#define DBG_LVL DBG_INFO +#include + +enum vdso_abi { + VDSO_ABI_AA64, +}; +enum vvar_pages { + VVAR_DATA_PAGE_OFFSET, + VVAR_TIMENS_PAGE_OFFSET, + VVAR_NR_PAGES, +}; +struct vdso_abi_info { + const char *name; + const char *vdso_code_start; + const char *vdso_code_end; + unsigned long vdso_pages; + +}; + +static struct vdso_abi_info vdso_info[] = { + [VDSO_ABI_AA64] = { + .name = "vdso_aarch64", + .vdso_code_start = __vdso_text_start, + .vdso_code_end = __vdso_text_end, + }, +}; + +static union { + struct vdso_data data[CS_BASES]; + uint8_t page[ARCH_PAGE_SIZE]; +} vdso_data_store __page_aligned_data; +struct vdso_data *vdso_data = vdso_data_store.data; +int init_ret_flag = RT_EOK; + +static int __setup_additional_pages(enum vdso_abi abi, struct rt_lwp *lwp) +{ + RT_ASSERT(lwp != RT_NULL); + + int ret; + void *vdso_base = RT_NULL; + unsigned long vdso_data_len, vdso_text_len; + + vdso_data_len = VVAR_NR_PAGES * ARCH_PAGE_SIZE; + vdso_text_len = vdso_info[abi].vdso_pages << ARCH_PAGE_SHIFT; + + vdso_base = lwp_map_user_phy(lwp, RT_NULL, rt_kmem_v2p((void *)vdso_data), vdso_data_len, 0); + if(vdso_base != RT_NULL) + { + ret = RT_EOK; + } + else + { + ret = RT_ERROR; + } + vdso_base += vdso_data_len; + vdso_base = lwp_map_user_phy(lwp, vdso_base, rt_kmem_v2p((void *)vdso_info[abi].vdso_code_start), vdso_text_len, 0); + + lwp->vdso_vbase = vdso_base; + return ret; +} + +int arch_setup_additional_pages(struct rt_lwp *lwp) +{ + int ret; + if (init_ret_flag != RT_EOK) return -RT_ERROR; + ret = __setup_additional_pages(VDSO_ABI_AA64, lwp); + + return ret; +} + +static void __initdata(void) +{ + struct tm time_vdso = SOFT_RTC_VDSOTIME_DEFAULT; + vdso_data->realtime_initdata = timegm(&time_vdso); +} + +static int validate_vdso_elf(void) +{ + if (rt_memcmp(vdso_info[VDSO_ABI_AA64].vdso_code_start, ELF_HEAD, ELF_HEAD_LEN)) { + LOG_E("vDSO is not a valid ELF object!"); + init_ret_flag = -RT_ERROR; + return -RT_ERROR; + } + vdso_info[VDSO_ABI_AA64].vdso_pages = ( + vdso_info[VDSO_ABI_AA64].vdso_code_end - + vdso_info[VDSO_ABI_AA64].vdso_code_start) >> + ARCH_PAGE_SHIFT; + + __initdata(); + return RT_EOK; +} +INIT_COMPONENT_EXPORT(validate_vdso_elf); diff --git a/components/lwp/arch/aarch64/common/vdso_data.c b/components/lwp/arch/aarch64/common/vdso_data.c new file mode 100644 index 0000000000..13c055ec56 --- /dev/null +++ b/components/lwp/arch/aarch64/common/vdso_data.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#include +#include +#include +#include +#include +#include + +void rt_vdso_update_glob_time(void) +{ + struct vdso_data *vdata = get_k_vdso_data(); + struct timespec *vdso_ts; + uint64_t initdata = vdata->realtime_initdata; + rt_vdso_write_begin(vdata); + + vdso_ts = &vdata[CS_HRES_COARSE].basetime[CLOCK_REALTIME]; + rt_ktime_boottime_get_ns(vdso_ts); + vdso_ts->tv_sec = initdata + vdso_ts->tv_sec; + + vdso_ts = &vdata[CS_HRES_COARSE].basetime[CLOCK_MONOTONIC]; + rt_ktime_boottime_get_ns(vdso_ts); + + vdata->cycle_last = rt_hw_get_cntpct_val(); + rt_vdso_write_end(vdata); +} diff --git a/components/lwp/lwp.h b/components/lwp/lwp.h index e2cf2e8bd7..24b4150270 100644 --- a/components/lwp/lwp.h +++ b/components/lwp/lwp.h @@ -197,6 +197,10 @@ struct rt_lwp unsigned int asid; #endif struct rusage rt_rusage; + +#ifdef RT_USING_VDSO + void *vdso_vbase; +#endif }; @@ -373,6 +377,7 @@ void lwp_jobctrl_on_exit(struct rt_lwp *lwp); #define AT_RANDOM 25 #define AT_HWCAP2 26 #define AT_EXECFN 31 +#define AT_SYSINFO_EHDR 33 struct process_aux_item { diff --git a/components/lwp/lwp_elf.c b/components/lwp/lwp_elf.c index da698e3674..69021a496d 100644 --- a/components/lwp/lwp_elf.c +++ b/components/lwp/lwp_elf.c @@ -25,6 +25,10 @@ #include #endif +#ifdef RT_USING_VDSO +#include +#endif + #define DBG_TAG "load.elf" #ifdef ELF_DEBUG_ENABLE #define DBG_LVL DBG_LOG @@ -607,6 +611,17 @@ static int elf_aux_fill(elf_load_info_t *load_info) ELF_AUX_ENT(aux_info, AT_CLKTCK, 0); ELF_AUX_ENT(aux_info, AT_SECURE, 0); +#ifdef RT_USING_VDSO + if(RT_EOK == arch_setup_additional_pages(load_info->lwp)) + { + ELF_AUX_ENT(aux_info, AT_SYSINFO_EHDR, (size_t)load_info->lwp->vdso_vbase); + } + else + { + LOG_W("vdso map error,VDSO currently only supports aarch64 architecture!"); + } +#endif + return 0; } diff --git a/components/lwp/vdso/Kconfig b/components/lwp/vdso/Kconfig new file mode 100644 index 0000000000..a10e016271 --- /dev/null +++ b/components/lwp/vdso/Kconfig @@ -0,0 +1,5 @@ +menuconfig RT_USING_VDSO + bool "vDSO" + default y + depends on RT_USING_SMART + diff --git a/components/lwp/vdso/SConscript b/components/lwp/vdso/SConscript new file mode 100644 index 0000000000..addcdfc840 --- /dev/null +++ b/components/lwp/vdso/SConscript @@ -0,0 +1,48 @@ +import os +import rtconfig +import subprocess +from building import * +Import('RTT_ROOT') + +group = [] + +cwd = GetCurrentDir() +CPPPATH = [cwd, cwd + "/kernel"] + +if not GetDepend(['RT_USING_VDSO']): + Return('group') + +if rtconfig.ARCH != "aarch64": + src = Glob('*.c') + group = DefineGroup('VDSO', src, depend = ['RT_USING_SMART','RT_USING_VDSO'], CPPPATH = CPPPATH) + Return('group') + +list = os.listdir(cwd) +src = Glob('kernel/*.c') +src +=Glob('kernel/*.S') + +if not os.path.exists(cwd + "/user/vdso.lds"): + Preprocessing("user/vdso.lds.S", ".lds", CPPPATH=[cwd]) + +#aarch64 vdso xmake +# vdso_file = os.path.join(cwd, 'usr', 'xmake.lua') +# command = ["xmake", "-F", vdso_file] +# clean = ["xmake", "clean"] + +vdso_file = os.path.join(cwd, 'user', 'SConstruct') +command = ["scons", "-f", vdso_file] +clean = ["scons", "-f", vdso_file, "--clean"] + +if not GetOption('clean'): + result = subprocess.run(command) +else: + result = subprocess.run(clean) + +if result.returncode == 0: + print("Command executed successfully") +else: + print("Command failed with exit code:", result.returncode) + exit(1) + +group = DefineGroup('VDSO', src, depend = ['RT_USING_SMART','RT_USING_VDSO'], CPPPATH = CPPPATH) +Return('group') diff --git a/components/lwp/vdso/kernel/vdso.h b/components/lwp/vdso/kernel/vdso.h new file mode 100644 index 0000000000..1cb3b44e8c --- /dev/null +++ b/components/lwp/vdso/kernel/vdso.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#ifndef _VDSO_H +#define _VDSO_H + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern char __vdso_text_start[]; +extern char __vdso_text_end[]; + +#define ELF_HEAD "\177ELF" +#define ELF_HEAD_LEN 4 +#define MAX_PAGES 5 + +#define __page_aligned_data __attribute__((section(".data.vdso.datapage"))) __attribute__((aligned(VDSO_PAGE_SIZE))) + +int arch_setup_additional_pages(struct rt_lwp *lwp); +void rt_vdso_update_glob_time(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _VDSO_H */ diff --git a/components/lwp/vdso/kernel/vdso_data.h b/components/lwp/vdso/kernel/vdso_data.h new file mode 100644 index 0000000000..5d077e4a9e --- /dev/null +++ b/components/lwp/vdso/kernel/vdso_data.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#ifndef _VDSO_KDATA_H +#define _VDSO_KDATA_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern struct vdso_data *vdso_data; + +rt_inline +struct vdso_data *_get_k_vdso_data(void) +{ + return vdso_data; +} +#define get_k_vdso_data _get_k_vdso_data + +rt_inline +void rt_vdso_write_begin(struct vdso_data *vd) +{ + rt_atomic_add(&vd[CS_HRES_COARSE].seq, 1); + rt_atomic_add(&vd[CS_RAW].seq, 1); +} + +rt_inline +void rt_vdso_write_end(struct vdso_data *vd) +{ + rt_atomic_add(&vd[CS_HRES_COARSE].seq, 1); + rt_atomic_add(&vd[CS_RAW].seq, 1); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _VDSO_KDATA_H */ diff --git a/components/lwp/vdso/kernel/vdso_text.S b/components/lwp/vdso/kernel/vdso_text.S new file mode 100644 index 0000000000..f9c1f8aa72 --- /dev/null +++ b/components/lwp/vdso/kernel/vdso_text.S @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#include + + .globl __vdso_text_start, __vdso_text_end + .section .rodata + .balign VDSO_PAGE_SIZE +__vdso_text_start: + .incbin VDSO_PATH + .balign VDSO_PAGE_SIZE +__vdso_text_end: + + .previous diff --git a/components/lwp/vdso/user/SConstruct b/components/lwp/vdso/user/SConstruct new file mode 100644 index 0000000000..a7cee1127f --- /dev/null +++ b/components/lwp/vdso/user/SConstruct @@ -0,0 +1,39 @@ +import os +import sys +import subprocess + +arguments = sys.argv[2] +vdso_usr = os.path.dirname(arguments) +vdso_root = os.path.dirname(vdso_usr) + + +EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin' +PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-' + +CC = PREFIX + 'gcc' +CXX = PREFIX + 'g++' +CPP = PREFIX + 'cpp' +AS = PREFIX + 'gcc' +AR = PREFIX + 'ar' +LINK = PREFIX + 'gcc' + +DEVICE = ' -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' +CXXFLAGS = DEVICE + ' -Wall -fdiagnostics-color=always' +AFLAGS = ' -x assembler-with-cpp' +CFLAGS = DEVICE + ' -Wall -Wno-cpp -std=gnu99 -fdiagnostics-color=always -fPIC -O2' +LFLAGS = DEVICE + ' -Bsymbolic -Wl,--gc-sections,-u,system_vectors -T {path}/vdso.lds'.format(path=vdso_usr) +CFLAGS += " -I {path} -I{path}/user".format(path=vdso_root) + +env = Environment(tools=['gcc', 'link'], + AS = AS, ASFLAGS = AFLAGS, + CC = CC, CFLAGS = CFLAGS, + CXX = CXX, CXXFLAGS = CXXFLAGS, + AR = AR, + LINK = LINK, LINKFLAGS = LFLAGS) +env.PrependENVPath('PATH', EXEC_PATH) + +src = os.path.join(vdso_usr,'vdso_sys.c') +target_name = 'librtos_vdso.so' +target = os.path.join(vdso_usr, "build", target_name) +shared_lib = env.SharedLibrary(target=target, source=src) +env.Default(shared_lib) diff --git a/components/lwp/vdso/user/vdso.lds.S b/components/lwp/vdso/user/vdso.lds.S new file mode 100644 index 0000000000..8b0038ee2d --- /dev/null +++ b/components/lwp/vdso/user/vdso.lds.S @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#include + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) + +SECTIONS +{ + PROVIDE(_vdso_data = . - __VVAR_PAGES * VDSO_PAGE_SIZE); + . = SIZEOF_HEADERS; + + .hash : { *(.hash) } :text + .gnu.hash : { *(.gnu.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + + .dynamic : { *(.dynamic) } :text :dynamic + .rela.dyn : ALIGN(8) { *(.rela .rela*) } + + .rodata : { + *(.rodata*) + *(.got) + *(.got.plt) + *(.plt) + *(.plt.*) + *(.iplt) + *(.igot .igot.plt) + } :text + /DISCARD/ : { + *(.data .data.* .sdata*) + *(.bss .sbss .dynbss .dynsbss) + } +} + +PHDRS +{ + text PT_LOAD FLAGS(5) FILEHDR PHDRS; + dynamic PT_DYNAMIC FLAGS(4); +} + +VERSION +{ + LINUX_2.6.39 { + global: + __kernel_clock_gettime; + local: *; + }; +} diff --git a/components/lwp/vdso/user/vdso_sys.c b/components/lwp/vdso/user/vdso_sys.c new file mode 100644 index 0000000000..61da379f04 --- /dev/null +++ b/components/lwp/vdso/user/vdso_sys.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#include +#include +#include +#include +#include + +#ifndef rt_vdso_cycles_ready +static inline bool rt_vdso_cycles_ready(uint64_t cycles) +{ + return true; +} +#endif + +#ifndef rt_vdso_get_ns +static inline +uint64_t rt_vdso_get_ns(uint64_t cycles, uint64_t last) +{ + return (cycles - last) * NSEC_PER_SEC / __arch_get_hw_frq(); +} +#endif + +static int +__rt_vdso_getcoarse(struct timespec *ts, clockid_t clock, const struct vdso_data *vdns) +{ + const struct vdso_data *vd; + const struct timespec *vdso_ts; + uint32_t seq; + uint64_t sec, last, ns, cycles; + + if (clock != CLOCK_MONOTONIC_RAW) + vd = &vdns[CS_HRES_COARSE]; + else + vd = &vdns[CS_RAW]; + + vdso_ts = &vd->basetime[clock]; + + do { + seq = rt_vdso_read_begin(vd); + cycles = __arch_get_hw_counter(vd->clock_mode, vd); + if (unlikely(!rt_vdso_cycles_ready(cycles))) + return -1; + ns = vdso_ts->tv_nsec; + last = vd->cycle_last; + ns += rt_vdso_get_ns(cycles, last); + sec = vdso_ts->tv_sec; + } while (unlikely(rt_vdso_read_retry(vd, seq))); + + ts->tv_sec = sec + __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); + ts->tv_nsec = ns; + + return 0; +} + +static inline int +__vdso_clock_gettime_common(const struct vdso_data *vd, clockid_t clock, + struct timespec *ts) +{ + u_int32_t msk; + + if (unlikely((u_int32_t) clock >= MAX_CLOCKS)) + return -1; + + msk = 1U << clock; + if (likely(msk & VDSO_REALTIME)) + return __rt_vdso_getcoarse(ts,CLOCK_REALTIME,vd); + else if (msk & VDSO_MONOTIME) + return __rt_vdso_getcoarse(ts,CLOCK_MONOTONIC,vd); + else + return ENOENT; +} + +static __maybe_unused int +rt_vdso_clock_gettime_data(const struct vdso_data *vd, clockid_t clock, + struct timespec *ts) +{ + int ret = 0; + ret = __vdso_clock_gettime_common(vd, clock, ts); + return ret; +} + +int +__kernel_clock_gettime(clockid_t clock, struct timespec *ts) +{ + return rt_vdso_clock_gettime_data(__arch_get_vdso_data(), clock, ts); +} diff --git a/components/lwp/vdso/user/vdso_sys.h b/components/lwp/vdso/user/vdso_sys.h new file mode 100644 index 0000000000..ecc7b366ad --- /dev/null +++ b/components/lwp/vdso/user/vdso_sys.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#ifndef ASM_VDSO_SYS_H +#define ASM_VDSO_SYS_H + +#include +#include +#include +#include +#include + +#define __always_unused __attribute__((__unused__)) +#define __maybe_unused __attribute__((__unused__)) + +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) + +#define arch_counter_enforce_ordering(val) do { \ + uint64_t tmp, _val = (val); \ + \ + asm volatile( \ + " eor %0, %1, %1\n" \ + " add %0, sp, %0\n" \ + " ldr xzr, [%0]" \ + : "=r" (tmp) : "r" (_val)); \ +} while (0) + +static inline uint64_t __arch_get_hw_counter() +{ + uint64_t res; + + __asm__ volatile("mrs %0, CNTVCT_EL0":"=r"(res)); + + arch_counter_enforce_ordering(res); + return res; +} + +static inline uint64_t __arch_get_hw_frq() +{ + uint64_t res; + + __asm__ volatile("mrs %0, CNTFRQ_EL0":"=r"(res)); + + arch_counter_enforce_ordering(res); + return res; +} + +static inline uint32_t +__iter_div_u64_rem(uint64_t dividend, uint32_t divisor, uint64_t *remainder) +{ + uint32_t ret = 0; + + while (dividend >= divisor) { + /* The following asm() prevents the compiler from + optimising this loop into a modulo operation. */ + __asm__("" : "+rm"(dividend)); + + dividend -= divisor; + ret++; + } + + *remainder = dividend; + + return ret; +} + +#define __RT_STRINGIFY(x...) #x +#define RT_STRINGIFY(x...) __RT_STRINGIFY(x) +#define rt_hw_barrier(cmd, ...) \ + __asm__ volatile (RT_STRINGIFY(cmd) " "RT_STRINGIFY(__VA_ARGS__):::"memory") + +#define rt_hw_isb() rt_hw_barrier(isb) +#define rt_hw_dmb() rt_hw_barrier(dmb, ish) +#define rt_hw_wmb() rt_hw_barrier(dmb, ishst) +#define rt_hw_rmb() rt_hw_barrier(dmb, ishld) +#define rt_hw_dsb() rt_hw_barrier(dsb, ish) + +#ifndef barrier +/* The "volatile" is due to gcc bugs */ +# define barrier() __asm__ __volatile__("": : :"memory") +#endif + +static inline void cpu_relax(void) +{ + __asm__ volatile("yield" ::: "memory"); +} + +#define __READ_ONCE_SIZE \ +({ \ + switch (size) { \ + case 1: *(__u8 *)res = *(volatile __u8 *)p; break; \ + case 2: *(__u16 *)res = *(volatile __u16 *)p; break; \ + case 4: *(__u32 *)res = *(volatile __u32 *)p; break; \ + case 8: *(__u64 *)res = *(volatile __u64 *)p; break; \ + default: \ + barrier(); \ + __builtin_memcpy((void *)res, (const void *)p, size); \ + barrier(); \ + } \ +}) + +static inline +void __read_once_size(const volatile void *p, void *res, int size) +{ + __READ_ONCE_SIZE; +} + +#define __READ_ONCE(x, check) \ +({ \ + union { typeof(x) __val; char __c[1]; } __u; \ + if (check) \ + __read_once_size(&(x), __u.__c, sizeof(x)); \ + smp_read_barrier_depends(); /* Enforce dependency ordering from x */ \ + __u.__val; \ +}) +#define READ_ONCE(x) __READ_ONCE(x, 1) + +extern struct vdso_data _vdso_data[CS_BASES] __attribute__((visibility("hidden"))); +static inline struct vdso_data *__arch_get_vdso_data(void) +{ + return _vdso_data; +} + +static inline uint32_t rt_vdso_read_begin(const struct vdso_data *vd) +{ + uint32_t seq; + + while (unlikely((seq = READ_ONCE(vd->seq)) & 1)) + cpu_relax(); + + rt_hw_rmb(); + return seq; +} + +static inline uint32_t rt_vdso_read_retry(const struct vdso_data *vd, + uint32_t start) +{ + uint32_t seq; + + rt_hw_rmb(); + seq = READ_ONCE(vd->seq); + return seq != start; +} + +#endif diff --git a/components/lwp/vdso/user/xmake.lua b/components/lwp/vdso/user/xmake.lua new file mode 100644 index 0000000000..c36448131f --- /dev/null +++ b/components/lwp/vdso/user/xmake.lua @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +toolchain("aarch64-smart-musleabi") + set_kind("standalone") + + local exec_path = os.getenv("RTT_EXEC_PATH") or "/opt/aarch64-linux-musleabi/bin/" + local sdkdir = exec_path .. "/../" + local incdir = os.curdir() .. "/../include" + local device = '-march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' + + set_bindir(exec_path) + set_sdkdir(sdkdir) + + set_toolset("sh", "aarch64-linux-musleabi-gcc") + on_load(function(toolchain) + toolchain:load_cross_toolchain() + toolchain:add("cxflags", device) + toolchain:add("cxflags", "-Wall -Wno-cpp -std=gnu99") + toolchain:add("cxflags", "-fdiagnostics-color=always") + toolchain:add("cxflags", "-O2") + toolchain:add("cxflags", "-I" .. incdir) + + toolchain:add("shflags", device) + toolchain:add("shflags", "-Wl,--gc-sections") + toolchain:add("shflags", "-u,system_vectors") + toolchain:add("shflags", "-T vdso.lds") + end) +toolchain_end() + +set_config("plat", "cross") +set_config("target_os", "rt-smart") +set_config("arch", "aarch64") + +rule("vdso_lds") + set_extensions(".lds.S") + on_buildcmd_file(function (target, batchcmds, sourcefile, opt) + local incdir = os.curdir() .. "/../include" + local targetfile = path.basename(sourcefile) + local prefix = os.getenv("RTT_CC_PREFIX=") or "aarch64-linux-musleabi-" + batchcmds:vrunv(prefix .. "gcc", {"-E", "-P", sourcefile, "-o", targetfile, "-I", incdir}) + end) + +target("rtos_vdso") + set_toolchains("aarch64-smart-musleabi") + add_rules("vdso_lds") + set_kind("shared") + add_files("vdso.lds.S") + add_files("vdso_sys.c") + set_targetdir("build") +target_end() diff --git a/components/lwp/vdso/vdso_config.h b/components/lwp/vdso/vdso_config.h new file mode 100644 index 0000000000..ec5d775a33 --- /dev/null +++ b/components/lwp/vdso/vdso_config.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#ifndef __ASM_VDSO_H +#define __ASM_VDSO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define __VVAR_PAGES 2 +#define VDSO_PAGE_SHIFT 12 +#define VDSO_PAGE_SIZE (1 << VDSO_PAGE_SHIFT) + +#define BIT_MASK(nr) ((1) << (nr)) + +#ifndef read_barrier_depends +#define read_barrier_depends() do { } while (0) +#endif + +#ifndef smp_read_barrier_depends +#define smp_read_barrier_depends() read_barrier_depends() +#endif + +#define VDSO_PATH "../user/build/librtos_vdso.so" + +#ifdef __cplusplus +} +#endif + +#endif /* __ASM_VDSO_H */ diff --git a/components/lwp/vdso/vdso_datapage.h b/components/lwp/vdso/vdso_datapage.h new file mode 100644 index 0000000000..243af48bf1 --- /dev/null +++ b/components/lwp/vdso/vdso_datapage.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#ifndef _VDSO_DATAPAGE_H +#define _VDSO_DATAPAGE_H + +#include +#include +#include "vdso_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef signed char __s8; +typedef signed short __s16; +typedef signed int __s32; +typedef signed long __s64; + +typedef unsigned char __u8; +typedef unsigned short __u16; +typedef unsigned int __u32; +typedef unsigned long __u64; + +#define MAX_CLOCKS 16 + +#define VDSO_BASES (CLOCK_TAI + 1) +#define VDSO_REALTIME (BIT_MASK(CLOCK_REALTIME) | \ + BIT_MASK(CLOCK_REALTIME_COARSE)) +#define VDSO_MONOTIME (BIT_MASK(CLOCK_MONOTONIC) | \ + BIT_MASK(CLOCK_MONOTONIC_COARSE) | \ + BIT_MASK(CLOCK_MONOTONIC_RAW) | \ + BIT_MASK(CLOCK_BOOTTIME)) + +#define CS_HRES_COARSE 0 +#define CS_RAW 1 +#define CS_BASES (CS_RAW + 1) + +/* 2018-01-30 14:44:50 = RTC_TIME_INIT(2018, 1, 30, 14, 44, 50) */ +#define RTC_VDSOTIME_INIT(year, month, day, hour, minute, second) \ + {.tm_year = year - 1900, .tm_mon = month - 1, .tm_mday = day, .tm_hour = hour, .tm_min = minute, .tm_sec = second} + +#ifndef SOFT_RTC_VDSOTIME_DEFAULT +#define SOFT_RTC_VDSOTIME_DEFAULT RTC_VDSOTIME_INIT(2018, 1, 1, 0, 0 ,0) +#endif + +struct vdso_data { + uint32_t seq; + uint32_t clock_mode; + uint64_t realtime_initdata; + uint64_t cycle_last; + struct timespec basetime[VDSO_BASES]; +}; +typedef struct vdso_data *vdso_data_t; + +#define MSEC_PER_SEC 1000L +#define USEC_PER_MSEC 1000L +#define NSEC_PER_USEC 1000L +#define NSEC_PER_MSEC 1000000L +#define USEC_PER_SEC 1000000L +#define NSEC_PER_SEC 1000000000L +#define FSEC_PER_SEC 1000000000000000LL + +#ifdef __cplusplus +} +#endif + +#endif /* _VDSO_DATAPAGE_H */ diff --git a/components/lwp/vdso/vdso_weak.c b/components/lwp/vdso/vdso_weak.c new file mode 100644 index 0000000000..56f452cc87 --- /dev/null +++ b/components/lwp/vdso/vdso_weak.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-07-04 rcitach init ver. + */ + +#include +#include +#include "vdso.h" + +rt_weak int arch_setup_additional_pages(struct rt_lwp *lwp) +{ + return -RT_ERROR; +} + +rt_weak void rt_vdso_update_glob_time(void) +{ + +} diff --git a/libcpu/aarch64/cortex-a/entry_point.S b/libcpu/aarch64/cortex-a/entry_point.S index 315e331aac..c0acacb2ca 100644 --- a/libcpu/aarch64/cortex-a/entry_point.S +++ b/libcpu/aarch64/cortex-a/entry_point.S @@ -234,6 +234,10 @@ init_cpu_el: bic x0, x0, #(1 << 1) /* Disable Alignment check */ msr sctlr_el1, x0 + mrs x0, cntkctl_el1 + orr x0, x0, #(1 << 1) /* Set EL0VCTEN, enabling the EL0 Virtual Count Timer */ + msr cntkctl_el1, x0 + /* Avoid trap from SIMD or float point instruction */ mov x0, #0x00300000 /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */ msr cpacr_el1, x0 diff --git a/src/clock.c b/src/clock.c index 6a2366a0ac..34684d2885 100644 --- a/src/clock.c +++ b/src/clock.c @@ -23,6 +23,10 @@ #include #include +#if defined(RT_USING_SMART) && defined(RT_USING_VDSO) +#include +#endif + #ifdef RT_USING_SMP #define rt_tick rt_cpu_index(0)->tick #else @@ -141,6 +145,10 @@ void rt_tick_increase(void) } #endif rt_timer_check(); + +#ifdef RT_USING_VDSO + rt_vdso_update_glob_time(); +#endif } /** From 80668e0ba20572d98300fdbaeb31a7aaf698b443 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 24 May 2024 08:58:09 +0800 Subject: [PATCH 03/14] bsp:cvitek: revert add i2c pinmux config for c906 The contents of the SOC type part in the Kconfig configuration are retained, and other parts related to I2C pin multiplexing selection have been rolled back. Signed-off-by: Chen Wang Reviewed-by: Yuanjie He <943313837@qq.com> Reviewed-by: Shell --- bsp/cvitek/c906_little/board/Kconfig | 115 --------- bsp/cvitek/cv18xx_risc-v/board/Kconfig | 115 --------- bsp/cvitek/drivers/drv_hw_i2c.c | 326 +------------------------ 3 files changed, 9 insertions(+), 547 deletions(-) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 52fdc2d2a9..06d8214321 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -29,127 +29,12 @@ menu "General Drivers Configuration" if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" - depends on BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR default n - if BSP_USING_I2C0 - choice - prompt "SCL" - - config BSP_USING_IIC0_SCL__IIC0_SCL - bool "IIC0_SCL/GP0" - endchoice - - choice - prompt "SDA" - - config BSP_USING_IIC0_SDA__IIC0_SDA - bool "IIC0_SDA/GP1" - endchoice - endif - config BSP_USING_I2C1 bool "Enable I2C1" default n - if BSP_USING_I2C1 - choice - prompt "SCL" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_D2__IIC1_SCL - bool "SD1_D2/GP4" - config BSP_USING_SD1_D3__IIC1_SCL - bool "SD1_D3/GP9" - config BSP_USING_PAD_MIPIRX0N__IIC1_SCL - bool "PAD_MIPIRX0N/GP11" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_D2__IIC1_SCL - bool "SD1_D2/GP4" - config BSP_USING_SD1_D3__IIC1_SCL - bool "SD1_D3/GP9" - endif - - endchoice - - choice - prompt "SDA" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_D1__IIC1_SDA - bool "SD1_D1/GP5" - config BSP_USING_SD1_D0__IIC1_SDA - bool "SD1_D0/GP8" - config BSP_USING_PAD_MIPIRX1P__IIC1_SDA - bool "PAD_MIPIRX1P/GP10" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_D1__IIC1_SDA - bool "SD1_D1/GP5" - config BSP_USING_SD1_D0__IIC1_SDA - bool "SD1_D0/GP8" - endif - endchoice - endif - - config BSP_USING_I2C2 - bool "Enable I2C2" - depends on BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - default n - - if BSP_USING_I2C2 - choice - prompt "SCL" - - config BSP_USING_PAD_MIPI_TXP1__IIC2_SCL - bool "PAD_MIPI_TXP1/GP11" - endchoice - - choice - prompt "SDA" - - config BSP_USING_PAD_MIPI_TXM1__IIC2_SDA - bool "PAD_MIPI_TXM1/GP10" - endchoice - endif - - config BSP_USING_I2C3 - bool "Enable I2C3" - default n - - if BSP_USING_I2C3 - choice - prompt "SCL" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_CMD__IIC3_SCL - bool "SD1_CMD/GP7" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_CMD__IIC3_SCL - bool "SD1_CMD/GP7" - endif - endchoice - - choice - prompt "SDA" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_CLK__IIC3_SDA - bool "SD1_CLK/GP6" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_CLK__IIC3_SDA - bool "SD1_CLK/GP6" - endif - endchoice - endif - config I2C_IRQ_BASE int default 32 diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 50efa0e0b0..bc213c777e 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -42,127 +42,12 @@ menu "General Drivers Configuration" if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" - depends on BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR default n - if BSP_USING_I2C0 - choice - prompt "SCL" - - config BSP_USING_IIC0_SCL__IIC0_SCL - bool "IIC0_SCL/GP0" - endchoice - - choice - prompt "SDA" - - config BSP_USING_IIC0_SDA__IIC0_SDA - bool "IIC0_SDA/GP1" - endchoice - endif - config BSP_USING_I2C1 bool "Enable I2C1" default n - if BSP_USING_I2C1 - choice - prompt "SCL" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_D2__IIC1_SCL - bool "SD1_D2/GP4" - config BSP_USING_SD1_D3__IIC1_SCL - bool "SD1_D3/GP9" - config BSP_USING_PAD_MIPIRX0N__IIC1_SCL - bool "PAD_MIPIRX0N/GP11" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_D2__IIC1_SCL - bool "SD1_D2/GP4" - config BSP_USING_SD1_D3__IIC1_SCL - bool "SD1_D3/GP9" - endif - - endchoice - - choice - prompt "SDA" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_D1__IIC1_SDA - bool "SD1_D1/GP5" - config BSP_USING_SD1_D0__IIC1_SDA - bool "SD1_D0/GP8" - config BSP_USING_PAD_MIPIRX1P__IIC1_SDA - bool "PAD_MIPIRX1P/GP10" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_D1__IIC1_SDA - bool "SD1_D1/GP5" - config BSP_USING_SD1_D0__IIC1_SDA - bool "SD1_D0/GP8" - endif - endchoice - endif - - config BSP_USING_I2C2 - bool "Enable I2C2" - depends on BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - default n - - if BSP_USING_I2C2 - choice - prompt "SCL" - - config BSP_USING_PAD_MIPI_TXP1__IIC2_SCL - bool "PAD_MIPI_TXP1/GP11" - endchoice - - choice - prompt "SDA" - - config BSP_USING_PAD_MIPI_TXM1__IIC2_SDA - bool "PAD_MIPI_TXM1/GP10" - endchoice - endif - - config BSP_USING_I2C3 - bool "Enable I2C3" - default n - - if BSP_USING_I2C3 - choice - prompt "SCL" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_CMD__IIC3_SCL - bool "SD1_CMD/GP7" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_CMD__IIC3_SCL - bool "SD1_CMD/GP7" - endif - endchoice - - choice - prompt "SDA" - - if BOARD_TYPE_MILKV_DUO || BOARD_TYPE_MILKV_DUO_SPINOR - config BSP_USING_SD1_CLK__IIC3_SDA - bool "SD1_CLK/GP6" - endif - - if BOARD_TYPE_MILKV_DUO256M || BOARD_TYPE_MILKV_DUO256M_SPINOR - config BSP_USING_SD1_CLK__IIC3_SDA - bool "SD1_CLK/GP6" - endif - endchoice - endif - config I2C_IRQ_BASE int default 49 diff --git a/bsp/cvitek/drivers/drv_hw_i2c.c b/bsp/cvitek/drivers/drv_hw_i2c.c index 3189de4579..022a050c74 100644 --- a/bsp/cvitek/drivers/drv_hw_i2c.c +++ b/bsp/cvitek/drivers/drv_hw_i2c.c @@ -467,327 +467,19 @@ static const struct rt_i2c_bus_device_ops i2c_ops = .i2c_bus_control = RT_NULL }; -static void rt_hw_i2c_pinmux_config_i2c0() -{ -#ifdef BSP_USING_I2C0 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_IIC0_SCL__IIC0_SCL) - PINMUX_CONFIG(IIC0_SCL, IIC0_SCL); - #elif defined(BSP_USING_PWR_GPIO2__IIC0_SCL) - PINMUX_CONFIG(PWR_GPIO2, IIC0_SCL); - #elif defined(BSP_USING_PAD_MIPIRX4N__IIC0_SCL) - PINMUX_CONFIG(PAD_MIPIRX4N, IIC0_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP2__IIC0_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP2, IIC0_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_IIC0_SCL__IIC0_SCL) - PINMUX_CONFIG(IIC0_SCL, IIC0_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_IIC0_SDA__IIC0_SDA) - PINMUX_CONFIG(IIC0_SDA, IIC0_SDA); - #elif defined(BSP_USING_PWR_GPIO1__IIC0_SDA) - PINMUX_CONFIG(PWR_GPIO1, IIC0_SDA); - #elif defined(BSP_USING_PAD_MIPIRX4P__IIC0_SDA) - PINMUX_CONFIG(PAD_MIPIRX4P, IIC0_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM2__IIC0_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM2, IIC0_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_IIC0_SDA__IIC0_SDA) - PINMUX_CONFIG(IIC0_SDA, IIC0_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C0 */ -} - -static void rt_hw_i2c_pinmux_config_i2c1() -{ -#ifdef BSP_USING_I2C1 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_SD0_CMD__IIC1_SCL) - PINMUX_CONFIG(SD0_CMD, IIC1_SCL); - #elif defined(BSP_USING_SD0_D2__IIC1_SCL) - PINMUX_CONFIG(SD0_D2, IIC1_SCL); - #elif defined(BSP_USING_SD1_D3__IIC1_SCL) - PINMUX_CONFIG(SD1_D3, IIC1_SCL); - #elif defined(BSP_USING_SD1_D2__IIC1_SCL) - PINMUX_CONFIG(SD1_D2, IIC1_SCL); - #elif defined(BSP_USING_MUX_SPI1_MOSI__IIC1_SCL) - PINMUX_CONFIG(MUX_SPI1_MOSI, IIC1_SCL); - #elif defined(BSP_USING_PAD_ETH_TXP__IIC1_SCL) - PINMUX_CONFIG(PAD_ETH_TXP, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPIRX4P__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPIRX4P, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPIRX0N__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP2__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP2, IIC1_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_SD0_CMD__IIC1_SCL) - PINMUX_CONFIG(SD0_CMD, IIC1_SCL); - #elif defined(BSP_USING_SD0_D2__IIC1_SCL) - PINMUX_CONFIG(SD0_D2, IIC1_SCL); - #elif defined(BSP_USING_SD1_D3__IIC1_SCL) - PINMUX_CONFIG(SD1_D3, IIC1_SCL); - #elif defined(BSP_USING_SD1_D2__IIC1_SCL) - PINMUX_CONFIG(SD1_D2, IIC1_SCL); - #elif defined(BSP_USING_MUX_SPI1_MOSI__IIC1_SCL) - PINMUX_CONFIG(MUX_SPI1_MOSI, IIC1_SCL); - #elif defined(BSP_USING_PAD_ETH_TXP__IIC1_SCL) - PINMUX_CONFIG(PAD_ETH_TXP, IIC1_SCL); - #elif defined(BSP_USING_VIVO_D9__IIC1_SCL) - PINMUX_CONFIG(VIVO_D9, IIC1_SCL); - #elif defined(BSP_USING_VIVO_D3__IIC1_SCL) - PINMUX_CONFIG(VIVO_D3, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPIRX4P__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPIRX4P, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPIRX0N__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP4__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP4, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP3__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP3, IIC1_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP2__IIC1_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP2, IIC1_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_SD0_CLK__IIC1_SDA) - PINMUX_CONFIG(SD0_CLK, IIC1_SDA); - #elif defined(BSP_USING_SD0_D1__IIC1_SDA) - PINMUX_CONFIG(SD0_D1, IIC1_SDA); - #elif defined(BSP_USING_SD1_D1__IIC1_SDA) - PINMUX_CONFIG(SD1_D1, IIC1_SDA); - #elif defined(BSP_USING_SD1_D0__IIC1_SDA) - PINMUX_CONFIG(SD1_D0, IIC1_SDA); - #elif defined(BSP_USING_MUX_SPI1_MISO__IIC1_SDA) - PINMUX_CONFIG(MUX_SPI1_MISO, IIC1_SDA); - #elif defined(BSP_USING_PAD_ETH_TXM__IIC1_SDA) - PINMUX_CONFIG(PAD_ETH_TXM, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPIRX4N__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPIRX4N, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPIRX1P__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM2__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM2, IIC1_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_SD0_CLK__IIC1_SDA) - PINMUX_CONFIG(SD0_CLK, IIC1_SDA); - #elif defined(BSP_USING_SD0_D1__IIC1_SDA) - PINMUX_CONFIG(SD0_D1, IIC1_SDA); - #elif defined(BSP_USING_SD1_D1__IIC1_SDA) - PINMUX_CONFIG(SD1_D1, IIC1_SDA); - #elif defined(BSP_USING_SD1_D0__IIC1_SDA) - PINMUX_CONFIG(SD1_D0, IIC1_SDA); - #elif defined(BSP_USING_MUX_SPI1_MISO__IIC1_SDA) - PINMUX_CONFIG(MUX_SPI1_MISO, IIC1_SDA); - #elif defined(BSP_USING_PAD_ETH_TXM__IIC1_SDA) - PINMUX_CONFIG(PAD_ETH_TXM, IIC1_SDA); - #elif defined(BSP_USING_VIVO_D10__IIC1_SDA) - PINMUX_CONFIG(VIVO_D10, IIC1_SDA); - #elif defined(BSP_USING_VIVO_D4__IIC1_SDA) - PINMUX_CONFIG(VIVO_D4, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPIRX4N__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPIRX4N, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPIRX1P__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM4__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM4, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM3__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM3, IIC1_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM2__IIC1_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM2, IIC1_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C1 */ -} - -static void rt_hw_i2c_pinmux_config_i2c2() -{ -#ifdef BSP_USING_I2C2 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_PWR_GPIO1__IIC2_SCL) - PINMUX_CONFIG(PWR_GPIO1, IIC2_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP1__IIC2_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_PWR_GPIO1__IIC2_SCL) - PINMUX_CONFIG(PWR_GPIO1, IIC2_SCL); - #elif defined(BSP_USING_IIC2_SCL__IIC2_SCL) - PINMUX_CONFIG(IIC2_SCL, IIC2_SCL); - #elif defined(BSP_USING_VIVO_D8__IIC2_SCL) - PINMUX_CONFIG(VIVO_D8, IIC2_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP3__IIC2_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP3, IIC2_SCL); - #elif defined(BSP_USING_PAD_MIPI_TXP1__IIC2_SCL) - PINMUX_CONFIG(PAD_MIPI_TXP1, IIC2_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_PWR_GPIO2__IIC2_SDA) - PINMUX_CONFIG(PWR_GPIO2, IIC2_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM1__IIC2_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_PWR_GPIO2__IIC2_SDA) - PINMUX_CONFIG(PWR_GPIO2, IIC2_SDA); - #elif defined(BSP_USING_IIC2_SDA__IIC2_SDA) - PINMUX_CONFIG(IIC2_SDA, IIC2_SDA); - #elif defined(BSP_USING_VIVO_D7__IIC2_SDA) - PINMUX_CONFIG(VIVO_D7, IIC2_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM3__IIC2_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM3, IIC2_SDA); - #elif defined(BSP_USING_PAD_MIPI_TXM1__IIC2_SDA) - PINMUX_CONFIG(PAD_MIPI_TXM1, IIC2_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C2 */ -} - -static void rt_hw_i2c_pinmux_config_i2c3() -{ -#ifdef BSP_USING_I2C3 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_SD1_CMD__IIC3_SCL) - PINMUX_CONFIG(SD1_CMD, IIC3_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_IIC3_SCL__IIC3_SCL) - PINMUX_CONFIG(IIC3_SCL, IIC3_SCL); - #elif defined(BSP_USING_SD1_CMD__IIC3_SCL) - PINMUX_CONFIG(SD1_CMD, IIC3_SCL); - #elif defined(BSP_USING_VIVO_D0__IIC3_SCL) - PINMUX_CONFIG(VIVO_D0, IIC3_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_SD1_CLK__IIC3_SDA) - PINMUX_CONFIG(SD1_CLK, IIC3_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_IIC3_SDA__IIC3_SDA) - PINMUX_CONFIG(IIC3_SDA, IIC3_SDA); - #elif defined(BSP_USING_SD1_CLK__IIC3_SDA) - PINMUX_CONFIG(SD1_CLK, IIC3_SDA); - #elif defined(BSP_USING_VIVO_D1__IIC3_SDA) - PINMUX_CONFIG(VIVO_D1, IIC3_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C3 */ -} - -static void rt_hw_i2c_pinmux_config_i2c4() -{ -#ifdef BSP_USING_I2C4 - - // SCL - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_PWR_WAKEUP0__IIC4_SCL) - PINMUX_CONFIG(PWR_WAKEUP0, IIC4_SCL); - #elif defined(BSP_USING_PAD_MIPIRX2N__IIC4_SCL) - PINMUX_CONFIG(PAD_MIPIRX2N, IIC4_SCL); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_CAM_RST0__IIC4_SCL) - PINMUX_CONFIG(CAM_RST0, IIC4_SCL); - #elif defined(BSP_USING_PWR_WAKEUP0__IIC4_SCL) - PINMUX_CONFIG(PWR_WAKEUP0, IIC4_SCL); - #elif defined(BSP_USING_PWR_WAKEUP1__IIC4_SCL) - PINMUX_CONFIG(PWR_WAKEUP1, IIC4_SCL); - #elif defined(BSP_USING_ADC3__IIC4_SCL) - PINMUX_CONFIG(ADC3, IIC4_SCL); - #elif defined(BSP_USING_VIVO_D1__IIC4_SCL) - PINMUX_CONFIG(VIVO_D1, IIC4_SCL); - #endif - #endif // SOC_TYPE_SG2002 - - // SDA - #if defined(SOC_TYPE_CV180X) - #if defined(BSP_USING_PWR_BUTTON1__IIC4_SDA) - PINMUX_CONFIG(PWR_BUTTON1, IIC4_SDA); - #elif defined(BSP_USING_PAD_MIPIRX2P__IIC4_SDA) - PINMUX_CONFIG(PAD_MIPIRX2P, IIC4_SDA); - #endif - #endif // SOC_TYPE_CV180X - - #if defined(SOC_TYPE_SG2002) - #if defined(BSP_USING_CAM_PD1__IIC4_SDA) - PINMUX_CONFIG(CAM_PD1, IIC4_SDA); - #elif defined(BSP_USING_PWR_BUTTON1__IIC4_SDA) - PINMUX_CONFIG(PWR_BUTTON1, IIC4_SDA); - #elif defined(BSP_USING_PWR_ON__IIC4_SDA) - PINMUX_CONFIG(PWR_ON, IIC4_SDA); - #elif defined(BSP_USING_ADC2__IIC4_SDA) - PINMUX_CONFIG(ADC2, IIC4_SDA); - #elif defined(BSP_USING_VIVO_D0__IIC4_SDA) - PINMUX_CONFIG(VIVO_D0, IIC4_SDA); - #elif defined(BSP_USING_PAD_MIPIRX2P__IIC4_SDA) - PINMUX_CONFIG(PAD_MIPIRX2P, IIC4_SDA); - #endif - #endif // SOC_TYPE_SG2002 - -#endif /* BSP_USING_I2C4 */ -} - -static void rt_hw_i2c_pinmux_config() -{ - rt_hw_i2c_pinmux_config_i2c0(); - rt_hw_i2c_pinmux_config_i2c1(); - rt_hw_i2c_pinmux_config_i2c2(); - rt_hw_i2c_pinmux_config_i2c3(); - rt_hw_i2c_pinmux_config_i2c4(); -} - int rt_hw_i2c_init(void) { int result = RT_EOK; - rt_hw_i2c_pinmux_config(); +#ifdef BSP_USING_I2C0 + PINMUX_CONFIG(IIC0_SCL, IIC0_SCL); + PINMUX_CONFIG(IIC0_SDA, IIC0_SDA); +#endif /* BSP_USING_I2C0 */ + +#ifdef BSP_USING_I2C1 + PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA); + PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL); +#endif /* BSP_USING_I2C1 */ for (rt_size_t i = 0; i < sizeof(_i2c_obj) / sizeof(struct _i2c_bus); i++) { From a63c07fd75ec9632e063646f043db3bfdad2aa49 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 16:24:47 +0800 Subject: [PATCH 04/14] bsp: cvitek: new design for pinmux In the new design, we require the user to manually enter the PinName (as a string) in menuconfig instead of being given menu items to select. The original method will lead to too many menu item-related macros being defined in the code, causing ifdef and other codes scatter everywhere in the driver code, which is inconvenient to maintain. The new design adds a pinmux driver module to manage the multiplexing of pins. This patch provides this driver module. P.S., the reason why users are allowed to specify pinname in a string instead of the pin number is mainly because the technical manual provided by the SOC manufacturer does not have numbers for some pins, only names. Signed-off-by: Chen Wang Reviewed-by: Yuanjie He <943313837@qq.com> Reviewed-by: Shell --- bsp/cvitek/drivers/SConscript | 1 + bsp/cvitek/drivers/drv_pinmux.c | 544 ++++++++++++++++++++++++++++++++ bsp/cvitek/drivers/drv_pinmux.h | 448 ++++++++++++++++++++++++++ 3 files changed, 993 insertions(+) create mode 100644 bsp/cvitek/drivers/drv_pinmux.c create mode 100644 bsp/cvitek/drivers/drv_pinmux.h diff --git a/bsp/cvitek/drivers/SConscript b/bsp/cvitek/drivers/SConscript index 96be9b9aa9..d67ffc5e39 100755 --- a/bsp/cvitek/drivers/SConscript +++ b/bsp/cvitek/drivers/SConscript @@ -5,6 +5,7 @@ src = Split(''' drv_uart.c drv_por.c drv_gpio.c + drv_pinmux.c ''') CPPDEFINES = [] diff --git a/bsp/cvitek/drivers/drv_pinmux.c b/bsp/cvitek/drivers/drv_pinmux.c new file mode 100644 index 0000000000..17e7857944 --- /dev/null +++ b/bsp/cvitek/drivers/drv_pinmux.c @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/05/24 unicornx first version + */ + +#include + +#include +#include "mmio.h" +#include "pinctrl.h" +#include "drv_pinmux.h" + +#define DBG_TAG "drv.pinmux" +#define DBG_LVL DBG_INFO +#include + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(ar) (sizeof(ar)/sizeof(ar[0])) +#endif + +/** + * @brief Function Selection for one Pin + * + * type: type of function + * select: value of selection + */ +struct fselect { + fs_type type; + uint8_t select; +}; + +/** + * @brief Function Mux for one Pin + * + * name: Pin Name + * addr: offset of pinmux registers against PINMUX_BASE + * offset: offset of function selection field in the pinmux register + * mask: mask of function selection field in the pinmux register + * selected: 1 if this pin has been selected, used for binding check. + */ +struct fmux { + char *name; + uint16_t addr; + uint8_t offset; + uint8_t mask; + uint8_t selected; +}; + +#define FS_NONE {fs_none, 0} + +#define FS_PINMUX(PIN_NAME) { \ + .name = #PIN_NAME, \ + .addr = FMUX_GPIO_FUNCSEL_##PIN_NAME, \ + .offset = PINMUX_OFFSET(PIN_NAME), \ + .mask = PINMUX_MASK(PIN_NAME), \ + .selected = 0, \ + } + + +/** + * @brief Define TWO tables for every SOC. + * + * Table-1: pinmux_array: every line maps to one pin register, store basic info. + * Table-2: pin_selects_array: function selection array, extend Table-1, store + * function selection info. + * NOTE: Index of pinmux_array matches the same as that in pin_selects_array. + */ +#if defined(SOC_TYPE_CV180X) + +struct fmux pinmux_array[] = { + FS_PINMUX(SD0_CLK), + FS_PINMUX(SD0_CMD), + FS_PINMUX(SD0_D0), + FS_PINMUX(SD0_D1), + FS_PINMUX(SD0_D2), + FS_PINMUX(SD0_D3), + FS_PINMUX(SD0_CD), + FS_PINMUX(SD0_PWR_EN), + FS_PINMUX(SPK_EN), + FS_PINMUX(UART0_TX), + FS_PINMUX(UART0_RX), + FS_PINMUX(SPINOR_HOLD_X), + FS_PINMUX(SPINOR_SCK), + FS_PINMUX(SPINOR_MOSI), + FS_PINMUX(SPINOR_WP_X), + FS_PINMUX(SPINOR_MISO), + FS_PINMUX(SPINOR_CS_X), + FS_PINMUX(JTAG_CPU_TMS), + FS_PINMUX(JTAG_CPU_TCK), + FS_PINMUX(IIC0_SCL), + FS_PINMUX(IIC0_SDA), + FS_PINMUX(AUX0), + FS_PINMUX(GPIO_ZQ), + FS_PINMUX(PWR_VBAT_DET), + FS_PINMUX(PWR_RSTN), + FS_PINMUX(PWR_SEQ1), + FS_PINMUX(PWR_SEQ2), + FS_PINMUX(PWR_WAKEUP0), + FS_PINMUX(PWR_BUTTON1), + FS_PINMUX(XTAL_XIN), + FS_PINMUX(PWR_GPIO0), + FS_PINMUX(PWR_GPIO1), + FS_PINMUX(PWR_GPIO2), + FS_PINMUX(SD1_GPIO1), + FS_PINMUX(SD1_GPIO0), + FS_PINMUX(SD1_D3), + FS_PINMUX(SD1_D2), + FS_PINMUX(SD1_D1), + FS_PINMUX(SD1_D0), + FS_PINMUX(SD1_CMD), + FS_PINMUX(SD1_CLK), + FS_PINMUX(PWM0_BUCK), + FS_PINMUX(ADC1), + FS_PINMUX(USB_VBUS_DET), + FS_PINMUX(MUX_SPI1_MISO), + FS_PINMUX(MUX_SPI1_MOSI), + FS_PINMUX(MUX_SPI1_CS), + FS_PINMUX(MUX_SPI1_SCK), + FS_PINMUX(PAD_ETH_TXP), + FS_PINMUX(PAD_ETH_TXM), + FS_PINMUX(PAD_ETH_RXP), + FS_PINMUX(PAD_ETH_RXM), + FS_PINMUX(GPIO_RTX), + FS_PINMUX(PAD_MIPIRX4N), + FS_PINMUX(PAD_MIPIRX4P), + FS_PINMUX(PAD_MIPIRX3N), + FS_PINMUX(PAD_MIPIRX3P), + FS_PINMUX(PAD_MIPIRX2N), + FS_PINMUX(PAD_MIPIRX2P), + FS_PINMUX(PAD_MIPIRX1N), + FS_PINMUX(PAD_MIPIRX1P), + FS_PINMUX(PAD_MIPIRX0N), + FS_PINMUX(PAD_MIPIRX0P), + FS_PINMUX(PAD_MIPI_TXM2), + FS_PINMUX(PAD_MIPI_TXP2), + FS_PINMUX(PAD_MIPI_TXM1), + FS_PINMUX(PAD_MIPI_TXP1), + FS_PINMUX(PAD_MIPI_TXM0), + FS_PINMUX(PAD_MIPI_TXP0), + FS_PINMUX(PKG_TYPE0), + FS_PINMUX(PKG_TYPE1), + FS_PINMUX(PKG_TYPE2), + FS_PINMUX(PAD_AUD_AINL_MIC), + FS_PINMUX(PAD_AUD_AINR_MIC), + FS_PINMUX(PAD_AUD_AOUTL), + FS_PINMUX(PAD_AUD_AOUTR), +}; + +const struct fselect pin_selects_array[][8] = { +/* SD0_CLK */ {{SDIO0_CLK, 0}, {IIC1_SDA, 1}, {SPI0_SCK, 2}, {XGPIOA_7, 3}, FS_NONE, {PWM_15, 5}, {EPHY_LNK_LED, 6}, {DBG_0, 7}}, +/* SD0_CMD */ {{SDIO0_CMD, 0}, {IIC1_SCL, 1}, {SPI0_SDO, 2}, {XGPIOA_8, 3}, FS_NONE, {PWM_14, 5}, {EPHY_SPD_LED, 6}, {DBG_1, 7}}, +/* SD0_D0 */ {{SDIO0_D_0, 0}, {CAM_MCLK1, 1}, {SPI0_SDI, 2}, {XGPIOA_9, 3}, {UART3_TX, 4}, {PWM_13, 5}, {WG0_D0, 6}, {DBG_2, 7}}, +/* SD0_D1 */ {{SDIO0_D_1, 0}, {IIC1_SDA, 1}, {AUX0, 2}, {XGPIOA_10, 3}, {UART1_TX, 4}, {PWM_12, 5}, {WG0_D1, 6}, {DBG_3, 7}}, +/* SD0_D2 */ {{SDIO0_D_2, 0}, {IIC1_SCL, 1}, {AUX1, 2}, {XGPIOA_11, 3}, {UART1_RX, 4}, {PWM_11, 5}, {WG1_D0, 6}, {DBG_4, 7}}, +/* SD0_D3 */ {{SDIO0_D_3, 0}, {CAM_MCLK0, 1}, {SPI0_CS_X, 2}, {XGPIOA_12, 3}, {UART3_RX, 4}, {PWM_10, 5}, {WG1_D1, 6}, {DBG_5, 7}}, +/* SD0_CD */ {{SDIO0_CD, 0}, FS_NONE, FS_NONE, {XGPIOA_13, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SD0_PWR_EN */ {{SDIO0_PWR_EN, 0}, FS_NONE, FS_NONE, {XGPIOA_14, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPK_EN */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOA_15, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* UART0_TX */ {{UART0_TX, 0}, {CAM_MCLK1, 1}, {PWM_4, 2}, {XGPIOA_16, 3}, {UART1_TX, 4}, {AUX1, 5}, {JTAG_TMS, 6}, {DBG_6, 7}}, +/* UART0_RX */ {{UART0_RX, 0}, {CAM_MCLK0, 1}, {PWM_5, 2}, {XGPIOA_17, 3}, {UART1_RX, 4}, {AUX0, 5}, {JTAG_TCK, 6}, {DBG_7, 7}}, +/* SPINOR_HOLD_X */ {FS_NONE, {SPINOR_HOLD_X, 1}, {SPINAND_HOLD, 2}, {XGPIOA_26, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_SCK */ {FS_NONE, {SPINOR_SCK, 1}, {SPINAND_CLK, 2}, {XGPIOA_22, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_MOSI */ {FS_NONE, {SPINOR_MOSI, 1}, {SPINAND_MOSI, 2}, {XGPIOA_25, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_WP_X */ {FS_NONE, {SPINOR_WP_X, 1}, {SPINAND_WP, 2}, {XGPIOA_27, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_MISO */ {FS_NONE, {SPINOR_MISO, 1}, {SPINAND_MISO, 2}, {XGPIOA_23, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPINOR_CS_X */ {FS_NONE, {SPINOR_CS_X, 1}, {SPINAND_CS, 2}, {XGPIOA_24, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* JTAG_CPU_TMS */ {{JTAG_TMS, 0}, {CAM_MCLK0, 1}, {PWM_7, 2}, {XGPIOA_19, 3}, {UART1_RTS, 4}, {AUX0, 5}, {UART1_TX, 6}, FS_NONE}, +/* JTAG_CPU_TCK */ {{JTAG_TCK, 0}, {CAM_MCLK1, 1}, {PWM_6, 2}, {XGPIOA_18, 3}, {UART1_CTS, 4}, {AUX1, 5}, {UART1_RX, 6}, FS_NONE}, +/* IIC0_SCL */ {{JTAG_TDI, 0}, {UART1_TX, 1}, {UART2_TX, 2}, {XGPIOA_28, 3}, {IIC0_SCL, 4}, {WG0_D0, 5}, FS_NONE, {DBG_10, 7}}, +/* IIC0_SDA */ {{JTAG_TDO, 0}, {UART1_RX, 1}, {UART2_RX, 2}, {XGPIOA_29, 3}, {IIC0_SDA, 4}, {WG0_D1, 5}, {WG1_D0, 6}, {DBG_11, 7}}, +/* AUX0 */ {{AUX0, 0}, FS_NONE, FS_NONE, {XGPIOA_30, 3}, {IIS1_MCLK, 4}, FS_NONE, {WG1_D1, 6}, {DBG_12, 7}}, +/* GPIO_ZQ */ {FS_NONE, FS_NONE, FS_NONE, {PWR_GPIO_24, 3}, {PWM_2, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_VBAT_DET */ {{PWR_VBAT_DET, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_RSTN */ {{PWR_RSTN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ1 */ {{PWR_SEQ1, 0}, FS_NONE, {PWR_GPIO_3, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ2 */ {{PWR_SEQ2, 0}, FS_NONE, {PWR_GPIO_4, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_WAKEUP0 */ {{PWR_WAKEUP0, 0}, {PWR_IR0, 1}, {PWR_UART0_TX, 2}, {PWR_GPIO_6, 3}, {UART1_TX, 4}, {IIC4_SCL, 5}, {EPHY_LNK_LED, 6}, {WG2_D0, 7}}, +/* PWR_BUTTON1 */ {{PWR_BUTTON1, 0}, FS_NONE, FS_NONE, {PWR_GPIO_8, 3}, {UART1_RX, 4}, {IIC4_SDA, 5}, {EPHY_SPD_LED, 6}, {WG2_D1, 7}}, +/* XTAL_XIN */ {{PWR_XTAL_CLKIN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_GPIO0 */ {{PWR_GPIO_0, 0}, {UART2_TX, 1}, {PWR_UART0_RX, 2}, FS_NONE, {PWM_8, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_GPIO1 */ {{PWR_GPIO_1, 0}, {UART2_RX, 1}, FS_NONE, {EPHY_LNK_LED, 3},{PWM_9, 4}, {PWR_IIC_SCL, 5}, {IIC2_SCL, 6}, {IIC0_SDA, 7}}, +/* PWR_GPIO2 */ {{PWR_GPIO_2, 0}, FS_NONE, {PWR_SECTICK, 2}, {EPHY_SPD_LED, 3},{PWM_10, 4}, {PWR_IIC_SDA, 5}, {IIC2_SDA, 6}, {IIC0_SCL, 7}}, +/* SD1_GPIO1 */ {FS_NONE, {UART4_TX, 1}, FS_NONE, {PWR_GPIO_26, 3}, FS_NONE, FS_NONE, FS_NONE, {PWM_10, 7}}, +/* SD1_GPIO0 */ {FS_NONE, {UART4_RX, 1}, FS_NONE, {PWR_GPIO_25, 3}, FS_NONE, FS_NONE, FS_NONE, {PWM_11, 7}}, +/* SD1_D3 */ {{PWR_SD1_D3, 0}, {SPI2_CS_X, 1}, {IIC1_SCL, 2}, {PWR_GPIO_18, 3}, {CAM_MCLK0, 4}, {UART3_CTS, 5}, {PWR_SPINOR1_CS_X, 6}, {PWM_4, 7}}, +/* SD1_D2 */ {{PWR_SD1_D2, 0}, {IIC1_SCL, 1}, {UART2_TX, 2}, {PWR_GPIO_19, 3}, {CAM_MCLK0, 4}, {UART3_TX, 5}, {PWR_SPINOR1_HOLD_X, 6},{PWM_5, 7}}, +/* SD1_D1 */ {{PWR_SD1_D1, 0}, {IIC1_SDA, 1}, {UART2_RX, 2}, {PWR_GPIO_20, 3}, {CAM_MCLK1, 4}, {UART3_RX, 5}, {PWR_SPINOR1_WP_X, 6}, {PWM_6, 7}}, +/* SD1_D0 */ {{PWR_SD1_D0, 0}, {SPI2_SDI, 1}, {IIC1_SDA, 2}, {PWR_GPIO_21, 3}, {CAM_MCLK1, 4}, {UART3_RTS, 5}, {PWR_SPINOR1_MISO, 6}, {PWM_7, 7}}, +/* SD1_CMD */ {{PWR_SD1_CMD, 0}, {SPI2_SDO, 1}, {IIC3_SCL, 2}, {PWR_GPIO_22, 3}, {CAM_VS0, 4}, {EPHY_LNK_LED, 5},{PWR_SPINOR1_MOSI, 6}, {PWM_8, 7}}, +/* SD1_CLK */ {{PWR_SD1_CLK, 0}, {SPI2_SCK, 1}, {IIC3_SDA, 2}, {PWR_GPIO_23, 3}, {CAM_HS0, 4}, {EPHY_SPD_LED, 5},{PWR_SPINOR1_SCK, 6}, {PWM_9, 7}}, +/* PWM0_BUCK */ {{PWM_0, 0}, FS_NONE, FS_NONE, {XGPIOB_0, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* ADC1 */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOB_3, 3}, {KEY_COL2, 4}, FS_NONE, {PWM_3, 6}, FS_NONE}, +/* PKG_TYPE0 */ {{PKG_TYPE0, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* USB_VBUS_DET */ {{USB_VBUS_DET, 0}, FS_NONE, FS_NONE, {XGPIOB_6, 3}, {CAM_MCLK0, 4}, {CAM_MCLK1, 5}, {PWM_4, 6}, FS_NONE}, +/* PKG_TYPE1 */ {{PKG_TYPE1, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PKG_TYPE2 */ {{PKG_TYPE2, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* MUX_SPI1_MISO */ {FS_NONE, {UART3_RTS, 1}, {IIC1_SDA, 2}, {XGPIOB_8, 3}, {PWM_9, 4}, {KEY_COL1, 5}, {SPI1_SDI, 6}, {DBG_14, 7}}, +/* MUX_SPI1_MOSI */ {FS_NONE, {UART3_RX, 1}, {IIC1_SCL, 2}, {XGPIOB_7, 3}, {PWM_8, 4}, {KEY_COL0, 5}, {SPI1_SDO, 6}, {DBG_13, 7}}, +/* MUX_SPI1_CS */ {FS_NONE, {UART3_CTS, 1}, {CAM_MCLK0, 2}, {XGPIOB_10, 3}, {PWM_11, 4}, {KEY_ROW3, 5}, {SPI1_CS_X, 6}, {DBG_16, 7}}, +/* MUX_SPI1_SCK */ {FS_NONE, {UART3_TX, 1}, {CAM_MCLK1, 2}, {XGPIOB_9, 3}, {PWM_10, 4}, {KEY_ROW2, 5}, {SPI1_SCK, 6}, {DBG_15, 7}}, +/* PAD_ETH_TXP */ {FS_NONE, {UART3_RX, 1}, {IIC1_SCL, 2}, {XGPIOB_25, 3}, {PWM_13, 4}, {CAM_MCLK0, 5}, {SPI1_SDO, 6}, {IIS2_LRCK, 7}}, +/* PAD_ETH_TXM */ {FS_NONE, {UART3_RTS, 1}, {IIC1_SDA, 2}, {XGPIOB_24, 3}, {PWM_12, 4}, {CAM_MCLK1, 5}, {SPI1_SDI, 6}, {IIS2_BCLK, 7}}, +/* PAD_ETH_RXP */ {FS_NONE, {UART3_TX, 1}, {CAM_MCLK1, 2}, {XGPIOB_27, 3}, {PWM_15, 4}, {CAM_HS0, 5}, {SPI1_SCK, 6}, {IIS2_DO, 7}}, +/* PAD_ETH_RXM */ {FS_NONE, {UART3_CTS, 1}, {CAM_MCLK0, 2}, {XGPIOB_26, 3}, {PWM_14, 4}, {CAM_VS0, 5}, {SPI1_CS_X, 6}, {IIS2_DI, 7}}, +/* GPIO_RTX */ {FS_NONE, {VI0_D_15, 1}, FS_NONE, {XGPIOB_23, 3}, {PWM_1, 4}, {CAM_MCLK0, 5}, FS_NONE, {IIS2_MCLK, 7}}, +/* PAD_MIPIRX4N */ {FS_NONE, {VI0_CLK, 1}, {IIC0_SCL, 2}, {XGPIOC_2, 3}, {IIC1_SDA, 4}, {CAM_MCLK0, 5}, {KEY_ROW0, 6}, {MUX_SPI1_SCK, 7}}, +/* PAD_MIPIRX4P */ {FS_NONE, {VI0_D_0, 1}, {IIC0_SDA, 2}, {XGPIOC_3, 3}, {IIC1_SCL, 4}, {CAM_MCLK1, 5}, {KEY_ROW1, 6}, {MUX_SPI1_CS, 7}}, +/* PAD_MIPIRX3N */ {FS_NONE, {VI0_D_1, 1}, FS_NONE, {XGPIOC_4, 3}, {CAM_MCLK0, 4}, FS_NONE, FS_NONE, {MUX_SPI1_MISO, 7}}, +/* PAD_MIPIRX3P */ {FS_NONE, {VI0_D_2, 1}, FS_NONE, {XGPIOC_5, 3}, FS_NONE, FS_NONE, FS_NONE, {MUX_SPI1_MOSI, 7}}, +/* PAD_MIPIRX2N */ {FS_NONE, {VI0_D_3, 1}, FS_NONE, {XGPIOC_6, 3}, FS_NONE, {IIC4_SCL, 5}, FS_NONE, {DBG_6, 7}}, +/* PAD_MIPIRX2P */ {FS_NONE, {VI0_D_4, 1}, FS_NONE, {XGPIOC_7, 3}, FS_NONE, {IIC4_SDA, 5}, FS_NONE, {DBG_7, 7}}, +/* PAD_MIPIRX1N */ {FS_NONE, {VI0_D_5, 1}, FS_NONE, {XGPIOC_8, 3}, FS_NONE, FS_NONE, {KEY_ROW3, 6}, {DBG_8, 7}}, +/* PAD_MIPIRX1P */ {FS_NONE, {VI0_D_6, 1}, FS_NONE, {XGPIOC_9, 3}, {IIC1_SDA, 4}, FS_NONE, {KEY_ROW2, 6}, {DBG_9, 7}}, +/* PAD_MIPIRX0N */ {FS_NONE, {VI0_D_7, 1}, FS_NONE, {XGPIOC_10, 3}, {IIC1_SCL, 4}, {CAM_MCLK1, 5}, FS_NONE, {DBG_10, 7}}, +/* PAD_MIPIRX0P */ {FS_NONE, {VI0_D_8, 1}, FS_NONE, {XGPIOC_11, 3}, {CAM_MCLK0, 4}, FS_NONE, FS_NONE, {DBG_11, 7}}, +/* PAD_MIPI_TXM2 */ {FS_NONE, {VI0_D_13, 1}, {IIC0_SDA, 2}, {XGPIOC_16, 3}, {IIC1_SDA, 4}, {PWM_8, 5}, {SPI0_SCK, 6}, FS_NONE}, +/* PAD_MIPI_TXP2 */ {FS_NONE, {VI0_D_14, 1}, {IIC0_SCL, 2}, {XGPIOC_17, 3}, {IIC1_SCL, 4}, {PWM_9, 5}, {SPI0_CS_X, 6}, {IIS1_MCLK, 7}}, +/* PAD_MIPI_TXM1 */ {{SPI3_SDO, 0}, {VI0_D_11, 1}, {IIS1_LRCK, 2}, {XGPIOC_14, 3}, {IIC2_SDA, 4}, {PWM_10, 5}, {SPI0_SDO, 6}, {DBG_14, 7}}, +/* PAD_MIPI_TXP1 */ {{SPI3_SDI, 0}, {VI0_D_12, 1}, {IIS1_DO, 2}, {XGPIOC_15, 3}, {IIC2_SCL, 4}, {PWM_11, 5}, {SPI0_SDI, 6}, {DBG_15, 7}}, +/* PAD_MIPI_TXM0 */ {{SPI3_SCK, 0}, {VI0_D_9, 1}, {IIS1_DI, 2}, {XGPIOC_12, 3}, {CAM_MCLK1, 4}, {PWM_14, 5}, {CAM_VS0, 6}, {DBG_12, 7}}, +/* PAD_MIPI_TXP0 */ {{SPI3_CS_X, 0}, {VI0_D_10, 1}, {IIS1_BCLK, 2}, {XGPIOC_13, 3}, {CAM_MCLK0, 4}, {PWM_15, 5}, {CAM_HS0, 6}, {DBG_13, 7}}, +/* PAD_AUD_AINL_MIC */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_23, 3}, {IIS1_BCLK, 4}, {IIS2_BCLK, 5}, FS_NONE, FS_NONE}, +/* PAD_AUD_AINR_MIC */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_22, 3}, {IIS1_DO, 4}, {IIS2_DI, 5}, {IIS1_DI, 6}, FS_NONE}, +/* PAD_AUD_AOUTL */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_25, 3}, {IIS1_LRCK, 4}, {IIS2_LRCK, 5}, FS_NONE, FS_NONE}, +/* PAD_AUD_AOUTR */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_24, 3}, {IIS1_DI, 4}, {IIS2_DO, 5}, {IIS1_DO, 6}, FS_NONE}, +}; + +#elif defined(SOC_TYPE_SG2002) + +struct fmux pinmux_array[] = { + FS_PINMUX(CAM_MCLK0), + FS_PINMUX(CAM_PD0), + FS_PINMUX(CAM_RST0), + FS_PINMUX(CAM_MCLK1), + FS_PINMUX(CAM_PD1), + FS_PINMUX(IIC3_SCL), + FS_PINMUX(IIC3_SDA), + FS_PINMUX(SD0_CLK), + FS_PINMUX(SD0_CMD), + FS_PINMUX(SD0_D0), + FS_PINMUX(SD0_D1), + FS_PINMUX(SD0_D2), + FS_PINMUX(SD0_D3), + FS_PINMUX(SD0_CD), + FS_PINMUX(SD0_PWR_EN), + FS_PINMUX(SPK_EN), + FS_PINMUX(UART0_TX), + FS_PINMUX(UART0_RX), + FS_PINMUX(EMMC_RSTN), + FS_PINMUX(EMMC_DAT2), + FS_PINMUX(EMMC_CLK), + FS_PINMUX(EMMC_DAT0), + FS_PINMUX(EMMC_DAT3), + FS_PINMUX(EMMC_CMD), + FS_PINMUX(EMMC_DAT1), + FS_PINMUX(JTAG_CPU_TMS), + FS_PINMUX(JTAG_CPU_TCK), + FS_PINMUX(JTAG_CPU_TRST), + FS_PINMUX(IIC0_SCL), + FS_PINMUX(IIC0_SDA), + FS_PINMUX(AUX0), + FS_PINMUX(PWR_VBAT_DET), + FS_PINMUX(PWR_RSTN), + FS_PINMUX(PWR_SEQ1), + FS_PINMUX(PWR_SEQ2), + FS_PINMUX(PWR_SEQ3), + FS_PINMUX(PWR_WAKEUP0), + FS_PINMUX(PWR_WAKEUP1), + FS_PINMUX(PWR_BUTTON1), + FS_PINMUX(PWR_ON), + FS_PINMUX(XTAL_XIN), + FS_PINMUX(PWR_GPIO0), + FS_PINMUX(PWR_GPIO1), + FS_PINMUX(PWR_GPIO2), + FS_PINMUX(CLK32K), + FS_PINMUX(CLK25M), + FS_PINMUX(IIC2_SCL), + FS_PINMUX(IIC2_SDA), + FS_PINMUX(UART2_TX), + FS_PINMUX(UART2_RTS), + FS_PINMUX(UART2_RX), + FS_PINMUX(UART2_CTS), + FS_PINMUX(SD1_D3), + FS_PINMUX(SD1_D2), + FS_PINMUX(SD1_D1), + FS_PINMUX(SD1_D0), + FS_PINMUX(SD1_CMD), + FS_PINMUX(SD1_CLK), + FS_PINMUX(RSTN), + FS_PINMUX(PWM0_BUCK), + FS_PINMUX(ADC3), + FS_PINMUX(ADC2), + FS_PINMUX(ADC1), + FS_PINMUX(USB_ID), + FS_PINMUX(USB_VBUS_EN), + FS_PINMUX(PKG_TYPE0), + FS_PINMUX(USB_VBUS_DET), + FS_PINMUX(PKG_TYPE1), + FS_PINMUX(PKG_TYPE2), + FS_PINMUX(MUX_SPI1_MISO), + FS_PINMUX(MUX_SPI1_MOSI), + FS_PINMUX(MUX_SPI1_CS), + FS_PINMUX(MUX_SPI1_SCK), + FS_PINMUX(PAD_ETH_TXM), + FS_PINMUX(PAD_ETH_TXP), + FS_PINMUX(PAD_ETH_RXM), + FS_PINMUX(PAD_ETH_RXP), + FS_PINMUX(VIVO_D10), + FS_PINMUX(VIVO_D9), + FS_PINMUX(VIVO_D8), + FS_PINMUX(VIVO_D7), + FS_PINMUX(VIVO_D6), + FS_PINMUX(VIVO_D5), + FS_PINMUX(VIVO_D4), + FS_PINMUX(VIVO_D3), + FS_PINMUX(VIVO_D2), + FS_PINMUX(VIVO_D1), + FS_PINMUX(VIVO_D0), + FS_PINMUX(VIVO_CLK), + FS_PINMUX(PAD_MIPIRX5N), + FS_PINMUX(PAD_MIPIRX5P), + FS_PINMUX(PAD_MIPIRX4N), + FS_PINMUX(PAD_MIPIRX4P), + FS_PINMUX(PAD_MIPIRX3N), + FS_PINMUX(PAD_MIPIRX3P), + FS_PINMUX(PAD_MIPIRX2N), + FS_PINMUX(PAD_MIPIRX2P), + FS_PINMUX(PAD_MIPIRX1N), + FS_PINMUX(PAD_MIPIRX1P), + FS_PINMUX(PAD_MIPIRX0N), + FS_PINMUX(PAD_MIPIRX0P), + FS_PINMUX(PAD_MIPI_TXM4), + FS_PINMUX(PAD_MIPI_TXP4), + FS_PINMUX(PAD_MIPI_TXM3), + FS_PINMUX(PAD_MIPI_TXP3), + FS_PINMUX(PAD_MIPI_TXM2), + FS_PINMUX(PAD_MIPI_TXP2), + FS_PINMUX(PAD_MIPI_TXM1), + FS_PINMUX(PAD_MIPI_TXP1), + FS_PINMUX(PAD_MIPI_TXM0), + FS_PINMUX(PAD_MIPI_TXP0), + FS_PINMUX(PAD_AUD_AINL_MIC), + FS_PINMUX(PAD_AUD_AINR_MIC), + FS_PINMUX(PAD_AUD_AOUTL), + FS_PINMUX(PAD_AUD_AOUTR), + FS_PINMUX(GPIO_RTX), + FS_PINMUX(GPIO_ZQ), +}; + +const struct fselect pin_selects_array[][8] = { +/* CAM_MCLK0 */ {{CAM_MCLK0, 0}, FS_NONE, {AUX1, 2}, {XGPIOA_0, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* CAM_PD0 */ {FS_NONE, {IIS1_MCLK, 1}, FS_NONE, {XGPIOA_1, 3}, {CAM_HS0, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* CAM_RST0 */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOA_2, 3}, {CAM_VS0, 4}, FS_NONE, {IIC4_SCL, 6}, FS_NONE}, +/* CAM_MCLK1 */ {{CAM_MCLK1, 0}, FS_NONE, {AUX2, 2}, {XGPIOA_3, 3}, {CAM_HS0, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* CAM_PD1 */ {FS_NONE, {IIS1_MCLK, 1}, FS_NONE, {XGPIOA_4, 3}, {CAM_VS0, 4}, FS_NONE, {IIC4_SDA, 6}, FS_NONE}, +/* IIC3_SCL */ {{IIC3_SCL, 0}, FS_NONE, FS_NONE, {XGPIOA_5, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* IIC3_SDA */ {{IIC3_SDA, 0}, FS_NONE, FS_NONE, {XGPIOA_6, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SD0_CLK */ {{SDIO0_CLK, 0}, {IIC1_SDA, 1}, {SPI0_SCK, 2}, {XGPIOA_7, 3}, FS_NONE, {PWM_15, 5}, {EPHY_LNK_LED, 6}, {DBG_0, 7}}, +/* SD0_CMD */ {{SDIO0_CMD, 0}, {IIC1_SCL, 1}, {SPI0_SDO, 2}, {XGPIOA_8, 3}, FS_NONE, {PWM_14, 5}, {EPHY_SPD_LED, 6}, {DBG_1, 7}}, +/* SD0_D0 */ {{SDIO0_D_0, 0}, {CAM_MCLK1, 1}, {SPI0_SDI, 2}, {XGPIOA_9, 3}, {UART3_TX, 4}, {PWM_13, 5}, {WG0_D0, 6}, {DBG_2, 7}}, +/* SD0_D1 */ {{SDIO0_D_1, 0}, {IIC1_SDA, 1}, {AUX0, 2}, {XGPIOA_10, 3}, {UART1_TX, 4}, {PWM_12, 5}, {WG0_D1, 6}, {DBG_3, 7}}, +/* SD0_D2 */ {{SDIO0_D_2, 0}, {IIC1_SCL, 1}, {AUX1, 2}, {XGPIOA_11, 3}, {UART1_RX, 4}, {PWM_11, 5}, {WG1_D0, 6}, {DBG_4, 7}}, +/* SD0_D3 */ {{SDIO0_D_3, 0}, {CAM_MCLK0, 1}, {SPI0_CS_X, 2}, {XGPIOA_12, 3}, {UART3_RX, 4}, {PWM_10, 5}, {WG1_D1, 6}, {DBG_5, 7}}, +/* SD0_CD */ {{SDIO0_CD, 0}, FS_NONE, FS_NONE, {XGPIOA_13, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SD0_PWR_EN */ {{SDIO0_PWR_EN, 0}, FS_NONE, FS_NONE, {XGPIOA_14, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* SPK_EN */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOA_15, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* UART0_TX */ {{UART0_TX, 0}, {CAM_MCLK1, 1}, {PWM_4, 2}, {XGPIOA_16, 3}, {UART1_TX, 4}, {AUX1, 5}, {JTAG_TMS, 6}, {DBG_6, 7}}, +/* UART0_RX */ {{UART0_RX, 0}, {CAM_MCLK0, 1}, {PWM_5, 2}, {XGPIOA_17, 3}, {UART1_RX, 4}, {AUX0, 5}, FS_NONE, {DBG_7, 7}}, +/* EMMC_RSTN */ {{EMMC_RSTN, 0}, FS_NONE, FS_NONE, {XGPIOA_21, 3}, {AUX2, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_DAT2 */ {{EMMC_DAT_2, 0}, {SPINOR_HOLD_X, 1}, {SPINAND_HOLD, 2}, {XGPIOA_26, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_CLK */ {{EMMC_CLK, 0}, {SPINOR_SCK, 1}, {SPINAND_CLK, 2}, {XGPIOA_22, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_DAT0 */ {{EMMC_DAT_0, 0}, {SPINOR_MOSI, 1}, {SPINAND_MOSI, 2}, {XGPIOA_25, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_DAT3 */ {{EMMC_DAT_3, 0}, {SPINOR_WP_X, 1}, {SPINAND_WP, 2}, {XGPIOA_27, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_CMD */ {{EMMC_CMD, 0}, {SPINOR_MISO, 1}, {SPINAND_MISO, 2}, {XGPIOA_23, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* EMMC_DAT1 */ {{EMMC_DAT_1, 0}, {SPINOR_CS_X, 1}, {SPINAND_CS, 2}, {XGPIOA_24, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* JTAG_CPU_TMS */ {{JTAG_CPU_TMS, 0}, {CAM_MCLK0, 1}, {PWM_7, 2}, {XGPIOA_19, 3}, {UART1_RTS, 4}, {AUX0, 5}, {UART1_TX, 6}, {VO_D_28, 7}}, +/* JTAG_CPU_TCK */ {{JTAG_CPU_TCK, 0}, {CAM_MCLK1, 1}, {PWM_6, 2}, {XGPIOA_18, 3}, {UART1_CTS, 4}, {AUX1, 5}, {UART1_RX, 6}, {VO_D_29, 7}}, +/* JTAG_CPU_TRST */ {{JTAG_CPU_TRST, 0}, FS_NONE, FS_NONE, {XGPIOA_20, 3}, FS_NONE, FS_NONE, {VO_D_30, 6}, FS_NONE}, +/* IIC0_SCL */ {{IIC0_SCL, 0}, {UART1_TX, 1}, {UART2_TX, 2}, {XGPIOA_28, 3}, FS_NONE, {WG0_D0, 5}, FS_NONE, {DBG_10, 7}}, +/* IIC0_SDA */ {{IIC0_SDA, 0}, {UART1_RX, 1}, {UART2_RX, 2}, {XGPIOA_29, 3}, FS_NONE, {WG0_D1, 5}, {WG1_D0, 6}, {DBG_11, 7}}, +/* AUX0 */ {{AUX0, 0}, FS_NONE, FS_NONE, {XGPIOA_30, 3}, {IIS1_MCLK, 4}, {VO_D_31, 5}, {WG1_D1, 6}, {DBG_12, 7}}, +/* PWR_VBAT_DET */ {{PWR_VBAT_DET, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_RSTN */ {{PWR_RSTN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ1 */ {{PWR_SEQ1, 0}, FS_NONE, {PWR_GPIO_3, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ2 */ {{PWR_SEQ2, 0}, FS_NONE, {PWR_GPIO_4, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_SEQ3 */ {{PWR_SEQ3, 0}, FS_NONE, {PWR_GPIO_5, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_WAKEUP0 */ {{PWR_WAKEUP0, 0}, {PWR_IR0, 1}, {PWR_UART0_TX, 2}, {PWR_GPIO_6, 3}, {UART1_TX, 4}, {IIC4_SCL, 5}, {EPHY_LNK_LED, 6}, {WG2_D0, 7}}, +/* PWR_WAKEUP1 */ {{PWR_WAKEUP1, 0}, {PWR_IR1, 1}, FS_NONE, {PWR_GPIO_7, 3}, {UART1_TX, 4}, {IIC4_SCL, 5}, {EPHY_LNK_LED, 6}, {WG0_D0, 7}}, +/* PWR_BUTTON1 */ {{PWR_BUTTON1, 0}, FS_NONE, FS_NONE, {PWR_GPIO_8, 3}, {UART1_RX, 4}, {IIC4_SDA, 5}, {EPHY_SPD_LED, 6}, {WG2_D1, 7}}, +/* PWR_ON */ {{PWR_ON, 0}, FS_NONE, FS_NONE, {PWR_GPIO_9, 3}, {UART1_RX, 4}, {IIC4_SDA, 5}, {EPHY_SPD_LED, 6}, {WG0_D1, 7}}, +/* XTAL_XIN */ {{PWR_XTAL_CLKIN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_GPIO0 */ {{PWR_GPIO_0, 0}, {UART2_TX, 1}, {PWR_UART0_RX, 2}, FS_NONE, {PWM_8, 4}, FS_NONE, FS_NONE, FS_NONE}, +/* PWR_GPIO1 */ {{PWR_GPIO_1, 0}, {UART2_RX, 1}, FS_NONE, {EPHY_LNK_LED, 3}, {PWM_9, 4}, {PWR_IIC_SCL, 5}, {IIC2_SCL, 6}, {PWR_MCU_JTAG_TMS, 7}}, +/* PWR_GPIO2 */ {{PWR_GPIO_2, 0}, FS_NONE, {PWR_SECTICK, 2}, {EPHY_SPD_LED, 3}, {PWM_10, 4}, {PWR_IIC_SDA, 5}, {IIC2_SDA, 6}, {PWR_MCU_JTAG_TCK, 7}}, +/* CLK32K */ {{CLK32K, 0}, {AUX0, 1}, {PWR_MCU_JTAG_TDI, 2}, {PWR_GPIO_10, 3}, {PWM_2, 4}, {KEY_COL0, 5}, {CAM_MCLK0, 6}, {DBG_0, 7}}, +/* CLK25M */ {{CLK25M, 0}, {AUX1, 1}, {PWR_MCU_JTAG_TDO, 2}, {PWR_GPIO_11, 3}, {PWM_3, 4}, {KEY_COL1, 5}, {CAM_MCLK1, 6}, {DBG_1, 7}}, +/* IIC2_SCL */ {{IIC2_SCL, 0}, {PWM_14, 1}, FS_NONE, {PWR_GPIO_12, 3}, {UART2_RX, 4}, FS_NONE, FS_NONE, {KEY_COL2, 7}}, +/* IIC2_SDA */ {{IIC2_SDA, 0}, {PWM_15, 1}, FS_NONE, {PWR_GPIO_13, 3}, {UART2_TX, 4}, {IIS1_MCLK, 5}, {IIS2_MCLK, 6}, {KEY_COL3, 7}}, +/* UART2_TX */ {{UART2_TX, 0}, {PWM_11, 1}, {PWR_UART1_TX, 2}, {PWR_GPIO_14, 3}, {KEY_ROW3, 4}, {UART4_TX, 5}, {IIS2_BCLK, 6}, {WG2_D0, 7}}, +/* UART2_RTS */ {{UART2_RTS, 0}, {PWM_8, 1}, FS_NONE, {PWR_GPIO_15, 3}, {KEY_ROW0, 4}, {UART4_RTS, 5}, {IIS2_DO, 6}, {WG1_D0, 7}}, +/* UART2_RX */ {{UART2_RX, 0}, {PWM_10, 1}, {PWR_UART1_RX, 2}, {PWR_GPIO_16, 3}, {KEY_COL3, 4}, {UART4_RX, 5}, {IIS2_DI, 6}, {WG2_D1, 7}}, +/* UART2_CTS */ {{UART2_CTS, 0}, {PWM_9, 1}, FS_NONE, {PWR_GPIO_17, 3}, {KEY_ROW1, 4}, {UART4_CTS, 5}, {IIS2_LRCK, 6}, {WG1_D1, 7}}, +/* SD1_D3 */ {{PWR_SD1_D3_VO32, 0}, {SPI2_CS_X, 1}, {IIC1_SCL, 2}, {PWR_GPIO_18, 3}, {CAM_MCLK0, 4}, {UART3_CTS, 5}, {PWR_SPINOR1_CS_X, 6}, {PWM_4, 7}}, +/* SD1_D2 */ {{PWR_SD1_D2_VO33, 0}, {IIC1_SCL, 1}, {UART2_TX, 2}, {PWR_GPIO_19, 3}, {CAM_MCLK0, 4}, {UART3_TX, 5}, {PWR_SPINOR1_HOLD_X, 6},{PWM_5, 7}}, +/* SD1_D1 */ {{PWR_SD1_D1_VO34, 0}, {IIC1_SDA, 1}, {UART2_RX, 2}, {PWR_GPIO_20, 3}, {CAM_MCLK1, 4}, {UART3_RX, 5}, {PWR_SPINOR1_WP_X, 6}, {PWM_6, 7}}, +/* SD1_D0 */ {{PWR_SD1_D0_VO35, 0}, {SPI2_SDI, 1}, {IIC1_SDA, 2}, {PWR_GPIO_21, 3}, {CAM_MCLK1, 4}, {UART3_RTS, 5}, {PWR_SPINOR1_MISO, 6}, {PWM_7, 7}}, +/* SD1_CMD */ {{PWR_SD1_CMD_VO36, 0}, {SPI2_SDO, 1}, {IIC3_SCL, 2}, {PWR_GPIO_22, 3}, {CAM_VS0, 4}, {EPHY_LNK_LED, 5}, {PWR_SPINOR1_MOSI, 6}, {PWM_8, 7}}, +/* SD1_CLK */ {{PWR_SD1_CLK_VO37, 0}, {SPI2_SCK, 1}, {IIC3_SDA, 2}, {PWR_GPIO_23, 3}, {CAM_HS0, 4}, {EPHY_SPD_LED, 5}, {PWR_SPINOR1_SCK, 6}, {PWM_9, 7}}, +/* RSTN */ {{RSTN, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PWM0_BUCK */ {{PWM_0, 0}, FS_NONE, FS_NONE, {XGPIOB_0, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* ADC3 */ {FS_NONE, {CAM_MCLK0, 1}, {IIC4_SCL, 2}, {XGPIOB_1, 3}, {PWM_12, 4}, {EPHY_LNK_LED, 5}, {WG2_D0, 6}, {UART3_TX, 7}}, +/* ADC2 */ {FS_NONE, {CAM_MCLK1, 1}, {IIC4_SDA, 2}, {XGPIOB_2, 3}, {PWM_13, 4}, {EPHY_SPD_LED, 5}, {WG2_D1, 6}, {UART3_RX, 7}}, +/* ADC1 */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOB_3, 3}, {KEY_COL2, 4}, FS_NONE, {PWM_3, 6}, FS_NONE}, +/* USB_ID */ {{USB_ID, 0}, FS_NONE, FS_NONE, {XGPIOB_4, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* USB_VBUS_EN */ {{USB_VBUS_EN, 0}, FS_NONE, FS_NONE, {XGPIOB_5, 3}, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PKG_TYPE0 */ {{PKG_TYPE0, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* USB_VBUS_DET */ {{USB_VBUS_DET, 0}, FS_NONE, FS_NONE, {XGPIOB_6, 3}, {CAM_MCLK0, 4}, {CAM_MCLK1, 5}, FS_NONE, FS_NONE}, +/* PKG_TYPE1 */ {{PKG_TYPE1, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* PKG_TYPE2 */ {{PKG_TYPE2, 0}, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE, FS_NONE}, +/* MUX_SPI1_MISO */ {FS_NONE, {UART3_RTS, 1}, {IIC1_SDA, 2}, {XGPIOB_8, 3}, {PWM_9, 4}, {KEY_COL1, 5}, {SPI1_SDI, 6}, {DBG_14, 7}}, +/* MUX_SPI1_MOSI */ {FS_NONE, {UART3_RX, 1}, {IIC1_SCL, 2}, {XGPIOB_7, 3}, {PWM_8, 4}, {KEY_COL0, 5}, {SPI1_SDO, 6}, {DBG_13, 7}}, +/* MUX_SPI1_CS */ {FS_NONE, {UART3_CTS, 1}, {CAM_MCLK0, 2}, {XGPIOB_10, 3}, {PWM_11, 4}, {KEY_ROW3, 5}, {SPI1_CS_X, 6}, {DBG_16, 7}}, +/* MUX_SPI1_SCK */ {FS_NONE, {UART3_TX, 1}, {CAM_MCLK1, 2}, {XGPIOB_9, 3}, {PWM_10, 4}, {KEY_ROW2, 5}, {SPI1_SCK, 6}, {DBG_15, 7}}, +/* PAD_ETH_TXM */ {FS_NONE, {UART3_RTS, 1}, {IIC1_SDA, 2}, {XGPIOB_24, 3}, {PWM_12, 4}, {CAM_MCLK1, 5}, {SPI1_SDI, 6}, {IIS2_BCLK, 7}}, +/* PAD_ETH_TXP */ {FS_NONE, {UART3_RX, 1}, {IIC1_SCL, 2}, {XGPIOB_25, 3}, {PWM_13, 4}, {CAM_MCLK0, 5}, {SPI1_SDO, 6}, {IIS2_LRCK, 7}}, +/* PAD_ETH_RXM */ {FS_NONE, {UART3_CTS, 1}, {CAM_MCLK0, 2}, {XGPIOB_26, 3}, {PWM_14, 4}, {CAM_VS0, 5}, {SPI1_CS_X, 6}, {IIS2_DI, 7}}, +/* PAD_ETH_RXP */ {FS_NONE, {UART3_TX, 1}, {CAM_MCLK1, 2}, {XGPIOB_27, 3}, {PWM_15, 4}, {CAM_HS0, 5}, {SPI1_SCK, 6}, {IIS2_DO, 7}}, +/* VIVO_D10 */ {{PWM_1, 0}, {VI1_D_10, 1}, {VO_D_23, 2}, {XGPIOB_11, 3}, {RMII0_IRQ, 4}, {CAM_MCLK0, 5}, {IIC1_SDA, 6}, {UART2_TX, 7}}, +/* VIVO_D9 */ {{PWM_2, 0}, {VI1_D_9, 1}, {VO_D_22, 2}, {XGPIOB_12, 3}, FS_NONE, {CAM_MCLK1, 5}, {IIC1_SCL, 6}, {UART2_RX, 7}}, +/* VIVO_D8 */ {{PWM_3, 0}, {VI1_D_8, 1}, {VO_D_21, 2}, {XGPIOB_13, 3}, {RMII0_MDIO, 4}, {SPI3_SDO, 5}, {IIC2_SCL, 6}, {CAM_VS0, 7}}, +/* VIVO_D7 */ {{VI2_D_7, 0}, {VI1_D_7, 1}, {VO_D_20, 2}, {XGPIOB_14, 3}, {RMII0_RXD1, 4}, {SPI3_SDI, 5}, {IIC2_SDA, 6}, {CAM_HS0, 7}}, +/* VIVO_D6 */ {{VI2_D_6, 0}, {VI1_D_6, 1}, {VO_D_19, 2}, {XGPIOB_15, 3}, {RMII0_REFCLKI, 4},{SPI3_SCK, 5}, {UART2_TX, 6}, {CAM_VS0, 7}}, +/* VIVO_D5 */ {{VI2_D_5, 0}, {VI1_D_5, 1}, {VO_D_18, 2}, {XGPIOB_16, 3}, {RMII0_RXD0, 4}, {SPI3_CS_X, 5}, {UART2_RX, 6}, {CAM_HS0, 7}}, +/* VIVO_D4 */ {{VI2_D_4, 0}, {VI1_D_4, 1}, {VO_D_17, 2}, {XGPIOB_17, 3}, {RMII0_MDC, 4}, {IIC1_SDA, 5}, {UART2_CTS, 6}, {CAM_VS0, 7}}, +/* VIVO_D3 */ {{VI2_D_3, 0}, {VI1_D_3, 1}, {VO_D_16, 2}, {XGPIOB_18, 3}, {RMII0_TXD0, 4}, {IIC1_SCL, 5}, {UART2_RTS, 6}, {CAM_HS0, 7}}, +/* VIVO_D2 */ {{VI2_D_2, 0}, {VI1_D_2, 1}, {VO_D_15, 2}, {XGPIOB_19, 3}, {RMII0_TXD1, 4}, {CAM_MCLK1, 5}, {PWM_2, 6}, {UART2_TX, 7}}, +/* VIVO_D1 */ {{VI2_D_1, 0}, {VI1_D_1, 1}, {VO_D_14, 2}, {XGPIOB_20, 3}, {RMII0_RXDV, 4}, {IIC3_SDA, 5}, {PWM_3, 6}, {IIC4_SCL, 7}}, +/* VIVO_D0 */ {{VI2_D_0, 0}, {VI1_D_0, 1}, {VO_D_13, 2}, {XGPIOB_21, 3}, {RMII0_TXCLK, 4}, {IIC3_SCL, 5}, {WG1_D0, 6}, {IIC4_SDA, 7}}, +/* VIVO_CLK */ {{VI2_CLK, 0}, {VI1_CLK, 1}, {VO_CLK1, 2}, {XGPIOB_22, 3}, {RMII0_TXEN, 4}, {CAM_MCLK0, 5}, {WG1_D1, 6}, {UART2_RX, 7}}, +/* PAD_MIPIRX5N */ {FS_NONE, {VI1_D_11, 1}, {VO_D_12, 2}, {XGPIOC_0, 3}, FS_NONE, {CAM_MCLK0, 5}, {WG0_D0, 6}, {DBG_0, 7}}, +/* PAD_MIPIRX5P */ {FS_NONE, {VI1_D_12, 1}, {VO_D_11, 2}, {XGPIOC_1, 3}, {IIS1_MCLK, 4}, {CAM_MCLK1, 5}, {WG0_D1, 6}, {DBG_1, 7}}, +/* PAD_MIPIRX4N */ {FS_NONE, {VI0_CLK, 1}, {VI1_D_13, 2}, {XGPIOC_2, 3}, {IIC1_SDA, 4}, {CAM_MCLK0, 5}, {KEY_ROW0, 6}, {MUX_SPI1_SCK, 7}}, +/* PAD_MIPIRX4P */ {FS_NONE, {VI0_D_0, 1}, {VI1_D_14, 2}, {XGPIOC_3, 3}, {IIC1_SCL, 4}, {CAM_MCLK1, 5}, {KEY_ROW1, 6}, {MUX_SPI1_CS, 7}}, +/* PAD_MIPIRX3N */ {FS_NONE, {VI0_D_1, 1}, {VI1_D_15, 2}, {XGPIOC_4, 3}, {CAM_MCLK0, 4}, FS_NONE, FS_NONE, {MUX_SPI1_MISO, 7}}, +/* PAD_MIPIRX3P */ {FS_NONE, {VI0_D_2, 1}, {VI1_D_16, 2}, {XGPIOC_5, 3}, FS_NONE, FS_NONE, FS_NONE, {MUX_SPI1_MOSI, 7}}, +/* PAD_MIPIRX2N */ {FS_NONE, {VI0_D_3, 1}, {VO_D_10, 2}, {XGPIOC_6, 3}, {VI1_D_17, 4}, {IIC4_SCL, 5}, FS_NONE, {DBG_6, 7}}, +/* PAD_MIPIRX2P */ {FS_NONE, {VI0_D_4, 1}, {VO_D_9, 2}, {XGPIOC_7, 3}, {VI1_D_18, 4}, {IIC4_SDA, 5}, FS_NONE, {DBG_7, 7}}, +/* PAD_MIPIRX1N */ {FS_NONE, {VI0_D_5, 1}, {VO_D_8, 2}, {XGPIOC_8, 3}, FS_NONE, FS_NONE, {KEY_ROW3, 6}, {DBG_8, 7}}, +/* PAD_MIPIRX1P */ {FS_NONE, {VI0_D_6, 1}, {VO_D_7, 2}, {XGPIOC_9, 3}, {IIC1_SDA, 4}, FS_NONE, {KEY_ROW2, 6}, {DBG_9, 7}}, +/* PAD_MIPIRX0N */ {FS_NONE, {VI0_D_7, 1}, {VO_D_6, 2}, {XGPIOC_10, 3}, {IIC1_SCL, 4}, {CAM_MCLK1, 5}, FS_NONE, {DBG_10, 7}}, +/* PAD_MIPIRX0P */ {FS_NONE, {VI0_D_8, 1}, {VO_D_5, 2}, {XGPIOC_11, 3}, {CAM_MCLK0, 4}, FS_NONE, FS_NONE, {DBG_11, 7}}, +/* PAD_MIPI_TXM4 */ {FS_NONE, {SD1_CLK, 1}, {VO_D_24, 2}, {XGPIOC_18, 3}, {CAM_MCLK1, 4}, {PWM_12, 5}, {IIC1_SDA, 6}, {DBG_18, 7}}, +/* PAD_MIPI_TXP4 */ {FS_NONE, {SD1_CMD, 1}, {VO_D_25, 2}, {XGPIOC_19, 3}, {CAM_MCLK0, 4}, {PWM_13, 5}, {IIC1_SCL, 6}, {DBG_19, 7}}, +/* PAD_MIPI_TXM3 */ {FS_NONE, {SD1_D0, 1}, {VO_D_26, 2}, {XGPIOC_20, 3}, {IIC2_SDA, 4}, {PWM_14, 5}, {IIC1_SDA, 6}, {CAM_VS0, 7}}, +/* PAD_MIPI_TXP3 */ {FS_NONE, {SD1_D1, 1}, {VO_D_27, 2}, {XGPIOC_21, 3}, {IIC2_SCL, 4}, {PWM_15, 5}, {IIC1_SCL, 6}, {CAM_HS0, 7}}, +/* PAD_MIPI_TXM2 */ {FS_NONE, {VI0_D_13, 1}, {VO_D_0, 2}, {XGPIOC_16, 3}, {IIC1_SDA, 4}, {PWM_8, 5}, {SPI0_SCK, 6}, {SD1_D2, 7}}, +/* PAD_MIPI_TXP2 */ {FS_NONE, {VI0_D_14, 1}, {VO_CLK0, 2}, {XGPIOC_17, 3}, {IIC1_SCL, 4}, {PWM_9, 5}, {SPI0_CS_X, 6}, {SD1_D3, 7}}, +/* PAD_MIPI_TXM1 */ {FS_NONE, {VI0_D_11, 1}, {VO_D_2, 2}, {XGPIOC_14, 3}, {IIC2_SDA, 4}, {PWM_10, 5}, {SPI0_SDO, 6}, {DBG_14, 7}}, +/* PAD_MIPI_TXP1 */ {FS_NONE, {VI0_D_12, 1}, {VO_D_1, 2}, {XGPIOC_15, 3}, {IIC2_SCL, 4}, {PWM_11, 5}, {SPI0_SDI, 6}, {DBG_15, 7}}, +/* PAD_MIPI_TXM0 */ {FS_NONE, {VI0_D_9, 1}, {VO_D_4, 2}, {XGPIOC_12, 3}, {CAM_MCLK1, 4}, {PWM_14, 5}, {CAM_VS0, 6}, {DBG_12, 7}}, +/* PAD_MIPI_TXP0 */ {FS_NONE, {VI0_D_10, 1}, {VO_D_3, 2}, {XGPIOC_13, 3}, {CAM_MCLK0, 4}, {PWM_15, 5}, {CAM_HS0, 6}, {DBG_13, 7}}, +/* PAD_AUD_AINL_MIC */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_23, 3}, {IIS1_BCLK, 4}, {IIS2_BCLK, 5}, FS_NONE, FS_NONE}, +/* PAD_AUD_AINR_MIC */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_22, 3}, {IIS1_DO, 4}, {IIS2_DI, 5}, {IIS1_DI, 6}, FS_NONE}, +/* PAD_AUD_AOUTL */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_25, 3}, {IIS1_LRCK, 4}, {IIS2_LRCK, 5}, FS_NONE, FS_NONE}, +/* PAD_AUD_AOUTR */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOC_24, 3}, {IIS1_DI, 4}, {IIS2_DO, 5}, {IIS1_DO, 6}, FS_NONE}, +/* GPIO_RTX */ {FS_NONE, FS_NONE, FS_NONE, {XGPIOB_23, 3}, {PWM_1, 4}, {CAM_MCLK0, 5}, FS_NONE, FS_NONE}, +/* GPIO_ZQ */ {FS_NONE, FS_NONE, FS_NONE, {PWR_GPIO_24, 3}, {PWM_2, 4}, FS_NONE, FS_NONE, FS_NONE}, +}; + +#else + +#error "Unsupported SOC type!" + +#endif + +static int8_t pinmux_get_index(uint8_t pin_index, fs_type func_type) +{ + const struct fselect *p; + for (int i = 0; i < 8; i++) { + p = &(pin_selects_array[pin_index][i]); + LOG_D("[%d], type = %d, select = %d\n", i, p->type, p->select); + if (p->type == func_type) + return (int8_t)p->select; // it's safe bcos select should be [0, 7] + } + return -1; +} + +static int pinmux_check_whitelist(const char *pin_name, const char *whitelist[]) +{ + const char **name = &whitelist[0]; + while (*name) { + if (0 == strcmp(pin_name, *name)) + return 0; + name++; + } + return -1; +} + +int pinmux_config(const char *pin_name, fs_type func_type, const char *whitelist[]) +{ + const struct fmux *p_fmux; + int index; + int8_t select; + + if (whitelist) { + if (0 != pinmux_check_whitelist(pin_name, whitelist)) { + LOG_W("Pin Name \"%s\" is NOT Allowed by Whitelist!", pin_name); + return -RT_ERROR; + } + } + + for (index = 0; index < ARRAY_SIZE(pinmux_array); index++) { + p_fmux = &(pinmux_array[index]); + LOG_D("index[%d]: name: %s, addr: %d, offset: %d, mask: %d\n", + index, p_fmux->name, p_fmux->addr, p_fmux->offset, p_fmux->mask); + if (0 == strcmp(pin_name, p_fmux->name)) { + break; + } + } + if (index == ARRAY_SIZE(pinmux_array)) { + LOG_W("Pin Name \"%s\" is not found!", pin_name); + return -RT_ERROR;; + } + if (p_fmux->selected) { + LOG_W("Pin Name \"%s\" has been selected, duplicated?", pin_name); + return -RT_ERROR; + } + + select = pinmux_get_index(index, func_type); + if (-1 == select) { + LOG_W("Can not found Function selection for Pin \"%s\"", pin_name); + return -RT_ERROR; + } + + LOG_I("Pin Name = \"%s\", Func Type = %d, selected Func [%d]\n", pin_name, func_type, select); + pinmux_array[index].selected = 1; + mmio_clrsetbits_32(PINMUX_BASE + p_fmux->addr, p_fmux->mask << p_fmux->offset, select); + return RT_EOK; +} diff --git a/bsp/cvitek/drivers/drv_pinmux.h b/bsp/cvitek/drivers/drv_pinmux.h new file mode 100644 index 0000000000..56f228d265 --- /dev/null +++ b/bsp/cvitek/drivers/drv_pinmux.h @@ -0,0 +1,448 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/05/24 unicornx first version + */ +#ifndef __DRV_PINMUX_H__ +#define __DRV_PINMUX_H__ + +/** + * @brief Function Selection Type + * + * FIXME: At present, we only define the ones we will use, + * not all of them. We will need to add them later. + */ +typedef enum _fs_type +{ + fs_none = 0, + AUX0, + AUX1, + AUX2, + CAM_HS0, + CAM_MCLK0, + CAM_MCLK1, + CAM_VS0, + CLK25M, + CLK32K, + DBG_0, + DBG_1, + DBG_2, + DBG_3, + DBG_4, + DBG_5, + DBG_6, + DBG_7, + DBG_8, + DBG_9, + DBG_10, + DBG_11, + DBG_12, + DBG_13, + DBG_14, + DBG_15, + DBG_16, + DBG_18, + DBG_19, + EMMC_CLK, + EMMC_CMD, + EMMC_DAT_0, + EMMC_DAT_1, + EMMC_DAT_2, + EMMC_DAT_3, + EMMC_RSTN, + EPHY_LNK_LED, + EPHY_SPD_LED, + IIC0_SCL, + IIC0_SDA, + IIC1_SCL, + IIC1_SDA, + IIC2_SCL, + IIC2_SDA, + IIC3_SCL, + IIC3_SDA, + IIC4_SCL, + IIC4_SDA, + IIS1_BCLK, + IIS1_DI, + IIS1_DO, + IIS1_LRCK, + IIS1_MCLK, + IIS2_BCLK, + IIS2_DI, + IIS2_DO, + IIS2_LRCK, + IIS2_MCLK, + JTAG_TCK, + JTAG_TDI, + JTAG_TDO, + JTAG_TMS, + JTAG_CPU_TCK, + JTAG_CPU_TMS, + JTAG_CPU_TRST, + KEY_COL0, + KEY_COL1, + KEY_COL2, + KEY_COL3, + KEY_ROW0, + KEY_ROW1, + KEY_ROW2, + KEY_ROW3, + MUX_SPI1_CS, + MUX_SPI1_MISO, + MUX_SPI1_MOSI, + MUX_SPI1_SCK, + PKG_TYPE0, + PKG_TYPE1, + PKG_TYPE2, + PWM_0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11, + PWM_12, + PWM_13, + PWM_14, + PWM_15, + PWR_BUTTON1, + PWR_GPIO_0, + PWR_GPIO_1, + PWR_GPIO_2, + PWR_GPIO_3, + PWR_GPIO_4, + PWR_GPIO_5, + PWR_GPIO_6, + PWR_GPIO_7, + PWR_GPIO_8, + PWR_GPIO_9, + PWR_GPIO_10, + PWR_GPIO_11, + PWR_GPIO_12, + PWR_GPIO_13, + PWR_GPIO_14, + PWR_GPIO_15, + PWR_GPIO_16, + PWR_GPIO_17, + PWR_GPIO_18, + PWR_GPIO_19, + PWR_GPIO_20, + PWR_GPIO_21, + PWR_GPIO_22, + PWR_GPIO_23, + PWR_GPIO_24, + PWR_GPIO_25, + PWR_GPIO_26, + PWR_IIC_SCL, + PWR_IIC_SDA, + PWR_IR0, + PWR_IR1, + PWR_MCU_JTAG_TCK, + PWR_MCU_JTAG_TDI, + PWR_MCU_JTAG_TDO, + PWR_MCU_JTAG_TMS, + PWR_ON, + PWR_PTEST, + PWR_RSTN, + PWR_SD1_CLK_VO37, + PWR_SD1_CMD_VO36, + PWR_SD1_D0_VO35, + PWR_SD1_D1_VO34, + PWR_SD1_D2_VO33, + PWR_SD1_D3_VO32, + PWR_SD1_CLK, + PWR_SD1_CMD, + PWR_SD1_D0, + PWR_SD1_D1, + PWR_SD1_D2, + PWR_SD1_D3, + PWR_SECTICK, + PWR_SEQ1, + PWR_SEQ2, + PWR_SEQ3, + PWR_SPINOR1_CS_X, + PWR_SPINOR1_HOLD_X, + PWR_SPINOR1_MISO, + PWR_SPINOR1_MOSI, + PWR_SPINOR1_SCK, + PWR_SPINOR1_WP_X, + PWR_UART0_RX, + PWR_UART0_TX, + PWR_UART1_RX, + PWR_UART1_TX, + PWR_VBAT_DET, + PWR_WAKEUP0, + PWR_WAKEUP1, + PWR_XTAL_CLKIN, + RMII0_IRQ, + RMII0_MDC, + RMII0_MDIO, + RMII0_REFCLKI, + RMII0_RXD0, + RMII0_RXD1, + RMII0_RXDV, + RMII0_TXCLK, + RMII0_TXD0, + RMII0_TXD1, + RMII0_TXEN, + RSTN, + SD1_CLK, + SD1_CMD, + SD1_D0, + SD1_D1, + SD1_D2, + SD1_D3, + SDIO0_CD, + SDIO0_CLK, + SDIO0_CMD, + SDIO0_D_0, + SDIO0_D_1, + SDIO0_D_2, + SDIO0_D_3, + SDIO0_PWR_EN, + SPI0_CS_X, + SPI0_SCK, + SPI0_SDI, + SPI0_SDO, + SPI1_CS_X, + SPI1_SCK, + SPI1_SDI, + SPI1_SDO, + SPI2_CS_X, + SPI2_SCK, + SPI2_SDI, + SPI2_SDO, + SPI3_CS_X, + SPI3_SCK, + SPI3_SDI, + SPI3_SDO, + SPINAND_CLK, + SPINAND_CS, + SPINAND_HOLD, + SPINAND_MISO, + SPINAND_MOSI, + SPINAND_WP, + SPINOR_CS_X, + SPINOR_HOLD_X, + SPINOR_MISO, + SPINOR_MOSI, + SPINOR_SCK, + SPINOR_WP_X, + UART0_RX, + UART0_TX, + UART1_CTS, + UART1_RTS, + UART1_RX, + UART1_TX, + UART2_CTS, + UART2_RTS, + UART2_RX, + UART2_TX, + UART3_CTS, + UART3_RTS, + UART3_RX, + UART3_TX, + UART4_CTS, + UART4_RTS, + UART4_RX, + UART4_TX, + USB_ID, + USB_VBUS_DET, + USB_VBUS_EN, + VI0_CLK, + VI0_D_0, + VI0_D_1, + VI0_D_2, + VI0_D_3, + VI0_D_4, + VI0_D_5, + VI0_D_6, + VI0_D_7, + VI0_D_8, + VI0_D_9, + VI0_D_10, + VI0_D_11, + VI0_D_12, + VI0_D_13, + VI0_D_14, + VI0_D_15, + VI1_CLK, + VI1_D_0, + VI1_D_1, + VI1_D_2, + VI1_D_3, + VI1_D_4, + VI1_D_5, + VI1_D_6, + VI1_D_7, + VI1_D_8, + VI1_D_9, + VI1_D_10, + VI1_D_11, + VI1_D_12, + VI1_D_13, + VI1_D_14, + VI1_D_15, + VI1_D_16, + VI1_D_17, + VI1_D_18, + VI2_CLK, + VI2_D_0, + VI2_D_1, + VI2_D_2, + VI2_D_3, + VI2_D_4, + VI2_D_5, + VI2_D_6, + VI2_D_7, + VO_CLK0, + VO_CLK1, + VO_D_0, + VO_D_1, + VO_D_2, + VO_D_3, + VO_D_4, + VO_D_5, + VO_D_6, + VO_D_7, + VO_D_8, + VO_D_9, + VO_D_10, + VO_D_11, + VO_D_12, + VO_D_13, + VO_D_14, + VO_D_15, + VO_D_16, + VO_D_17, + VO_D_18, + VO_D_19, + VO_D_20, + VO_D_21, + VO_D_22, + VO_D_23, + VO_D_24, + VO_D_25, + VO_D_26, + VO_D_27, + VO_D_28, + VO_D_29, + VO_D_30, + VO_D_31, + WG0_D0, + WG0_D1, + WG1_D0, + WG1_D1, + WG2_D0, + WG2_D1, + XGPIOA_0, + XGPIOA_1, + XGPIOA_2, + XGPIOA_3, + XGPIOA_4, + XGPIOA_5, + XGPIOA_6, + XGPIOA_7, + XGPIOA_8, + XGPIOA_9, + XGPIOA_10, + XGPIOA_11, + XGPIOA_12, + XGPIOA_13, + XGPIOA_14, + XGPIOA_15, + XGPIOA_16, + XGPIOA_17, + XGPIOA_18, + XGPIOA_19, + XGPIOA_20, + XGPIOA_21, + XGPIOA_22, + XGPIOA_23, + XGPIOA_24, + XGPIOA_25, + XGPIOA_26, + XGPIOA_27, + XGPIOA_28, + XGPIOA_29, + XGPIOA_30, + XGPIOB_0, + XGPIOB_1, + XGPIOB_2, + XGPIOB_3, + XGPIOB_4, + XGPIOB_5, + XGPIOB_6, + XGPIOB_7, + XGPIOB_8, + XGPIOB_9, + XGPIOB_10, + XGPIOB_11, + XGPIOB_12, + XGPIOB_13, + XGPIOB_14, + XGPIOB_15, + XGPIOB_16, + XGPIOB_17, + XGPIOB_18, + XGPIOB_19, + XGPIOB_20, + XGPIOB_21, + XGPIOB_22, + XGPIOB_23, + XGPIOB_24, + XGPIOB_25, + XGPIOB_26, + XGPIOB_27, + XGPIOC_0, + XGPIOC_1, + XGPIOC_2, + XGPIOC_3, + XGPIOC_4, + XGPIOC_5, + XGPIOC_6, + XGPIOC_7, + XGPIOC_8, + XGPIOC_9, + XGPIOC_10, + XGPIOC_11, + XGPIOC_12, + XGPIOC_13, + XGPIOC_14, + XGPIOC_15, + XGPIOC_16, + XGPIOC_17, + XGPIOC_18, + XGPIOC_19, + XGPIOC_20, + XGPIOC_21, + XGPIOC_22, + XGPIOC_23, + XGPIOC_24, + XGPIOC_25, +} fs_type; + +/** + * @brief configure pin multiplex + * + * @param pin_name pin name string + * @param func_type function type enum + * @param whitelist pin name whilelist which is allowed to set. Ignore check + * if NULL. + * NOTE: whitelist should be a string list ended with NULL. + * + * @return RT_EOK if succeeded + * else: something wrong occurred and config is abandoned. + */ +extern int pinmux_config(const char *pin_name, fs_type func_type, const char *whitelist[]); + +#endif From d8d0af9143bc40c017aa7d9833b6a87e5d843968 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Mon, 13 May 2024 08:05:34 +0800 Subject: [PATCH 05/14] bsp:cvitek: add calibration for adc The ADC controller needs to be calibrated during the initialization phase, otherwise the measured voltage value will be inaccurate. Signed-off-by: Chen Wang --- bsp/cvitek/drivers/drv_adc.c | 8 +++++++- bsp/cvitek/drivers/drv_adc.h | 18 ++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/bsp/cvitek/drivers/drv_adc.c b/bsp/cvitek/drivers/drv_adc.c index 39440cd49a..242d2216eb 100644 --- a/bsp/cvitek/drivers/drv_adc.c +++ b/bsp/cvitek/drivers/drv_adc.c @@ -103,7 +103,13 @@ static const struct rt_adc_ops _adc_ops = int rt_hw_adc_init(void) { rt_uint8_t i; - for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i ++) + + for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++) + { + cvi_do_calibration(adc_dev_config[i].base); + } + + for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++) { if (rt_hw_adc_register(&adc_dev_config[i].device, adc_dev_config[i].name, &_adc_ops, &adc_dev_config[i]) != RT_EOK) { diff --git a/bsp/cvitek/drivers/drv_adc.h b/bsp/cvitek/drivers/drv_adc.h index 7539ab5604..3ef86a2ecb 100644 --- a/bsp/cvitek/drivers/drv_adc.h +++ b/bsp/cvitek/drivers/drv_adc.h @@ -48,6 +48,11 @@ #define SARADC_RESULT_MASK 0x0FFF #define SARADC_RESULT_VALID (1 << 15) +#define SARADC_TEST_OFFSET 0x030 +#define SARADC_TEST_VREFSEL_BIT 2 + +#define SARADC_TRIM_OFFSET 0x034 + rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value) { value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET); @@ -78,6 +83,19 @@ rt_inline void cvi_set_cyc(unsigned long reg_base) mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value); } +rt_inline void cvi_do_calibration(unsigned long reg_base) +{ + rt_uint32_t val; + + val = mmio_read_32(reg_base + SARADC_TEST_OFFSET); + val |= 1 << SARADC_TEST_VREFSEL_BIT; + mmio_write_32(reg_base + SARADC_TEST_OFFSET, val); + + val = mmio_read_32(reg_base + SARADC_TRIM_OFFSET); + val |= 0x4; + mmio_write_32(reg_base + SARADC_TRIM_OFFSET, val); +} + int rt_hw_adc_init(void); #endif /* __DRV_ADC_H__ */ From 1b581d0755450788b161f05486ecd97ee4f88ff3 Mon Sep 17 00:00:00 2001 From: Shell Date: Tue, 16 Jul 2024 17:03:54 +0800 Subject: [PATCH 06/14] [dfs] Mark dirty on unmap on shared mapping only (#9195) [dfs] feat: Mark dirty on unmap for shared mapping This patch optimizes the pcache varea management by refining the conditions under which pages are marked dirty, specifically targeting the unmap operations in the dfs_pcache component. These changes were necessary to enhance the efficiency of page cache management. Changes: - Adjusted include statements in `dfs_pcache.c` for better organization. - Modified `dfs_aspace_unmap` function: - Added a check to ensure `varea` is not privately locked before marking a page as dirty. - Updated `dfs_aspace_page_unmap` function: - Added a similar check for `varea` lock status before marking a page as dirty. Signed-off-by: Shell --- components/dfs/dfs_v2/src/dfs_pcache.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/components/dfs/dfs_v2/src/dfs_pcache.c b/components/dfs/dfs_v2/src/dfs_pcache.c index 350ad1f061..6868170b9c 100644 --- a/components/dfs/dfs_v2/src/dfs_pcache.c +++ b/components/dfs/dfs_v2/src/dfs_pcache.c @@ -13,10 +13,11 @@ #define DBG_LVL DBG_WARNING #include -#include "dfs_pcache.h" -#include "dfs_dentry.h" -#include "dfs_mnt.h" -#include "mm_page.h" +#include +#include +#include +#include +#include #include #include @@ -1380,7 +1381,8 @@ int dfs_aspace_unmap(struct dfs_file *file, struct rt_varea *varea) rt_varea_unmap_page(map_varea, vaddr); - if (varea->attr == MMU_MAP_U_RWCB && page->fpos < page->aspace->vnode->size) + if (!rt_varea_is_private_locked(varea) && + page->fpos < page->aspace->vnode->size) { dfs_page_dirty(page); } @@ -1425,7 +1427,7 @@ int dfs_aspace_page_unmap(struct dfs_file *file, struct rt_varea *varea, void *v if (map && varea->aspace == map->aspace && vaddr == map->vaddr) { - if (varea->attr == MMU_MAP_U_RWCB) + if (!rt_varea_is_private_locked(varea)) { dfs_page_dirty(page); } From 23fc7bfa4d992a105d72f114f0a712b3f61cbd65 Mon Sep 17 00:00:00 2001 From: zms123456 <85141075+zmshahaha@users.noreply.github.com> Date: Tue, 16 Jul 2024 17:04:55 +0800 Subject: [PATCH 07/14] [libcpu][setup]fix fdt_ptr error (#9138) fix fdt_ptr error --- libcpu/aarch64/common/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index b38398ed9d..dd30b1d673 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -235,7 +235,7 @@ void rt_hw_common_setup(void) rt_memblock_reserve_memory("fdt", fdt_start, fdt_end, MEMBLOCK_NONE); rt_memmove((void *)(fdt_start - PV_OFFSET), (void *)(fdt_ptr - PV_OFFSET), fdt_size); - fdt_ptr = (void *)fdt_start; + fdt_ptr = (void *)fdt_start - PV_OFFSET; rt_system_heap_init((void *)(heap_start - PV_OFFSET), (void *)(heap_end - PV_OFFSET)); From e1eb3d321712cee44de1a3698fb58ef75e5d8339 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 16:33:30 +0800 Subject: [PATCH 08/14] bsp:cvitek: add pinmux for i2c Based on new pinmux framework, add configuration for uart. Board level pin available info is summarized and should be controlled by pin whitelist. Duo NAME I2C CV1800B/GPIO __ ---- --- ------------ --------------------- GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo256m NAME I2C CV1800B/GPIO __ ---- --- ------------ --------------------- GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA Duo S(Note, we have not supported duo S, just list for memo) NAME I2C CV1800B/GPIO __ ---- --- ------------ --------------------- J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/board/Kconfig | 57 +++++++++ bsp/cvitek/cv18xx_risc-v/board/Kconfig | 57 +++++++++ bsp/cvitek/drivers/drv_hw_i2c.c | 160 +++++++++++++++++++++++-- 3 files changed, 265 insertions(+), 9 deletions(-) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 06d8214321..acb65707cc 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -31,10 +31,67 @@ menu "General Drivers Configuration" bool "Enable I2C0" default n + if BSP_USING_I2C0 + config BSP_I2C0_SCL_PINNAME + string "i2c0 scl pin name" + default "" + config BSP_I2C0_SDA_PINNAME + string "i2c0 sda pin name" + default "" + endif + config BSP_USING_I2C1 bool "Enable I2C1" default n + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PINNAME + string "i2c1 scl pin name" + default "" + config BSP_I2C1_SDA_PINNAME + string "i2c1 sda pin name" + default "" + endif + + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + + if BSP_USING_I2C2 + config BSP_I2C2_SCL_PINNAME + string "i2c2 scl pin name" + default "" + config BSP_I2C2_SDA_PINNAME + string "i2c2 sda pin name" + default "" + endif + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + + if BSP_USING_I2C3 + config BSP_I2C3_SCL_PINNAME + string "i2c3 scl pin name" + default "" + config BSP_I2C3_SDA_PINNAME + string "i2c3 sda pin name" + default "" + endif + + config BSP_USING_I2C4 + bool "Enable I2C4" + default n + + if BSP_USING_I2C4 + config BSP_I2C4_SCL_PINNAME + string "i2c4 scl pin name" + default "" + config BSP_I2C4_SDA_PINNAME + string "i2c4 sda pin name" + default "" + endif + config I2C_IRQ_BASE int default 32 diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index bc213c777e..3c3b7daacb 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -44,10 +44,67 @@ menu "General Drivers Configuration" bool "Enable I2C0" default n + if BSP_USING_I2C0 + config BSP_I2C0_SCL_PINNAME + string "i2c0 scl pin name" + default "" + config BSP_I2C0_SDA_PINNAME + string "i2c0 sda pin name" + default "" + endif + config BSP_USING_I2C1 bool "Enable I2C1" default n + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PINNAME + string "i2c1 scl pin name" + default "" + config BSP_I2C1_SDA_PINNAME + string "i2c1 sda pin name" + default "" + endif + + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + + if BSP_USING_I2C2 + config BSP_I2C2_SCL_PINNAME + string "i2c2 scl pin name" + default "" + config BSP_I2C2_SDA_PINNAME + string "i2c2 sda pin name" + default "" + endif + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + + if BSP_USING_I2C3 + config BSP_I2C3_SCL_PINNAME + string "i2c3 scl pin name" + default "" + config BSP_I2C3_SDA_PINNAME + string "i2c3 sda pin name" + default "" + endif + + config BSP_USING_I2C4 + bool "Enable I2C4" + default n + + if BSP_USING_I2C4 + config BSP_I2C4_SCL_PINNAME + string "i2c4 scl pin name" + default "" + config BSP_I2C4_SDA_PINNAME + string "i2c4 sda pin name" + default "" + endif + config I2C_IRQ_BASE int default 49 diff --git a/bsp/cvitek/drivers/drv_hw_i2c.c b/bsp/cvitek/drivers/drv_hw_i2c.c index 022a050c74..6f2fd06b40 100644 --- a/bsp/cvitek/drivers/drv_hw_i2c.c +++ b/bsp/cvitek/drivers/drv_hw_i2c.c @@ -10,6 +10,7 @@ #include "drv_hw_i2c.h" #include #include +#include "drv_pinmux.h" #define DBG_TAG "drv.i2c" #define DBG_LVL DBG_INFO @@ -467,19 +468,160 @@ static const struct rt_i2c_bus_device_ops i2c_ops = .i2c_bus_control = RT_NULL }; + +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) + +#ifdef BSP_USING_I2C0 +static const char *pinname_whitelist_i2c0_scl[] = { + "IIC0_SCL", + NULL, +}; +static const char *pinname_whitelist_i2c0_sda[] = { + "IIC0_SDA", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C1 +static const char *pinname_whitelist_i2c1_scl[] = { + "SD1_D2", + "SD1_D3", + "PAD_MIPIRX0N", + NULL, +}; +static const char *pinname_whitelist_i2c1_sda[] = { + "SD1_D1", + "SD1_D0", + "PAD_MIPIRX1P", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C2 +// I2C2 is not ALLOWED for Duo +static const char *pinname_whitelist_i2c2_scl[] = { + NULL, +}; +static const char *pinname_whitelist_i2c2_sda[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_I2C3 +static const char *pinname_whitelist_i2c3_scl[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_i2c3_sda[] = { + "SD1_CLK", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C4 +// I2C4 is not ALLOWED for Duo +static const char *pinname_whitelist_i2c4_scl[] = { + NULL, +}; +static const char *pinname_whitelist_i2c4_sda[] = { + NULL, +}; +#endif + +#elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +#ifdef BSP_USING_I2C0 +// I2C0 is not ALLOWED for Duo +static const char *pinname_whitelist_i2c0_scl[] = { + NULL, +}; +static const char *pinname_whitelist_i2c0_sda[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_I2C1 +static const char *pinname_whitelist_i2c1_scl[] = { + "SD1_D2", + "SD1_D3", + NULL, +}; +static const char *pinname_whitelist_i2c1_sda[] = { + "SD1_D1", + "SD1_D0", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C2 +static const char *pinname_whitelist_i2c2_scl[] = { + "PAD_MIPI_TXP1", + NULL, +}; +static const char *pinname_whitelist_i2c2_sda[] = { + "PAD_MIPI_TXM1", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C3 +static const char *pinname_whitelist_i2c3_scl[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_i2c3_sda[] = { + "SD1_CLK", + NULL, +}; +#endif + +#ifdef BSP_USING_I2C4 +// I2C4 is not ALLOWED for Duo +static const char *pinname_whitelist_i2c4_scl[] = { + NULL, +}; +static const char *pinname_whitelist_i2c4_sda[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + +static void rt_hw_i2c_pinmux_config() +{ +#ifdef BSP_USING_I2C0 + pinmux_config(BSP_I2C0_SCL_PINNAME, IIC0_SCL, pinname_whitelist_i2c0_scl); + pinmux_config(BSP_I2C0_SDA_PINNAME, IIC0_SDA, pinname_whitelist_i2c0_sda); +#endif /* BSP_USING_I2C0 */ + +#ifdef BSP_USING_I2C1 + pinmux_config(BSP_I2C1_SCL_PINNAME, IIC1_SCL, pinname_whitelist_i2c1_scl); + pinmux_config(BSP_I2C1_SDA_PINNAME, IIC1_SDA, pinname_whitelist_i2c1_sda); +#endif /* BSP_USING_I2C1 */ + +#ifdef BSP_USING_I2C2 + pinmux_config(BSP_I2C2_SCL_PINNAME, IIC2_SCL, pinname_whitelist_i2c2_scl); + pinmux_config(BSP_I2C2_SDA_PINNAME, IIC2_SDA, pinname_whitelist_i2c2_sda); +#endif /* BSP_USING_I2C2 */ + +#ifdef BSP_USING_I2C3 + pinmux_config(BSP_I2C3_SCL_PINNAME, IIC3_SCL, pinname_whitelist_i2c3_scl); + pinmux_config(BSP_I2C3_SDA_PINNAME, IIC3_SDA, pinname_whitelist_i2c3_sda); +#endif /* BSP_USING_I2C3 */ + +#ifdef BSP_USING_I2C4 + pinmux_config(BSP_I2C4_SCL_PINNAME, IIC4_SCL, pinname_whitelist_i2c4_scl); + pinmux_config(BSP_I2C4_SDA_PINNAME, IIC4_SDA, pinname_whitelist_i2c4_sda); +#endif /* BSP_USING_I2C4 */ +} + int rt_hw_i2c_init(void) { int result = RT_EOK; -#ifdef BSP_USING_I2C0 - PINMUX_CONFIG(IIC0_SCL, IIC0_SCL); - PINMUX_CONFIG(IIC0_SDA, IIC0_SDA); -#endif /* BSP_USING_I2C0 */ - -#ifdef BSP_USING_I2C1 - PINMUX_CONFIG(PAD_MIPIRX1P, IIC1_SDA); - PINMUX_CONFIG(PAD_MIPIRX0N, IIC1_SCL); -#endif /* BSP_USING_I2C1 */ + rt_hw_i2c_pinmux_config(); for (rt_size_t i = 0; i < sizeof(_i2c_obj) / sizeof(struct _i2c_bus); i++) { From 114e143d56e5aabaee93880b06767ef8ebb832c3 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 16:12:24 +0800 Subject: [PATCH 09/14] bsp:cvitek: add pinmux for uart Board level UART pinmux summary, following capability should be controlled by pinname whitelist. Duo: NAME UART CV1800B/GPIO __ ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX Duo 256m: NAME UART CV1800B/GPIO __ ---- --- ------------ --------------------- GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX Note: this patch also update the .config and rtconfig.h because this patch modify some configuration items's name, for example: RT_USIMG_UART0 -> BSP_USING_UART0. FIXME: only handle RISC-V related, no ARM. Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/.config | 59 ++++++--- bsp/cvitek/c906_little/board/Kconfig | 73 +++++++++-- bsp/cvitek/c906_little/rtconfig.h | 18 ++- bsp/cvitek/cv18xx_risc-v/.config | 62 +++++++--- bsp/cvitek/cv18xx_risc-v/board/Kconfig | 88 +++++++++---- bsp/cvitek/cv18xx_risc-v/rtconfig.h | 18 ++- bsp/cvitek/drivers/drv_uart.c | 165 ++++++++++++++++++++++--- 7 files changed, 391 insertions(+), 92 deletions(-) diff --git a/bsp/cvitek/c906_little/.config b/bsp/cvitek/c906_little/.config index cb930cd937..5fe52bcac9 100644 --- a/bsp/cvitek/c906_little/.config +++ b/bsp/cvitek/c906_little/.config @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -25,6 +24,8 @@ CONFIG_IDLE_THREAD_STACK_SIZE=1024 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -45,6 +46,7 @@ CONFIG_RT_DEBUGING_ASSERT=y CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -131,6 +133,7 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set @@ -149,6 +152,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_ZERO is not set # CONFIG_RT_USING_RANDOM is not set # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -161,21 +166,12 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -252,6 +248,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -279,6 +284,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -383,6 +389,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set # end of IoT - internet of things # @@ -528,6 +535,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set # end of enhanced kernel services +# CONFIG_PKG_USING_AUNITY is not set + # # acceleration: Assembly language or algorithmic acceleration packages # @@ -618,11 +627,27 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set # end of STM32 HAL & SDK Drivers +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -817,6 +842,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set @@ -1133,8 +1159,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # General Drivers Configuration # CONFIG_BSP_USING_UART=y -# CONFIG_RT_USING_UART0 is not set -CONFIG_RT_USING_UART1=y +# CONFIG_BSP_USING_UART0 is not set +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_UART1_RX_PINNAME="IIC0_SDA" +CONFIG_BSP_UART1_TX_PINNAME="IIC0_SCL" +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set CONFIG_UART_IRQ_BASE=30 # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_ADC is not set diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index acb65707cc..6b7d6f91c5 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -6,17 +6,74 @@ menu "General Drivers Configuration" default y if BSP_USING_UART - config RT_USING_UART0 - bool "Enable UART 0" - default n + config BSP_USING_UART0 + bool "Enable UART 0" + default n - config RT_USING_UART1 - bool "Enable UART 1" - default y + if BSP_USING_UART0 + config BSP_UART0_RX_PINNAME + string "uart0 rx pin name" + default "" + config BSP_UART0_TX_PINNAME + string "uart0 tx pin name" + default "" + endif + + config BSP_USING_UART1 + bool "Enable UART 1" + default y + + if BSP_USING_UART1 + config BSP_UART1_RX_PINNAME + string "uart1 rx pin name" + default "IIC0_SDA" + config BSP_UART1_TX_PINNAME + string "uart1 tx pin name" + default "IIC0_SCL" + endif + + config BSP_USING_UART2 + bool "Enable UART 2" + default n + + if BSP_USING_UART2 + config BSP_UART2_RX_PINNAME + string "uart2 rx pin name" + default "" + config BSP_UART2_TX_PINNAME + string "uart2 tx pin name" + default "" + endif + + config BSP_USING_UART3 + bool "Enable UART 3" + default n + + if BSP_USING_UART3 + config BSP_UART3_RX_PINNAME + string "uart3 rx pin name" + default "" + config BSP_UART3_TX_PINNAME + string "uart3 tx pin name" + default "" + endif + + config BSP_USING_UART4 + bool "Enable UART 4" + default n + + if BSP_USING_UART4 + config BSP_UART4_RX_PINNAME + string "uart4 rx pin name" + default "" + config BSP_UART4_TX_PINNAME + string "uart4 tx pin name" + default "" + endif config UART_IRQ_BASE - int - default 30 + int + default 30 endif menuconfig BSP_USING_I2C diff --git a/bsp/cvitek/c906_little/rtconfig.h b/bsp/cvitek/c906_little/rtconfig.h index 70ef72f518..e86cf64339 100755 --- a/bsp/cvitek/c906_little/rtconfig.h +++ b/bsp/cvitek/c906_little/rtconfig.h @@ -9,7 +9,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -31,6 +30,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -95,10 +95,6 @@ #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -137,6 +133,10 @@ /* Utilities */ /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -233,6 +233,10 @@ /* end of STM32 HAL & SDK Drivers */ +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + /* Kendryte SDK */ /* end of Kendryte SDK */ @@ -319,7 +323,9 @@ /* General Drivers Configuration */ #define BSP_USING_UART -#define RT_USING_UART1 +#define BSP_USING_UART1 +#define BSP_UART1_RX_PINNAME "IIC0_SDA" +#define BSP_UART1_TX_PINNAME "IIC0_SCL" #define UART_IRQ_BASE 30 /* end of General Drivers Configuration */ #define BSP_USING_C906_LITTLE diff --git a/bsp/cvitek/cv18xx_risc-v/.config b/bsp/cvitek/cv18xx_risc-v/.config index a5bec1c11e..7593b94de2 100644 --- a/bsp/cvitek/cv18xx_risc-v/.config +++ b/bsp/cvitek/cv18xx_risc-v/.config @@ -15,7 +15,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set @@ -25,6 +24,8 @@ CONFIG_IDLE_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # # kservice optimization @@ -46,6 +47,7 @@ CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set # CONFIG_RT_DEBUGING_PAGE_LEAK is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y # # Inter-Thread communication @@ -170,6 +172,7 @@ CONFIG_RT_USING_DFS_ROMFS=y # Device Drivers # # CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y @@ -190,6 +193,8 @@ CONFIG_RT_USING_NULL=y CONFIG_RT_USING_ZERO=y CONFIG_RT_USING_RANDOM=y # CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set @@ -210,21 +215,12 @@ CONFIG_RT_MMCSD_MAX_PARTITION=16 # CONFIG_RT_USING_TOUCH is not set # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y CONFIG_RT_USING_KTIME=y # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set -# end of Using USB +# CONFIG_RT_USING_CHERRYUSB is not set # end of Device Drivers # @@ -393,6 +389,15 @@ CONFIG_RT_USING_ADT_REF=y # end of Utilities # CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set # end of RT-Thread Components # @@ -420,6 +425,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set # # Wi-Fi @@ -524,6 +530,7 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set # end of IoT - internet of things # @@ -669,6 +676,8 @@ CONFIG_RT_USING_ADT_REF=y # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set # end of enhanced kernel services +# CONFIG_PKG_USING_AUNITY is not set + # # acceleration: Assembly language or algorithmic acceleration packages # @@ -759,11 +768,27 @@ CONFIG_RT_USING_ADT_REF=y # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set # end of STM32 HAL & SDK Drivers +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -958,6 +983,7 @@ CONFIG_RT_USING_ADT_REF=y # # Signal Processing and Control Algorithm Packages # +# CONFIG_PKG_USING_APID is not set # CONFIG_PKG_USING_FIRE_PID_CURVE is not set # CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set @@ -1274,12 +1300,14 @@ CONFIG_RT_USING_ADT_REF=y # General Drivers Configuration # CONFIG_BSP_USING_UART=y -CONFIG_RT_USING_UART0=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_PINNAME="UART0_RX" +CONFIG_BSP_UART0_TX_PINNAME="UART0_TX" +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set CONFIG_UART_IRQ_BASE=44 -# CONFIG_RT_USING_UART1 is not set -# CONFIG_RT_USING_UART2 is not set -# CONFIG_RT_USING_UART3 is not set -# CONFIG_RT_USING_UART4 is not set # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_SPI is not set diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 3c3b7daacb..6b3cf19fdd 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -6,30 +6,74 @@ menu "General Drivers Configuration" default y if BSP_USING_UART - config RT_USING_UART0 - bool "Enable UART 0" - default y + config BSP_USING_UART0 + bool "Enable UART 0" + default y + + if BSP_USING_UART0 + config BSP_UART0_RX_PINNAME + string "uart0 rx pin name" + default "UART0_RX" + config BSP_UART0_TX_PINNAME + string "uart0 tx pin name" + default "UART0_TX" + endif + + config BSP_USING_UART1 + bool "Enable UART 1" + default n + + if BSP_USING_UART1 + config BSP_UART1_RX_PINNAME + string "uart1 rx pin name" + default "" + config BSP_UART1_TX_PINNAME + string "uart1 tx pin name" + default "" + endif + + config BSP_USING_UART2 + bool "Enable UART 2" + default n + + if BSP_USING_UART2 + config BSP_UART2_RX_PINNAME + string "uart2 rx pin name" + default "" + config BSP_UART2_TX_PINNAME + string "uart2 tx pin name" + default "" + endif + + config BSP_USING_UART3 + bool "Enable UART 3" + default n + + if BSP_USING_UART3 + config BSP_UART3_RX_PINNAME + string "uart3 rx pin name" + default "" + config BSP_UART3_TX_PINNAME + string "uart3 tx pin name" + default "" + endif + + config BSP_USING_UART4 + bool "Enable UART 4" + default n + + if BSP_USING_UART4 + config BSP_UART4_RX_PINNAME + string "uart4 rx pin name" + default "" + config BSP_UART4_TX_PINNAME + string "uart4 tx pin name" + default "" + endif config UART_IRQ_BASE - int - default 44 - - config RT_USING_UART1 - bool "Enable UART 1" - default n - - config RT_USING_UART2 - bool "Enable UART 2" - default n - - config RT_USING_UART3 - bool "Enable UART 3" - default n - - config RT_USING_UART4 - bool "Enable UART 4" - default n - + int + default 44 endif menuconfig BSP_USING_I2C diff --git a/bsp/cvitek/cv18xx_risc-v/rtconfig.h b/bsp/cvitek/cv18xx_risc-v/rtconfig.h index 0574fefe54..d168377aa8 100755 --- a/bsp/cvitek/cv18xx_risc-v/rtconfig.h +++ b/bsp/cvitek/cv18xx_risc-v/rtconfig.h @@ -9,7 +9,6 @@ #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK @@ -31,6 +30,7 @@ #define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK /* Inter-Thread communication */ @@ -135,10 +135,6 @@ #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_PIN #define RT_USING_KTIME - -/* Using USB */ - -/* end of Using USB */ /* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -252,6 +248,10 @@ #define RT_USING_ADT_HASHMAP #define RT_USING_ADT_REF /* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ /* end of RT-Thread Components */ /* RT-Thread Utestcases */ @@ -348,6 +348,10 @@ /* end of STM32 HAL & SDK Drivers */ +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + /* Kendryte SDK */ /* end of Kendryte SDK */ @@ -434,7 +438,9 @@ /* General Drivers Configuration */ #define BSP_USING_UART -#define RT_USING_UART0 +#define BSP_USING_UART0 +#define BSP_UART0_RX_PINNAME "UART0_RX" +#define BSP_UART0_TX_PINNAME "UART0_TX" #define UART_IRQ_BASE 44 /* end of General Drivers Configuration */ #define BSP_USING_CV18XX diff --git a/bsp/cvitek/drivers/drv_uart.c b/bsp/cvitek/drivers/drv_uart.c index ed482b2142..7da298452f 100644 --- a/bsp/cvitek/drivers/drv_uart.c +++ b/bsp/cvitek/drivers/drv_uart.c @@ -13,6 +13,7 @@ #include "board.h" #include "drv_uart.h" +#include "drv_pinmux.h" #define DBG_TAG "DRV.UART" #define DBG_LVL DBG_WARNING @@ -50,19 +51,19 @@ static struct hw_uart_device _uart##no##_device = \ }; \ static struct rt_serial_device _serial##no; -#ifdef RT_USING_UART0 +#ifdef BSP_USING_UART0 BSP_DEFINE_UART_DEVICE(0); #endif -#ifdef RT_USING_UART1 +#ifdef BSP_USING_UART1 BSP_DEFINE_UART_DEVICE(1); #endif -#ifdef RT_USING_UART2 +#ifdef BSP_USING_UART2 BSP_DEFINE_UART_DEVICE(2); #endif -#ifdef RT_USING_UART3 +#ifdef BSP_USING_UART3 BSP_DEFINE_UART_DEVICE(3); #endif @@ -234,6 +235,132 @@ static void rt_hw_uart_isr(int irqno, void *param) } } +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) + +#ifdef BSP_USING_UART0 +static const char *pinname_whitelist_uart0_rx[] = { + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_uart0_tx[] = { + "UART0_TX", + NULL, +}; +#endif + +#ifdef BSP_USING_UART1 +static const char *pinname_whitelist_uart1_rx[] = { + "IIC0_SDA", + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_uart1_tx[] = { + "IIC0_SCL", + "UART0_TX", + NULL, +}; +#endif + +#ifdef BSP_USING_UART2 +static const char *pinname_whitelist_uart2_rx[] = { + "IIC0_SDA", + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_uart2_tx[] = { + "IIC0_SCL", + "SD1_D2", + NULL, +}; +#endif + +#ifdef BSP_USING_UART3 +static const char *pinname_whitelist_uart3_rx[] = { + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_uart3_tx[] = { + "SD1_D2", + NULL, +}; +#endif + +#ifdef BSP_USING_UART4 +static const char *pinname_whitelist_uart4_rx[] = { + "SD1_GPIO0", + NULL, +}; +static const char *pinname_whitelist_uart4_tx[] = { + "SD1_GPIO1", + NULL, +}; +#endif + +#elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +#ifdef BSP_USING_UART0 +static const char *pinname_whitelist_uart0_rx[] = { + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_uart0_tx[] = { + "UART0_TX", + NULL, +}; +#endif + +#ifdef BSP_USING_UART1 +static const char *pinname_whitelist_uart1_rx[] = { + "IIC0_SDA", + "JTAG_CPU_TCK", + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_uart1_tx[] = { + "IIC0_SCL", + "JTAG_CPU_TMS", + "UART0_TX", + NULL, +}; +#endif + +#ifdef BSP_USING_UART2 +static const char *pinname_whitelist_uart2_rx[] = { + "IIC0_SDA", + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_uart2_tx[] = { + "IIC0_SCL", + "SD1_D2", + NULL, +}; +#endif + +#ifdef BSP_USING_UART3 +static const char *pinname_whitelist_uart3_rx[] = { + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_uart3_tx[] = { + "SD1_D2", + NULL, +}; +#endif + +#ifdef BSP_USING_UART4 +static const char *pinname_whitelist_uart4_rx[] = { + NULL, +}; +static const char *pinname_whitelist_uart4_tx[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + int rt_hw_uart_init(void) { struct hw_uart_device* uart; @@ -248,45 +375,45 @@ int rt_hw_uart_init(void) rt_hw_serial_register(&_serial##no, "uart" #no, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); \ rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial##no, "uart" #no); -#ifdef RT_USING_UART0 - PINMUX_CONFIG(UART0_RX, UART0_RX); - PINMUX_CONFIG(UART0_TX, UART0_TX); +#ifdef BSP_USING_UART0 + pinmux_config(BSP_UART0_RX_PINNAME, UART0_RX, pinname_whitelist_uart0_rx); + pinmux_config(BSP_UART0_TX_PINNAME, UART0_TX, pinname_whitelist_uart0_tx); BSP_INSTALL_UART_DEVICE(0); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); #endif /* defined(ARCH_ARM) */ #endif -#ifdef RT_USING_UART1 - PINMUX_CONFIG(IIC0_SDA, UART1_RX); - PINMUX_CONFIG(IIC0_SCL, UART1_TX); +#ifdef BSP_USING_UART1 + pinmux_config(BSP_UART1_RX_PINNAME, UART1_RX, pinname_whitelist_uart1_rx); + pinmux_config(BSP_UART1_TX_PINNAME, UART1_TX, pinname_whitelist_uart1_tx); BSP_INSTALL_UART_DEVICE(1); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); #endif /* defined(ARCH_ARM) */ #endif -#ifdef RT_USING_UART2 - PINMUX_CONFIG(SD1_D1, UART2_RX); - PINMUX_CONFIG(SD1_D2, UART2_TX); +#ifdef BSP_USING_UART2 + pinmux_config(BSP_UART2_RX_PINNAME, UART2_RX, pinname_whitelist_uart2_rx); + pinmux_config(BSP_UART2_TX_PINNAME, UART2_TX, pinname_whitelist_uart2_tx); BSP_INSTALL_UART_DEVICE(2); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); #endif /* defined(ARCH_ARM) */ #endif -#ifdef RT_USING_UART3 - PINMUX_CONFIG(SD1_D1, UART3_RX); - PINMUX_CONFIG(SD1_D2, UART3_TX); +#ifdef BSP_USING_UART3 + pinmux_config(BSP_UART3_RX_PINNAME, UART3_RX, pinname_whitelist_uart3_rx); + pinmux_config(BSP_UART3_TX_PINNAME, UART3_TX, pinname_whitelist_uart3_tx); BSP_INSTALL_UART_DEVICE(3); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); #endif /* defined(ARCH_ARM) */ #endif -#ifdef RT_USING_UART4 - PINMUX_CONFIG(SD1_GP0, UART4_RX); - PINMUX_CONFIG(SD1_GP1, UART4_TX); +#ifdef BSP_USING_UART4 + pinmux_config(BSP_UART4_RX_PINNAME, UART4_RX, pinname_whitelist_uart4_rx); + pinmux_config(BSP_UART4_TX_PINNAME, UART4_TX, pinname_whitelist_uart4_tx); BSP_INSTALL_UART_DEVICE(4); #if defined(ARCH_ARM) uart->hw_base = (rt_size_t)rt_ioremap((void*)uart->hw_base, 0x10000); From 51825a5b5cd32b445d0eba4beb421ae920d20c77 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 17:47:48 +0800 Subject: [PATCH 10/14] bsp:cvitek: add pinmux for pwm Board level pin available info is summarized and list here for memo: Duo: NAME PWM CV1800B/GPIO __ ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10 GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11 Duo256: NAME PWM CV1800B/GPIO __ ---- --- ------------ --------------------- PWM-1 GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4 GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4 GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5 GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5 GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6 GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6 GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7 GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7 PWM-2 GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8 GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9 GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10 GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11 Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/board/Kconfig | 76 ++++++++-- bsp/cvitek/cv18xx_risc-v/board/Kconfig | 76 ++++++++-- bsp/cvitek/drivers/drv_pwm.c | 185 +++++++++++++++++++++++++ 3 files changed, 321 insertions(+), 16 deletions(-) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 6b7d6f91c5..620f4039ff 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -190,20 +190,80 @@ menu "General Drivers Configuration" if BSP_USING_PWM config BSP_USING_PWM0 - bool "Enable PWM 0" - default n + bool "Enable PWM 0" + default n + + if BSP_USING_PWM0 + config BSP_PWM0_0_PINNAME + string "pwm[0] pin name" + default "" + config BSP_PWM0_1_PINNAME + string "pwm[1] pin name" + default "" + config BSP_PWM0_2_PINNAME + string "pwm[2] pin name" + default "" + config BSP_PWM0_3_PINNAME + string "pwm[3] pin name" + default "" + endif config BSP_USING_PWM1 - bool "Enable PWM 1" - default n + bool "Enable PWM 1" + default n + + if BSP_USING_PWM1 + config BSP_PWM1_4_PINNAME + string "pwm[4] pin name" + default "" + config BSP_PWM1_5_PINNAME + string "pwm[5] pin name" + default "" + config BSP_PWM1_6_PINNAME + string "pwm[6] pin name" + default "" + config BSP_PWM1_7_PINNAME + string "pwm[7] pin name" + default "" + endif config BSP_USING_PWM2 - bool "Enable PWM 2" - default n + bool "Enable PWM 2" + default n + + if BSP_USING_PWM2 + config BSP_PWM2_8_PINNAME + string "pwm[8] pin name" + default "" + config BSP_PWM2_9_PINNAME + string "pwm[9] pin name" + default "" + config BSP_PWM2_10_PINNAME + string "pwm[10] pin name" + default "" + config BSP_PWM2_11_PINNAME + string "pwm[11] pin name" + default "" + endif config BSP_USING_PWM3 - bool "Enable PWM 3" - default n + bool "Enable PWM 3" + default n + + if BSP_USING_PWM3 + config BSP_PWM3_12_PINNAME + string "pwm[12] pin name" + default "" + config BSP_PWM3_13_PINNAME + string "pwm[13] pin name" + default "" + config BSP_PWM3_14_PINNAME + string "pwm[14] pin name" + default "" + config BSP_PWM3_15_PINNAME + string "pwm[15] pin name" + default "" + endif endif config BSP_USING_RTC diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 6b3cf19fdd..85426b7418 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -190,20 +190,80 @@ menu "General Drivers Configuration" if BSP_USING_PWM config BSP_USING_PWM0 - bool "Enable PWM 0" - default n + bool "Enable PWM 0" + default n + + if BSP_USING_PWM0 + config BSP_PWM0_0_PINNAME + string "pwm[0] pin name" + default "" + config BSP_PWM0_1_PINNAME + string "pwm[1] pin name" + default "" + config BSP_PWM0_2_PINNAME + string "pwm[2] pin name" + default "" + config BSP_PWM0_3_PINNAME + string "pwm[3] pin name" + default "" + endif config BSP_USING_PWM1 - bool "Enable PWM 1" - default n + bool "Enable PWM 1" + default n + + if BSP_USING_PWM1 + config BSP_PWM1_4_PINNAME + string "pwm[4] pin name" + default "" + config BSP_PWM1_5_PINNAME + string "pwm[5] pin name" + default "" + config BSP_PWM1_6_PINNAME + string "pwm[6] pin name" + default "" + config BSP_PWM1_7_PINNAME + string "pwm[7] pin name" + default "" + endif config BSP_USING_PWM2 - bool "Enable PWM 2" - default n + bool "Enable PWM 2" + default n + + if BSP_USING_PWM2 + config BSP_PWM2_8_PINNAME + string "pwm[8] pin name" + default "" + config BSP_PWM2_9_PINNAME + string "pwm[9] pin name" + default "" + config BSP_PWM2_10_PINNAME + string "pwm[10] pin name" + default "" + config BSP_PWM2_11_PINNAME + string "pwm[11] pin name" + default "" + endif config BSP_USING_PWM3 - bool "Enable PWM 3" - default n + bool "Enable PWM 3" + default n + + if BSP_USING_PWM3 + config BSP_PWM3_12_PINNAME + string "pwm[12] pin name" + default "" + config BSP_PWM3_13_PINNAME + string "pwm[13] pin name" + default "" + config BSP_PWM3_14_PINNAME + string "pwm[14] pin name" + default "" + config BSP_PWM3_15_PINNAME + string "pwm[15] pin name" + default "" + endif endif config BSP_USING_RTC diff --git a/bsp/cvitek/drivers/drv_pwm.c b/bsp/cvitek/drivers/drv_pwm.c index e79a152119..a52bc6af7a 100644 --- a/bsp/cvitek/drivers/drv_pwm.c +++ b/bsp/cvitek/drivers/drv_pwm.c @@ -10,6 +10,7 @@ #include #include #include "drv_pwm.h" +#include "drv_pinmux.h" #define DBG_LEVEL DBG_LOG #include @@ -134,11 +135,195 @@ static struct cvi_pwm_dev cvi_pwm[] = #endif }; + +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) + +#ifdef BSP_USING_PWM0 +static const char *pinname_whitelist_pwm0[] = { + NULL, +}; +static const char *pinname_whitelist_pwm1[] = { + NULL, +}; +static const char *pinname_whitelist_pwm2[] = { + NULL, +}; +static const char *pinname_whitelist_pwm3[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_PWM1 +static const char *pinname_whitelist_pwm4[] = { + "SD1_D3", + "UART0_TX", + NULL, +}; +static const char *pinname_whitelist_pwm5[] = { + "SD1_D2", + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_pwm6[] = { + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_pwm7[] = { + "SD1_D0", + NULL, +}; +#endif + +#ifdef BSP_USING_PWM2 +static const char *pinname_whitelist_pwm8[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_pwm9[] = { + "SD1_CLK", + NULL, +}; +static const char *pinname_whitelist_pwm10[] = { + "SD1_GPIO1", + NULL, +}; +static const char *pinname_whitelist_pwm11[] = { + "SD1_GPIO0", + NULL, +}; +#endif + +#ifdef BSP_USING_PWM3 +static const char *pinname_whitelist_pwm12[] = { + NULL, +}; +static const char *pinname_whitelist_pwm13[] = { + NULL, +}; +static const char *pinname_whitelist_pwm14[] = { + NULL, +}; +static const char *pinname_whitelist_pwm15[] = { + NULL, +}; +#endif + +#elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +#ifdef BSP_USING_PWM0 +static const char *pinname_whitelist_pwm0[] = { + NULL, +}; +static const char *pinname_whitelist_pwm1[] = { + NULL, +}; +static const char *pinname_whitelist_pwm2[] = { + NULL, +}; +static const char *pinname_whitelist_pwm3[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_PWM1 +static const char *pinname_whitelist_pwm4[] = { + "SD1_D3", + "UART0_TX", + NULL, +}; +static const char *pinname_whitelist_pwm5[] = { + "SD1_D2", + "UART0_RX", + NULL, +}; +static const char *pinname_whitelist_pwm6[] = { + "JTAG_CPU_TCK", + "SD1_D1", + NULL, +}; +static const char *pinname_whitelist_pwm7[] = { + "JTAG_CPU_TMS", + "SD1_D0", + NULL, +}; +#endif + +#ifdef BSP_USING_PWM2 +static const char *pinname_whitelist_pwm8[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_pwm9[] = { + "SD1_CLK", + NULL, +}; +static const char *pinname_whitelist_pwm10[] = { + "PAD_MIPI_TXM1", + NULL, +}; +static const char *pinname_whitelist_pwm11[] = { + "PAD_MIPI_TXP1", + NULL, +}; +#endif + +#ifdef BSP_USING_PWM3 +static const char *pinname_whitelist_pwm12[] = { + NULL, +}; +static const char *pinname_whitelist_pwm13[] = { + NULL, +}; +static const char *pinname_whitelist_pwm14[] = { + NULL, +}; +static const char *pinname_whitelist_pwm15[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + +static void rt_hw_pwm_pinmux_config() +{ +#ifdef BSP_USING_PWM0 + pinmux_config(BSP_PWM0_0_PINNAME, PWM_0, pinname_whitelist_pwm0); + pinmux_config(BSP_PWM0_1_PINNAME, PWM_1, pinname_whitelist_pwm1); + pinmux_config(BSP_PWM0_2_PINNAME, PWM_2, pinname_whitelist_pwm2); + pinmux_config(BSP_PWM0_3_PINNAME, PWM_3, pinname_whitelist_pwm3); +#endif /* BSP_USING_PWM0 */ + +#ifdef BSP_USING_PWM1 + pinmux_config(BSP_PWM1_4_PINNAME, PWM_4, pinname_whitelist_pwm4); + pinmux_config(BSP_PWM1_5_PINNAME, PWM_5, pinname_whitelist_pwm5); + pinmux_config(BSP_PWM1_6_PINNAME, PWM_6, pinname_whitelist_pwm6); + pinmux_config(BSP_PWM1_7_PINNAME, PWM_7, pinname_whitelist_pwm7); +#endif /* BSP_USING_PWM1 */ + +#ifdef BSP_USING_PWM2 + pinmux_config(BSP_PWM2_8_PINNAME, PWM_8, pinname_whitelist_pwm8); + pinmux_config(BSP_PWM2_9_PINNAME, PWM_9, pinname_whitelist_pwm9); + pinmux_config(BSP_PWM2_10_PINNAME, PWM_10, pinname_whitelist_pwm10); + pinmux_config(BSP_PWM2_11_PINNAME, PWM_11, pinname_whitelist_pwm11); +#endif /* BSP_USING_PWM2 */ + +#ifdef BSP_USING_PWM3 + pinmux_config(BSP_PWM3_12_PINNAME, PWM_12, pinname_whitelist_pwm12); + pinmux_config(BSP_PWM3_13_PINNAME, PWM_13, pinname_whitelist_pwm13); + pinmux_config(BSP_PWM3_14_PINNAME, PWM_14, pinname_whitelist_pwm14); + pinmux_config(BSP_PWM3_15_PINNAME, PWM_15, pinname_whitelist_pwm15); +#endif /* BSP_USING_PWM3 */ +} + int rt_hw_pwm_init(void) { int result = RT_EOK; uint8_t i; + rt_hw_pwm_pinmux_config(); + for (i = 0; i < sizeof(cvi_pwm) / sizeof(cvi_pwm[0]); i++) { result = rt_device_pwm_register(&cvi_pwm[i].device, cvi_pwm[i].name, &cvi_pwm_ops, &cvi_pwm[i]); From 2c85bcb463a37ae0a1ec60281e4a23945eb046d5 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 28 May 2024 18:45:53 +0800 Subject: [PATCH 11/14] bsp:cvitek: add pinmux for spi Board level pin available info: duo & duo256: NAME SPI CV1800B/GPIO __ ---- --- ------------ --------------------- GP6 SPI2_SCK PWR_GPIO[23] SD1_CLK__SPI2_SCK GP7 SPI2_SDO PWR_GPIO[22] SD1_CMD__SPI2_SDO GP8 SPI2_SDI PWR_GPIO[21] SD1_D0__SPI2_SDI GP9 SPI2_CS_X PWR_GPIO[18] SD1_D3__SPI2_CS_X Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/board/Kconfig | 78 +++++++++++++++++++ bsp/cvitek/cv18xx_risc-v/board/Kconfig | 78 +++++++++++++++++++ bsp/cvitek/drivers/drv_spi.c | 104 +++++++++++++++++++++++++ 3 files changed, 260 insertions(+) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 620f4039ff..95c97e725b 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -164,6 +164,84 @@ menu "General Drivers Configuration" select RT_USING_SPI default n + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI 0" + default n + + if BSP_USING_SPI0 + config BSP_SPI0_SCK_PINNAME + string "spi0 sck pin name" + default "" + config BSP_SPI0_SDO_PINNAME + string "spi0 sdo pin name" + default "" + config BSP_SPI0_SDI_PINNAME + string "spi0 sdi pin name" + default "" + config BSP_SPI0_CS_PINNAME + string "spi0 cs pin name" + default "" + endif + + config BSP_USING_SPI1 + bool "Enable SPI 1" + default n + + if BSP_USING_SPI1 + config BSP_SPI1_SCK_PINNAME + string "spi1 sck pin name" + default "" + config BSP_SPI1_SDO_PINNAME + string "spi1 sdo pin name" + default "" + config BSP_SPI1_SDI_PINNAME + string "spi1 sdi pin name" + default "" + config BSP_SPI1_CS_PINNAME + string "spi1 cs pin name" + default "" + endif + + config BSP_USING_SPI2 + bool "Enable SPI 2" + default n + + if BSP_USING_SPI2 + config BSP_SPI2_SCK_PINNAME + string "spi2 sck pin name" + default "" + config BSP_SPI2_SDO_PINNAME + string "spi2 sdo pin name" + default "" + config BSP_SPI2_SDI_PINNAME + string "spi2 sdi pin name" + default "" + config BSP_SPI2_CS_PINNAME + string "spi2 cs pin name" + default "" + endif + + config BSP_USING_SPI3 + bool "Enable SPI 3" + default n + + if BSP_USING_SPI3 + config BSP_SPI3_SCK_PINNAME + string "spi3 sck pin name" + default "" + config BSP_SPI3_SDO_PINNAME + string "spi3 sdo pin name" + default "" + config BSP_SPI3_SDI_PINNAME + string "spi3 sdi pin name" + default "" + config BSP_SPI3_CS_PINNAME + string "spi3 cs pin name" + default "" + endif + endif + menuconfig BSP_USING_WDT bool "Enable Watchdog Timer" select RT_USING_WDT diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 85426b7418..6ed5c54e74 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -164,6 +164,84 @@ menu "General Drivers Configuration" select RT_USING_SPI default n + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI 0" + default n + + if BSP_USING_SPI0 + config BSP_SPI0_SCK_PINNAME + string "spi0 sck pin name" + default "" + config BSP_SPI0_SDO_PINNAME + string "spi0 sdo pin name" + default "" + config BSP_SPI0_SDI_PINNAME + string "spi0 sdi pin name" + default "" + config BSP_SPI0_CS_PINNAME + string "spi0 cs pin name" + default "" + endif + + config BSP_USING_SPI1 + bool "Enable SPI 1" + default n + + if BSP_USING_SPI1 + config BSP_SPI1_SCK_PINNAME + string "spi1 sck pin name" + default "" + config BSP_SPI1_SDO_PINNAME + string "spi1 sdo pin name" + default "" + config BSP_SPI1_SDI_PINNAME + string "spi1 sdi pin name" + default "" + config BSP_SPI1_CS_PINNAME + string "spi1 cs pin name" + default "" + endif + + config BSP_USING_SPI2 + bool "Enable SPI 2" + default n + + if BSP_USING_SPI2 + config BSP_SPI2_SCK_PINNAME + string "spi2 sck pin name" + default "" + config BSP_SPI2_SDO_PINNAME + string "spi2 sdo pin name" + default "" + config BSP_SPI2_SDI_PINNAME + string "spi2 sdi pin name" + default "" + config BSP_SPI2_CS_PINNAME + string "spi2 cs pin name" + default "" + endif + + config BSP_USING_SPI3 + bool "Enable SPI 3" + default n + + if BSP_USING_SPI3 + config BSP_SPI3_SCK_PINNAME + string "spi3 sck pin name" + default "" + config BSP_SPI3_SDO_PINNAME + string "spi3 sdo pin name" + default "" + config BSP_SPI3_SDI_PINNAME + string "spi3 sdi pin name" + default "" + config BSP_SPI3_CS_PINNAME + string "spi3 cs pin name" + default "" + endif + endif + menuconfig BSP_USING_WDT bool "Enable Watchdog Timer" select RT_USING_WDT diff --git a/bsp/cvitek/drivers/drv_spi.c b/bsp/cvitek/drivers/drv_spi.c index 82a5b31b3d..3e88af06f6 100644 --- a/bsp/cvitek/drivers/drv_spi.c +++ b/bsp/cvitek/drivers/drv_spi.c @@ -9,6 +9,7 @@ */ #include "drv_spi.h" +#include "drv_pinmux.h" #define DBG_TAG "drv.spi" #define DBG_LVL DBG_INFO @@ -209,11 +210,114 @@ const static struct rt_spi_ops drv_spi_ops = spixfer, }; +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) || defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +#ifdef BSP_USING_SPI0 +static const char *pinname_whitelist_spi0_sck[] = { + NULL, +}; +static const char *pinname_whitelist_spi0_sdo[] = { + NULL, +}; +static const char *pinname_whitelist_spi0_sdi[] = { + NULL, +}; +static const char *pinname_whitelist_spi0_cs[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_SPI1 +static const char *pinname_whitelist_spi1_sck[] = { + NULL, +}; +static const char *pinname_whitelist_spi1_sdo[] = { + NULL, +}; +static const char *pinname_whitelist_spi1_sdi[] = { + NULL, +}; +static const char *pinname_whitelist_spi1_cs[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_SPI2 +static const char *pinname_whitelist_spi2_sck[] = { + "SD1_CLK", + NULL, +}; +static const char *pinname_whitelist_spi2_sdo[] = { + "SD1_CMD", + NULL, +}; +static const char *pinname_whitelist_spi2_sdi[] = { + "SD1_D0", + NULL, +}; +static const char *pinname_whitelist_spi2_cs[] = { + "SD1_D3", + NULL, +}; +#endif + +#ifdef BSP_USING_SPI3 +static const char *pinname_whitelist_spi3_sck[] = { + NULL, +}; +static const char *pinname_whitelist_spi3_sdo[] = { + NULL, +}; +static const char *pinname_whitelist_spi3_sdi[] = { + NULL, +}; +static const char *pinname_whitelist_spi3_cs[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + +static void rt_hw_spi_pinmux_config() +{ +#ifdef BSP_USING_SPI0 + pinmux_config(BSP_SPI0_SCK_PINNAME, SPI0_SCK, pinname_whitelist_spi0_sck); + pinmux_config(BSP_SPI0_SDO_PINNAME, SPI0_SDO, pinname_whitelist_spi0_sdo); + pinmux_config(BSP_SPI0_SDI_PINNAME, SPI0_SDI, pinname_whitelist_spi0_sdi); + pinmux_config(BSP_SPI0_CS_PINNAME, SPI0_CS_X, pinname_whitelist_spi0_cs); +#endif /* BSP_USING_SPI0 */ + +#ifdef BSP_USING_SPI1 + pinmux_config(BSP_SPI1_SCK_PINNAME, SPI1_SCK, pinname_whitelist_spi1_sck); + pinmux_config(BSP_SPI1_SDO_PINNAME, SPI1_SDO, pinname_whitelist_spi1_sdo); + pinmux_config(BSP_SPI1_SDI_PINNAME, SPI1_SDI, pinname_whitelist_spi1_sdi); + pinmux_config(BSP_SPI1_CS_PINNAME, SPI1_CS_X, pinname_whitelist_spi1_cs); +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_USING_SPI2 + pinmux_config(BSP_SPI2_SCK_PINNAME, SPI2_SCK, pinname_whitelist_spi2_sck); + pinmux_config(BSP_SPI2_SDO_PINNAME, SPI2_SDO, pinname_whitelist_spi2_sdo); + pinmux_config(BSP_SPI2_SDI_PINNAME, SPI2_SDI, pinname_whitelist_spi2_sdi); + pinmux_config(BSP_SPI2_CS_PINNAME, SPI2_CS_X, pinname_whitelist_spi2_cs); +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_USING_SPI3 + pinmux_config(BSP_SPI3_SCK_PINNAME, SPI3_SCK, pinname_whitelist_spi3_sck); + pinmux_config(BSP_SPI3_SDO_PINNAME, SPI3_SDO, pinname_whitelist_spi3_sdo); + pinmux_config(BSP_SPI3_SDI_PINNAME, SPI3_SDI, pinname_whitelist_spi3_sdi); + pinmux_config(BSP_SPI3_CS_PINNAME, SPI3_CS_X, pinname_whitelist_spi3_cs); +#endif /* BSP_USING_SPI3 */ +} + int rt_hw_spi_init(void) { rt_err_t ret = RT_EOK; struct spi_regs *reg = NULL; + rt_hw_spi_pinmux_config(); + for (rt_size_t i = 0; i < sizeof(cv1800_spi_obj) / sizeof(struct cv1800_spi); i++) { /* set reg base addr */ reg = get_spi_base(cv1800_spi_obj[i].spi_id); From d8294de64027696437bc4947c0eec28a3b4a17c4 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 4 Jun 2024 11:18:00 +0800 Subject: [PATCH 12/14] bsp:cvitek: add pinmux for adc Signed-off-by: Chen Wang --- bsp/cvitek/c906_little/board/Kconfig | 36 +++++++++- bsp/cvitek/cv18xx_risc-v/board/Kconfig | 36 +++++++++- bsp/cvitek/drivers/drv_adc.c | 92 ++++++++++++++++++++++++++ 3 files changed, 162 insertions(+), 2 deletions(-) diff --git a/bsp/cvitek/c906_little/board/Kconfig b/bsp/cvitek/c906_little/board/Kconfig index 95c97e725b..2a2422537e 100755 --- a/bsp/cvitek/c906_little/board/Kconfig +++ b/bsp/cvitek/c906_little/board/Kconfig @@ -154,11 +154,45 @@ menu "General Drivers Configuration" default 32 endif - config BSP_USING_ADC + menuconfig BSP_USING_ADC bool "Using ADC" select RT_USING_ADC default n + if BSP_USING_ADC + config BSP_USING_ADC_ACTIVE + bool "Enable ADC Controller in Active Domain" + default n + + if BSP_USING_ADC_ACTIVE + config BSP_ACTIVE_ADC1_PINNAME + string "Pin name for VIN1 in Active Domain" + default "" + config BSP_ACTIVE_ADC2_PINNAME + string "Pin name for VIN2 in Active Domain" + default "" + config BSP_ACTIVE_ADC3_PINNAME + string "Pin name for VIN3 in Active Domain" + default "" + endif + + config BSP_USING_ADC_NODIE + bool "Enable ADC Controller in No-die Domain" + default n + + if BSP_USING_ADC_NODIE + config BSP_NODIE_ADC1_PINNAME + string "Pin name for VIN1 in No-die Domain" + default "" + config BSP_NODIE_ADC2_PINNAME + string "Pin name for VIN2 in No-die Domain" + default "" + config BSP_NODIE_ADC3_PINNAME + string "Pin name for VIN3 in No-die Domain" + default "" + endif + endif + config BSP_USING_SPI bool "Using SPI" select RT_USING_SPI diff --git a/bsp/cvitek/cv18xx_risc-v/board/Kconfig b/bsp/cvitek/cv18xx_risc-v/board/Kconfig index 6ed5c54e74..93ce4221c5 100755 --- a/bsp/cvitek/cv18xx_risc-v/board/Kconfig +++ b/bsp/cvitek/cv18xx_risc-v/board/Kconfig @@ -154,11 +154,45 @@ menu "General Drivers Configuration" default 49 endif - config BSP_USING_ADC + menuconfig BSP_USING_ADC bool "Using ADC" select RT_USING_ADC default n + if BSP_USING_ADC + config BSP_USING_ADC_ACTIVE + bool "Enable ADC Controller in Active Domain" + default n + + if BSP_USING_ADC_ACTIVE + config BSP_ACTIVE_ADC1_PINNAME + string "Pin name for VIN1 in Active Domain" + default "" + config BSP_ACTIVE_ADC2_PINNAME + string "Pin name for VIN2 in Active Domain" + default "" + config BSP_ACTIVE_ADC3_PINNAME + string "Pin name for VIN3 in Active Domain" + default "" + endif + + config BSP_USING_ADC_NODIE + bool "Enable ADC Controller in No-die Domain" + default n + + if BSP_USING_ADC_NODIE + config BSP_NODIE_ADC1_PINNAME + string "Pin name for VIN1 in No-die Domain" + default "" + config BSP_NODIE_ADC2_PINNAME + string "Pin name for VIN2 in No-die Domain" + default "" + config BSP_NODIE_ADC3_PINNAME + string "Pin name for VIN3 in No-die Domain" + default "" + endif + endif + config BSP_USING_SPI bool "Using SPI" select RT_USING_SPI diff --git a/bsp/cvitek/drivers/drv_adc.c b/bsp/cvitek/drivers/drv_adc.c index 242d2216eb..f5f179fed1 100644 --- a/bsp/cvitek/drivers/drv_adc.c +++ b/bsp/cvitek/drivers/drv_adc.c @@ -10,6 +10,7 @@ #include #include #include "drv_adc.h" +#include "drv_pinmux.h" #define DBG_LEVEL DBG_LOG #include @@ -100,10 +101,101 @@ static const struct rt_adc_ops _adc_ops = .convert = _adc_convert, }; + +#if defined(BOARD_TYPE_MILKV_DUO) || defined(BOARD_TYPE_MILKV_DUO_SPINOR) + +/* + * cv180xb supports + * - adc1 & adc2 for active domain + * - adc3 for no-die domain + * + * FIXME: currnet adc driver only support adc1 in active domain + */ +#ifdef BSP_USING_ADC_ACTIVE +static const char *pinname_whitelist_adc1_active[] = { + "ADC1", + NULL, +}; +static const char *pinname_whitelist_adc2_active[] = { + NULL, +}; +static const char *pinname_whitelist_adc3_active[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_ADC_NODIE +static const char *pinname_whitelist_adc1_nodie[] = { + NULL, +}; +static const char *pinname_whitelist_adc2_nodie[] = { + NULL, +}; +static const char *pinname_whitelist_adc3_nodie[] = { + NULL, +}; +#endif + +#elif defined(BOARD_TYPE_MILKV_DUO256M) || defined(BOARD_TYPE_MILKV_DUO256M_SPINOR) + +/* + * sg2002 supports + * - adc1 for active domain + * - adc1/adc2/adc3 for no-die domain + * + * FIXME: currnet adc driver only support adc1 in active domain + */ + +#ifdef BSP_USING_ADC_ACTIVE +static const char *pinname_whitelist_adc1_active[] = { + "ADC1", + NULL, +}; +static const char *pinname_whitelist_adc2_active[] = { + NULL, +}; +static const char *pinname_whitelist_adc3_active[] = { + NULL, +}; +#endif + +#ifdef BSP_USING_ADC_NODIE +static const char *pinname_whitelist_adc1_nodie[] = { + NULL, +}; +static const char *pinname_whitelist_adc2_nodie[] = { + NULL, +}; +static const char *pinname_whitelist_adc3_nodie[] = { + NULL, +}; +#endif + +#else + #error "Unsupported board type!" +#endif + +static void rt_hw_adc_pinmux_config() +{ +#ifdef BSP_USING_ADC_ACTIVE + pinmux_config(BSP_ACTIVE_ADC1_PINNAME, XGPIOB_3, pinname_whitelist_adc1_active); + pinmux_config(BSP_ACTIVE_ADC2_PINNAME, XGPIOB_6, pinname_whitelist_adc2_active); + /* cv1800b & sg2002 don't support ADC3 either in active domain */ +#endif + +#ifdef BSP_USING_ADC_NODIE + pinmux_config(BSP_NODIE_ADC1_PINNAME, PWR_GPIO_2, pinname_whitelist_adc1_nodie); + pinmux_config(BSP_NODIE_ADC2_PINNAME, PWR_GPIO_1, pinname_whitelist_adc2_nodie); + pinmux_config(BSP_NODIE_ADC3_PINNAME, PWR_VBAT_DET, pinname_whitelist_adc3_nodie); +#endif +} + int rt_hw_adc_init(void) { rt_uint8_t i; + rt_hw_adc_pinmux_config(); + for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++) { cvi_do_calibration(adc_dev_config[i].base); From 1d78d11567bc2187d10ca94e63c39cc95ff1195d Mon Sep 17 00:00:00 2001 From: Shell Date: Tue, 16 Jul 2024 20:38:55 +0800 Subject: [PATCH 13/14] [smart] feat: add unmap for null mapper (#9186) Do unmap before shrink so we don't see mapped entry on page table insertion, which is not acceptable for riscv implementation of architecture porting. Changes: - add un-mapping of pte on `_null_shrink()` Signed-off-by: Shell --- components/lwp/lwp_user_mm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c index 01640d5a07..18f10e176f 100644 --- a/components/lwp/lwp_user_mm.c +++ b/components/lwp/lwp_user_mm.c @@ -70,11 +70,29 @@ static void _null_page_fault(struct rt_varea *varea, static rt_err_t _null_shrink(rt_varea_t varea, void *new_start, rt_size_t size) { + char *varea_start = varea->start; + void *rm_start; + void *rm_end; + + if (varea_start == (char *)new_start) + { + rm_start = varea_start + size; + rm_end = varea_start + varea->size; + } + else /* if (varea_start < (char *)new_start) */ + { + RT_ASSERT(varea_start < (char *)new_start); + rm_start = varea_start; + rm_end = new_start; + } + + rt_varea_unmap_range(varea, rm_start, rm_end - rm_start); return RT_EOK; } static rt_err_t _null_split(struct rt_varea *existed, void *unmap_start, rt_size_t unmap_len, struct rt_varea *subset) { + rt_varea_unmap_range(existed, unmap_start, unmap_len); return RT_EOK; } From 4ad194bb47101345ce3b3fa631ab2215a0c190c0 Mon Sep 17 00:00:00 2001 From: zhuzhuzhu <945386260@qq.com> Date: Wed, 17 Jul 2024 09:08:10 +0800 Subject: [PATCH 14/14] [fix] fix cromfs read out of mem range (#9197) Update dfs_cromfs.c --- components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c b/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c index 0d82914df4..ae67887a4d 100644 --- a/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c +++ b/components/dfs/dfs_v2/filesystems/cromfs/dfs_cromfs.c @@ -786,18 +786,18 @@ static ssize_t dfs_cromfs_read(struct dfs_file *file, void *buf, size_t count, o rt_err_t result = RT_EOK; file_info *fi = NULL; cromfs_info *ci = NULL; - uint32_t length = 0; + ssize_t length = 0; ci = (cromfs_info *)file->dentry->mnt->data; fi = (file_info *)file->vnode->data; - if (count < file->vnode->size - *pos) + if ((off_t)count < (off_t)file->vnode->size - *pos) { length = count; } else { - length = file->vnode->size - *pos; + length = (off_t)file->vnode->size - *pos; } if (length > 0)