[bsp/ifx] add cyw43012 wifi module
This commit is contained in:
guozhanxin
Meco Man
parent
f307a2cd5d
commit
f53fc15f03
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@ -78,7 +78,6 @@ if GetDepend(['SOC_CY8C6244LQI_S4D92']):
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src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
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if GetDepend(['RT_USING_SERIAL']):
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src += ['retarget-io/cy_retarget_io.c']
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src += ['mtb-hal-cat1/source/cyhal_uart.c']
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src += ['mtb-pdl-cat1/drivers/source/cy_scb_uart.c']
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@ -93,7 +92,7 @@ if GetDepend(['RT_USING_ADC']):
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src += ['mtb-pdl-cat1/drivers/source/cy_dmac.c']
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src += ['mtb-pdl-cat1/drivers/source/cy_sysanalog.c']
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if GetDepend(['RT_USING_SDIO']):
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if GetDepend(['RT_USING_SDIO']) or GetDepend(['BSP_USING_CYW43012_WIFI']):
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src += ['mtb-hal-cat1/source/cyhal_sdhc.c']
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src += ['mtb-pdl-cat1/drivers/source/cy_sd_host.c']
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@ -1 +0,0 @@
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docs
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@ -1,55 +0,0 @@
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@ -1,38 +0,0 @@
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# Retarget IO
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|
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### Overview
|
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|
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A utility library to retarget the standard input/output (STDIO) messages to a UART port. With this library, you can directly print messages on a UART terminal using `printf()`. You can specify the TX pin, RX pin, and the baud rate through the `cy_retarget_io_init()` function. The UART HAL object is externally accessible so that you can use it with other UART HAL functions.
|
||||
|
||||
**NOTE:** The standard library is not standard in how it treats an I/O stream. Some implement a data buffer by default. The buffer is not flushed until it is full. In that case it may appear that your I/O is not working. You should be aware of how the library buffers data, and you should identify a buffering strategy and buffer size for a specified stream. If you supply a buffer, it must exist until the stream is closed. The following line of code disables the buffer for the standard library that accompanies the GCC compiler:
|
||||
|
||||
setvbuf( stdin, NULL, _IONBF, 0 );
|
||||
|
||||
**NOTE:** If the application is built using newlib-nano, by default, floating point format strings (%f) are not supported. To enable this support, you must add `-u _printf_float` to the linker command line.
|
||||
|
||||
# RTOS Integration
|
||||
To avoid concurrent access to the UART peripheral in a RTOS environment, the ARM and IAR libraries use mutexes to control access to stdio streams. For Newlib (GCC_ARM), the mutex must be implemented in _write() and can be enabled by adding `DEFINES+=CY_RTOS_AWARE` to the Makefile. For all libraries, the program must start the RTOS kernel before calling any stdio functions.
|
||||
|
||||
### Quick Start
|
||||
1. Add `#include "cy_retarget_io.h"`
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||||
2. Call `cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);`
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||||
|
||||
`CYBSP_DEBUG_UART_TX` and `CYBSP_DEBUG_UART_RX` pins are defined in the BSP and `CY_RETARGET_IO_BAUDRATE` is set to 115200. You can use a different baud rate if you prefer.
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3. Start printing using `printf()`
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### Enabling Conversion of '\\n' into "\r\n"
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If you want to use only '\\n' instead of "\r\n" for printing a new line using printf(), define the macro `CY_RETARGET_IO_CONVERT_LF_TO_CRLF` using the *DEFINES* variable in the application Makefile. The library will then append '\\r' before '\\n' character on the output direction (STDOUT). No conversion occurs if "\r\n" is already present.
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||||
### More information
|
||||
|
||||
* [API Reference Guide](https://infineon.github.io/retarget-io/html/index.html)
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||||
* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
|
||||
* [Infineon GitHub](https://github.com/infineon)
|
||||
* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
|
||||
* [PSoC™ 6 Code Examples using ModusToolbox™ IDE](https://github.com/infineon/Code-Examples-for-ModusToolbox-Software)
|
||||
* [ModusToolbox™ Software](https://github.com/Infineon/modustoolbox-software)
|
||||
* [PSoC™ 6 Resources - KBA223067](https://community.cypress.com/docs/DOC-14644)
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||||
|
||||
---
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||||
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2021.
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|
|
@ -1,49 +0,0 @@
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|||
# Retarget IO
|
||||
|
||||
A utility library to retarget the standard input/output (STDIO) messages to a UART port. With this library, you can directly print messages on a UART terminal using `printf()`.
|
||||
|
||||
### What's Included?
|
||||
* printf() support over a UART terminal
|
||||
* Support for GCC, IAR, and ARM toolchains
|
||||
* Thread safe write for NewLib
|
||||
|
||||
### What Changed?
|
||||
#### v1.3.0
|
||||
* Added support for checking whether data is being transmitted and waiting until done before finishing the deinit process
|
||||
* Added support for using with HAL v1 or v2
|
||||
#### v1.2.0
|
||||
* Improve error handling
|
||||
* Add de-initialization of the mutex to `cy_retarget_io_deinit`
|
||||
* Update documentation for integration of the library in a RTOS environment.
|
||||
#### v1.1.1
|
||||
* Minor update for documentation & branding
|
||||
#### v1.1.0
|
||||
* Implemented system I/O retarget functions specific to ARM Compiler 6.
|
||||
* Made _write implementation thread-safe for Newlib.
|
||||
#### v1.0.0
|
||||
* Initial release
|
||||
|
||||
### Supported Software and Tools
|
||||
This version of the Retarget IO was validated for compatibility with the following Software and Tools:
|
||||
|
||||
| Software and Tools | Version |
|
||||
| :--- | :----: |
|
||||
| ModusToolbox™ Software Environment | 2.4.0 |
|
||||
| GCC Compiler | 10.3.1 |
|
||||
| IAR Compiler | 8.4 |
|
||||
| ARM Compiler 6 | 6.11 |
|
||||
|
||||
Minimum required ModusToolbox™ Software Environment: v2.0
|
||||
|
||||
### More information
|
||||
|
||||
* [API Reference Guide](https://infineon.github.io/retarget-io/html/index.html)
|
||||
* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
|
||||
* [Infineon GitHub](https://github.com/infineon)
|
||||
* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
|
||||
* [PSoC™ 6 Code Examples using ModusToolbox™ IDE](https://github.com/infineon/Code-Examples-for-ModusToolbox-Software)
|
||||
* [ModusToolbox™ Software](https://github.com/Infineon/modustoolbox-software)
|
||||
* [PSoC™ 6 Resources - KBA223067](https://community.cypress.com/docs/DOC-14644)
|
||||
|
||||
---
|
||||
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2021.
|
||||
|
|
@ -1,603 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy_retarget_io.c
|
||||
*
|
||||
* \brief
|
||||
* Provides APIs for retargeting stdio to UART hardware contained on the Cypress
|
||||
* kits.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
#include "cy_retarget_io.h"
|
||||
#include "cyhal_hw_types.h"
|
||||
#include "cyhal_uart.h"
|
||||
#include "cy_utils.h"
|
||||
#include "cyhal_system.h"
|
||||
#include <stdbool.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#if (defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)) && defined(__GNUC__) && \
|
||||
!defined(__ARMCC_VERSION) && !defined(__clang__)
|
||||
|
||||
// The cyhal_uart driver is not necessarily thread-safe. To avoid concurrent
|
||||
// access, the ARM and IAR libraries use mutexes to control access to stdio
|
||||
// streams. For Newlib, the mutex must be implemented in _write(). For all
|
||||
// libraries, the program must start the RTOS kernel before calling any stdio
|
||||
// functions.
|
||||
|
||||
#include "cyabs_rtos.h"
|
||||
|
||||
static cy_mutex_t cy_retarget_io_mutex;
|
||||
static bool cy_retarget_io_mutex_initialized = false;
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_mutex_init
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static cy_rslt_t cy_retarget_io_mutex_init(void)
|
||||
{
|
||||
cy_rslt_t rslt;
|
||||
if (cy_retarget_io_mutex_initialized)
|
||||
{
|
||||
rslt = CY_RSLT_SUCCESS;
|
||||
}
|
||||
else if (CY_RSLT_SUCCESS == (rslt = cy_rtos_init_mutex(&cy_retarget_io_mutex)))
|
||||
{
|
||||
cy_retarget_io_mutex_initialized = true;
|
||||
}
|
||||
return rslt;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_mutex_acquire
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static void cy_retarget_io_mutex_acquire(void)
|
||||
{
|
||||
CY_ASSERT(cy_retarget_io_mutex_initialized);
|
||||
cy_rslt_t rslt = cy_rtos_get_mutex(&cy_retarget_io_mutex, CY_RTOS_NEVER_TIMEOUT);
|
||||
if (rslt != CY_RSLT_SUCCESS)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_mutex_release
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static void cy_retarget_io_mutex_release(void)
|
||||
{
|
||||
CY_ASSERT(cy_retarget_io_mutex_initialized);
|
||||
cy_rslt_t rslt = cy_rtos_set_mutex(&cy_retarget_io_mutex);
|
||||
if (rslt != CY_RSLT_SUCCESS)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_mutex_deinit
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static void cy_retarget_io_mutex_deinit(void)
|
||||
{
|
||||
CY_ASSERT(cy_retarget_io_mutex_initialized);
|
||||
cy_rslt_t rslt = cy_rtos_deinit_mutex(&cy_retarget_io_mutex);
|
||||
if (rslt != CY_RSLT_SUCCESS)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#else // if (defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)) && defined(__GNUC__) &&
|
||||
// !defined(__ARMCC_VERSION) && !defined(__clang__)
|
||||
#ifdef __ICCARM__
|
||||
// Ignore unused functions
|
||||
#pragma diag_suppress=Pe177
|
||||
#endif
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_mutex_init
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static inline cy_rslt_t cy_retarget_io_mutex_init(void)
|
||||
{
|
||||
return CY_RSLT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) // ARM-MDK
|
||||
__attribute__((unused))
|
||||
#endif
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_mutex_acquire
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static inline void cy_retarget_io_mutex_acquire(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) // ARM-MDK
|
||||
__attribute__((unused))
|
||||
#endif
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_mutex_release
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static inline void cy_retarget_io_mutex_release(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) // ARM-MDK
|
||||
__attribute__((unused))
|
||||
#endif
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_mutex_deinit
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static inline void cy_retarget_io_mutex_deinit(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
#endif // if (defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)) && defined(__GNUC__) &&
|
||||
// !defined(__ARMCC_VERSION) && !defined(__clang__)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// UART HAL object used by BSP for Debug UART port
|
||||
cyhal_uart_t cy_retarget_io_uart_obj;
|
||||
|
||||
// Tracks the previous character sent to output stream
|
||||
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
static char cy_retarget_io_stdout_prev_char = 0;
|
||||
#endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_getchar
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static inline cy_rslt_t cy_retarget_io_getchar(char* c)
|
||||
{
|
||||
return cyhal_uart_getc(&cy_retarget_io_uart_obj, (uint8_t*)c, 0);
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_putchar
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
static inline cy_rslt_t cy_retarget_io_putchar(char c)
|
||||
{
|
||||
return cyhal_uart_putc(&cy_retarget_io_uart_obj, (uint8_t)c);
|
||||
}
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) // ARM-MDK
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// fputc
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
__attribute__((weak)) int fputc(int ch, FILE* f)
|
||||
{
|
||||
(void)f;
|
||||
cy_rslt_t rslt = CY_RSLT_SUCCESS;
|
||||
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
if (((char)ch == '\n') && (cy_retarget_io_stdout_prev_char != '\r'))
|
||||
{
|
||||
rslt = cy_retarget_io_putchar('\r');
|
||||
}
|
||||
#endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
|
||||
if (CY_RSLT_SUCCESS == rslt)
|
||||
{
|
||||
rslt = cy_retarget_io_putchar(ch);
|
||||
}
|
||||
|
||||
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
if (CY_RSLT_SUCCESS == rslt)
|
||||
{
|
||||
cy_retarget_io_stdout_prev_char = (char)ch;
|
||||
}
|
||||
#endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
|
||||
return (CY_RSLT_SUCCESS == rslt) ? ch : EOF;
|
||||
}
|
||||
|
||||
|
||||
#elif defined (__ICCARM__) // IAR
|
||||
#include <yfuns.h>
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// __write
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
__weak size_t __write(int handle, const unsigned char* buffer, size_t size)
|
||||
{
|
||||
size_t nChars = 0;
|
||||
// This template only writes to "standard out", for all other file handles it returns failure.
|
||||
if (handle != _LLIO_STDOUT)
|
||||
{
|
||||
return (_LLIO_ERROR);
|
||||
}
|
||||
if (buffer != NULL)
|
||||
{
|
||||
cy_rslt_t rslt = CY_RSLT_SUCCESS;
|
||||
for (; nChars < size; ++nChars)
|
||||
{
|
||||
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
if ((*buffer == '\n') && (cy_retarget_io_stdout_prev_char != '\r'))
|
||||
{
|
||||
rslt = cy_retarget_io_putchar('\r');
|
||||
}
|
||||
#endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
|
||||
if (rslt == CY_RSLT_SUCCESS)
|
||||
{
|
||||
rslt = cy_retarget_io_putchar(*buffer);
|
||||
}
|
||||
|
||||
if (rslt != CY_RSLT_SUCCESS)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
cy_retarget_io_stdout_prev_char = *buffer;
|
||||
#endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
++buffer;
|
||||
}
|
||||
}
|
||||
return (nChars);
|
||||
}
|
||||
|
||||
|
||||
#else // (__GNUC__) GCC
|
||||
// Add an explicit reference to the floating point printf library to allow the usage of floating
|
||||
// point conversion specifier.
|
||||
__asm(".global _printf_float");
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _write
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
__attribute__((weak)) int _write(int fd, const char* ptr, int len)
|
||||
{
|
||||
int nChars = 0;
|
||||
(void)fd;
|
||||
if (ptr != NULL)
|
||||
{
|
||||
cy_rslt_t rslt = CY_RSLT_SUCCESS;
|
||||
cy_retarget_io_mutex_acquire();
|
||||
for (; nChars < len; ++nChars)
|
||||
{
|
||||
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
if ((*ptr == '\n') && (cy_retarget_io_stdout_prev_char != '\r'))
|
||||
{
|
||||
rslt = cy_retarget_io_putchar('\r');
|
||||
}
|
||||
#endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
|
||||
if (CY_RSLT_SUCCESS == rslt)
|
||||
{
|
||||
rslt = cy_retarget_io_putchar((uint32_t)*ptr);
|
||||
}
|
||||
|
||||
if (CY_RSLT_SUCCESS != rslt)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
cy_retarget_io_stdout_prev_char = *ptr;
|
||||
#endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
++ptr;
|
||||
}
|
||||
cy_retarget_io_mutex_release();
|
||||
}
|
||||
return (nChars);
|
||||
}
|
||||
|
||||
|
||||
#endif // if defined(__ARMCC_VERSION)
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) // ARM-MDK
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// fgetc
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
__attribute__((weak)) int fgetc(FILE* f)
|
||||
{
|
||||
(void)f;
|
||||
char c;
|
||||
cy_rslt_t rslt = cy_retarget_io_getchar(&c);
|
||||
return (CY_RSLT_SUCCESS == rslt) ? c : EOF;
|
||||
}
|
||||
|
||||
|
||||
#elif defined (__ICCARM__) // IAR
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// __read
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
__weak size_t __read(int handle, unsigned char* buffer, size_t size)
|
||||
{
|
||||
// This template only reads from "standard in", for all other file handles it returns failure.
|
||||
if ((handle != _LLIO_STDIN) || (buffer == NULL))
|
||||
{
|
||||
return (_LLIO_ERROR);
|
||||
}
|
||||
else
|
||||
{
|
||||
cy_rslt_t rslt = cy_retarget_io_getchar((char*)buffer);
|
||||
return (CY_RSLT_SUCCESS == rslt) ? 1 : 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#else // (__GNUC__) GCC
|
||||
// Add an explicit reference to the floating point scanf library to allow the usage of floating
|
||||
// point conversion specifier.
|
||||
__asm(".global _scanf_float");
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _read
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
__attribute__((weak)) int _read(int fd, char* ptr, int len)
|
||||
{
|
||||
(void)fd;
|
||||
|
||||
cy_rslt_t rslt;
|
||||
int nChars = 0;
|
||||
if (ptr != NULL)
|
||||
{
|
||||
for (; nChars < len; ++ptr)
|
||||
{
|
||||
rslt = cy_retarget_io_getchar(ptr);
|
||||
if (rslt == CY_RSLT_SUCCESS)
|
||||
{
|
||||
++nChars;
|
||||
if ((*ptr == '\n') || (*ptr == '\r'))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return (nChars);
|
||||
}
|
||||
|
||||
|
||||
#endif // if defined(__ARMCC_VERSION)
|
||||
|
||||
#if defined(__ARMCC_VERSION) // ARM-MDK
|
||||
// Include _sys_* prototypes provided by ARM Compiler runtime library
|
||||
#include <rt_sys.h>
|
||||
|
||||
// Prevent linkage of library functions that use semihosting calls
|
||||
__asm(".global __use_no_semihosting\n\t");
|
||||
|
||||
// Enable the linker to select an optimized library that does not include code to handle input
|
||||
// arguments to main()
|
||||
__asm(".global __ARM_use_no_argv\n\t");
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _sys_open
|
||||
//
|
||||
// Open a file: dummy implementation.
|
||||
// Everything goes to the same output, no need to translate the file names
|
||||
// (__stdin_name/__stdout_name/__stderr_name) to descriptor numbers
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
FILEHANDLE __attribute__((weak)) _sys_open(const char* name, int openmode)
|
||||
{
|
||||
(void)name;
|
||||
(void)openmode;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _sys_close
|
||||
//
|
||||
// Close a file: dummy implementation.
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
int __attribute__((weak)) _sys_close(FILEHANDLE fh)
|
||||
{
|
||||
(void)fh;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _sys_write
|
||||
//
|
||||
// Write to a file: dummy implementation.
|
||||
// The low-level function fputc retargets output to use UART TX
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
int __attribute__((weak)) _sys_write(FILEHANDLE fh, const unsigned char* buf, unsigned len,
|
||||
int mode)
|
||||
{
|
||||
(void)fh;
|
||||
(void)buf;
|
||||
(void)len;
|
||||
(void)mode;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _sys_read
|
||||
//
|
||||
// Read from a file: dummy implementation.
|
||||
// The low-level function fputc retargets input to use UART RX
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
int __attribute__((weak)) _sys_read(FILEHANDLE fh, unsigned char* buf, unsigned len, int mode)
|
||||
{
|
||||
(void)fh;
|
||||
(void)buf;
|
||||
(void)len;
|
||||
(void)mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _ttywrch
|
||||
//
|
||||
// Write a character to the output channel: dummy implementation.
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
void __attribute__((weak)) _ttywrch(int ch)
|
||||
{
|
||||
(void)ch;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _sys_istty
|
||||
//
|
||||
// Check if the file is connected to a terminal: dummy implementation
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
int __attribute__((weak)) _sys_istty(FILEHANDLE fh)
|
||||
{
|
||||
(void)fh;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _sys_seek
|
||||
//
|
||||
// Move the file position to a given offset: dummy implementation
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
int __attribute__((weak)) _sys_seek(FILEHANDLE fh, long pos)
|
||||
{
|
||||
(void)fh;
|
||||
(void)pos;
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _sys_flen
|
||||
// Return the current length of a file: dummy implementation
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
long __attribute__((weak)) _sys_flen(FILEHANDLE fh)
|
||||
{
|
||||
(void)fh;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _sys_exit
|
||||
//
|
||||
// Terminate the program: dummy implementation
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
void __attribute__((weak)) _sys_exit(int returncode)
|
||||
{
|
||||
(void)returncode;
|
||||
for (;;)
|
||||
{
|
||||
// Halt here forever
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// _sys_command_string
|
||||
//
|
||||
// Return a pointer to the command line: dummy implementation
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
char __attribute__((weak)) *_sys_command_string(char* cmd, int len)
|
||||
{
|
||||
(void)cmd;
|
||||
(void)len;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
#endif // ARM-MDK
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_init
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
cy_rslt_t cy_retarget_io_init(cyhal_gpio_t tx, cyhal_gpio_t rx, uint32_t baudrate)
|
||||
{
|
||||
const cyhal_uart_cfg_t uart_config =
|
||||
{
|
||||
.data_bits = 8,
|
||||
.stop_bits = 1,
|
||||
.parity = CYHAL_UART_PARITY_NONE,
|
||||
.rx_buffer = NULL,
|
||||
.rx_buffer_size = 0
|
||||
};
|
||||
|
||||
#if (CYHAL_API_VERSION >= 2)
|
||||
cy_rslt_t result =
|
||||
cyhal_uart_init(&cy_retarget_io_uart_obj, tx, rx, NC, NC, NULL, &uart_config);
|
||||
#else // HAL API version 1
|
||||
cy_rslt_t result = cyhal_uart_init(&cy_retarget_io_uart_obj, tx, rx, NULL, &uart_config);
|
||||
#endif
|
||||
|
||||
if (result == CY_RSLT_SUCCESS)
|
||||
{
|
||||
result = cyhal_uart_set_baud(&cy_retarget_io_uart_obj, baudrate, NULL);
|
||||
}
|
||||
|
||||
if (result == CY_RSLT_SUCCESS)
|
||||
{
|
||||
result = cy_retarget_io_mutex_init();
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_is_tx_active
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
bool cy_retarget_io_is_tx_active()
|
||||
{
|
||||
return cyhal_uart_is_tx_active(&cy_retarget_io_uart_obj);
|
||||
}
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// cy_retarget_io_deinit
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
void cy_retarget_io_deinit(void)
|
||||
{
|
||||
// Since the largest hardware buffer would be 256 bytes
|
||||
// it takes about 500 ms to transmit the 256 bytes at 9600 baud.
|
||||
// Thus 1000 ms gives roughly 50% padding to this time.
|
||||
int timeout_remaining_ms = 1000;
|
||||
while (timeout_remaining_ms > 0)
|
||||
{
|
||||
if (!cy_retarget_io_is_tx_active())
|
||||
{
|
||||
break;
|
||||
}
|
||||
cyhal_system_delay_ms(1);
|
||||
timeout_remaining_ms--;
|
||||
}
|
||||
CY_ASSERT(timeout_remaining_ms != 0);
|
||||
cyhal_uart_free(&cy_retarget_io_uart_obj);
|
||||
cy_retarget_io_mutex_deinit();
|
||||
}
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,99 +0,0 @@
|
|||
/***********************************************************************************************//**
|
||||
* \file cy_retarget_io.h
|
||||
*
|
||||
* \brief
|
||||
* Provides APIs for transmitting messages to or from the board via standard
|
||||
* printf/scanf functions. Messages are transmitted over a UART connection which
|
||||
* is generally connected to a host machine. Transmission is done at 115200 baud
|
||||
* using the tx and rx pins provided by the user of this library. The UART
|
||||
* instance is made available via cy_retarget_io_uart_obj in case any changes
|
||||
* to the default configuration are desired.
|
||||
* NOTE: If the application is built using newlib-nano, by default, floating
|
||||
* point format strings (%f) are not supported. To enable this support you must
|
||||
* add '-u _printf_float' to the linker command line.
|
||||
*
|
||||
***************************************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
**************************************************************************************************/
|
||||
|
||||
/**
|
||||
* \addtogroup group_board_libs Retarget IO
|
||||
* \{
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdio.h>
|
||||
#include "cy_result.h"
|
||||
#include "cyhal_hw_types.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** UART HAL object used by this library */
|
||||
extern cyhal_uart_t cy_retarget_io_uart_obj;
|
||||
|
||||
/** UART baud rate */
|
||||
#define CY_RETARGET_IO_BAUDRATE (115200)
|
||||
|
||||
#ifdef DOXYGEN
|
||||
|
||||
/** Defining this macro enables conversion of line feed (LF) into carriage
|
||||
* return followed by line feed (CR & LF) on the output direction (STDOUT). You
|
||||
* can define this macro through the DEFINES variable in the application
|
||||
* Makefile.
|
||||
*/
|
||||
#define CY_RETARGET_IO_CONVERT_LF_TO_CRLF
|
||||
|
||||
#endif // DOXYGEN
|
||||
|
||||
/**
|
||||
* \brief Initialization function for redirecting low level IO commands to allow
|
||||
* sending messages over a UART interface. This will setup the communication
|
||||
* interface to allow using printf and related functions.
|
||||
*
|
||||
* In an RTOS environment, this function must be called after the RTOS has been
|
||||
* initialized.
|
||||
*
|
||||
* \param tx UART TX pin
|
||||
* \param rx UART RX pin
|
||||
* \param baudrate UART baudrate
|
||||
* \returns CY_RSLT_SUCCESS if successfully initialized, else an error about
|
||||
* what went wrong
|
||||
*/
|
||||
cy_rslt_t cy_retarget_io_init(cyhal_gpio_t tx, cyhal_gpio_t rx, uint32_t baudrate);
|
||||
|
||||
/**
|
||||
* \brief Checks whether there is data waiting to be written to the serial console.
|
||||
* \returns true if there are pending TX transactions, otherwise false
|
||||
*/
|
||||
bool cy_retarget_io_is_tx_active();
|
||||
|
||||
/**
|
||||
* \brief Releases the UART interface allowing it to be used for other purposes.
|
||||
* After calling this, printf and related functions will no longer work.
|
||||
*/
|
||||
void cy_retarget_io_deinit(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \} group_board_libs */
|
||||
|
|
@ -1 +0,0 @@
|
|||
<version>1.3.0.25183</version>
|
||||
|
|
@ -13,7 +13,6 @@
|
|||
build
|
||||
Debug
|
||||
documentation/html
|
||||
packages/
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
|
|
|
|||
|
|
@ -372,53 +372,57 @@ menu "Board extended module Drivers"
|
|||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_RW007
|
||||
bool "Enable RW007"
|
||||
default n
|
||||
select PKG_USING_RW007
|
||||
select BSP_USING_SPI
|
||||
select BSP_USING_SPI0
|
||||
select RW007_NOT_USE_EXAMPLE_DRIVERS
|
||||
menuconfig BSP_USING_RW007
|
||||
bool "Enable RW007"
|
||||
default n
|
||||
select PKG_USING_RW007
|
||||
select BSP_USING_SPI
|
||||
select BSP_USING_SPI0
|
||||
select RW007_NOT_USE_EXAMPLE_DRIVERS
|
||||
|
||||
if BSP_USING_RW007
|
||||
comment "Notice: P5_7 --> 47; P5_6 -->46; P0_5 --> 5; P0_4 --> 4"
|
||||
config IFX_RW007_SPI_BUS_NAME
|
||||
string "RW007 BUS NAME"
|
||||
default "spi0"
|
||||
if BSP_USING_RW007
|
||||
comment "Notice: P5_7 --> 47; P5_6 -->46; P0_5 --> 5; P0_4 --> 4"
|
||||
config IFX_RW007_SPI_BUS_NAME
|
||||
string "RW007 BUS NAME"
|
||||
default "spi0"
|
||||
|
||||
config IFX_RW007_WIFI_SSID
|
||||
string "Wi-Fi SSID"
|
||||
default "realthread_VIP"
|
||||
config IFX_RW007_WIFI_SSID
|
||||
string "Wi-Fi SSID"
|
||||
default "realthread_VIP"
|
||||
|
||||
config IFX_RW007_WIFI_PASSWORD
|
||||
string "Wi-Fi Password"
|
||||
default "your wifi password"
|
||||
config IFX_RW007_WIFI_PASSWORD
|
||||
string "Wi-Fi Password"
|
||||
default "your wifi password"
|
||||
|
||||
config IFX_RW007_CS_PIN
|
||||
int "(INT)CS pin index"
|
||||
range 1 113
|
||||
default 5
|
||||
config IFX_RW007_CS_PIN
|
||||
int "(INT)CS pin index"
|
||||
range 1 113
|
||||
default 5
|
||||
|
||||
config IFX_RW007_BOOT0_PIN
|
||||
int "(INT)BOOT0 pin index (same as spi clk pin)"
|
||||
range 1 113
|
||||
default 4
|
||||
config IFX_RW007_BOOT0_PIN
|
||||
int "(INT)BOOT0 pin index (same as spi clk pin)"
|
||||
range 1 113
|
||||
default 4
|
||||
|
||||
config IFX_RW007_BOOT1_PIN
|
||||
int "(INT)BOOT1 pin index (same as spi cs pin)"
|
||||
range 1 113
|
||||
default 5
|
||||
config IFX_RW007_BOOT1_PIN
|
||||
int "(INT)BOOT1 pin index (same as spi cs pin)"
|
||||
range 1 113
|
||||
default 5
|
||||
|
||||
config IFX_RW007_INT_BUSY_PIN
|
||||
int "(INT)INT/BUSY pin index"
|
||||
range 1 113
|
||||
default 47
|
||||
config IFX_RW007_INT_BUSY_PIN
|
||||
int "(INT)INT/BUSY pin index"
|
||||
range 1 113
|
||||
default 47
|
||||
|
||||
config IFX_RW007_RST_PIN
|
||||
int "(INT)RESET pin index"
|
||||
range 1 113
|
||||
default 46
|
||||
endif
|
||||
config IFX_RW007_RST_PIN
|
||||
int "(INT)RESET pin index"
|
||||
range 1 113
|
||||
default 46
|
||||
endif
|
||||
config BSP_USING_CYW43012_WIFI
|
||||
bool "Enable cyw43012 wifi"
|
||||
select PKG_USING_WLAN_CYW43012
|
||||
default n
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -19,6 +19,9 @@ if GetDepend(['BSP_USING_SPI3_SAMPLE']):
|
|||
if GetDepend(['BSP_USING_RW007']):
|
||||
src += Glob('ports/drv_rw007.c')
|
||||
|
||||
if GetDepend(['BSP_USING_CYW43012_WIFI']):
|
||||
src += Glob('ports/drv_cyw43012.c')
|
||||
|
||||
if GetDepend(['BSP_USING_SLIDER_SAMPLE']):
|
||||
src += Glob('ports/slider_sample.c')
|
||||
|
||||
|
|
@ -35,6 +38,14 @@ elif rtconfig.PLATFORM in ['armclang']:
|
|||
'/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_ext.S']
|
||||
|
||||
CPPDEFINES = ['CY8C624ALQI_S2D42', 'CORE_NAME_CM0P_0', 'CORE_NAME_CM4_0', 'CY_USING_PREBUILT_CM0P_IMAGE', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1']
|
||||
|
||||
if GetDepend(['BSP_USING_CYW43012_WIFI']):
|
||||
CPPDEFINES += [
|
||||
"COMPONENT_WIFI_INTERFACE_SDIO",
|
||||
"CYBSP_WIFI_CAPABLE",
|
||||
"CY_RTOS_AWARE",
|
||||
"CY_SUPPORTS_DEVICE_VALIDATION",
|
||||
]
|
||||
group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
#include <rtthread.h>
|
||||
#include <rtdbg.h>
|
||||
#ifdef BSP_USING_CYW43012_WIFI
|
||||
#include <rtdevice.h>
|
||||
|
||||
int wifi_cyw43012_device_init(void)
|
||||
{
|
||||
rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
|
||||
rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_APP_EXPORT(wifi_cyw43012_device_init);
|
||||
|
||||
|
||||
#endif /* BSP_USING_CYW43012_WIFI */
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
# files format check exclude path, please follow the instructions below to modify;
|
||||
# If you need to exclude an entire folder, add the folder path in dir_path;
|
||||
# If you need to exclude a file, add the path to the file in file_path.
|
||||
|
||||
dir_path:
|
||||
- TARGET_RTT-062S2
|
||||
|
|
@ -287,7 +287,7 @@ Reset_Handler:
|
|||
bl SystemInit
|
||||
#endif
|
||||
|
||||
bl entry
|
||||
bl main
|
||||
|
||||
/* Should never get here */
|
||||
b .
|
||||
|
|
|
|||
|
|
@ -114,8 +114,6 @@ uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT,
|
|||
|
||||
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
|
||||
|
||||
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
|
||||
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
|
||||
|
||||
/*******************************************************************************
|
||||
* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
|
||||
|
|
@ -258,7 +256,7 @@ void SystemCoreClockUpdate (void)
|
|||
/* Sets clock frequency for Delay API */
|
||||
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
|
||||
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
|
||||
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
|
||||
|
||||
/* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
|
||||
cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -101,8 +101,6 @@ uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT,
|
|||
|
||||
uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
|
||||
|
||||
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
|
||||
CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
|
|
@ -252,7 +250,7 @@ void SystemCoreClockUpdate (void)
|
|||
/* Sets clock frequency for Delay API */
|
||||
cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
|
||||
cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
|
||||
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
|
||||
|
||||
/* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
|
||||
cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,74 @@
|
|||
# CY8CKIT-062S2-43012 BSP
|
||||
|
||||
## Overview
|
||||
|
||||
The CY8CKIT-062S2-43012 PSoC™ 6S2 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC™ 6 MCUs. It comes with a Murata 1LV Module (CYW43012 Wi-Fi + Bluetooth Combo Chip), industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface.
|
||||
|
||||
|
||||
|
||||
To use code from the BSP, simply include a reference to `cybsp.h`.
|
||||
|
||||
## Features
|
||||
|
||||
### Kit Features:
|
||||
|
||||
* Support of up to 2MB Flash and 1MB SRAM
|
||||
* Dedicated SDHC to interface with WICED wireless devices.
|
||||
* Delivers dual-cores, with a 150-MHz Arm® Cortex®-M4 as the primary application processor and a 100-MHz Arm® Cortex®-M0+ as the secondary processor for low-power operations.
|
||||
* Supports Full-Speed USB, capacitive-sensing with CAPSENSE, a PDM-PCM digital microphone interface, a Quad- SPI interface, 13 serial communication blocks, 7 programmable analog blocks, and 56 programmable digital blocks.
|
||||
|
||||
### Kit Contents:
|
||||
|
||||
* PSoC™ 6S2 Wi-Fi BT Pioneer Board
|
||||
* USB Type-A to Micro-B cable
|
||||
* Quick Start Guide
|
||||
* Four jumper wires (4 inches each)
|
||||
* Two jumper wires (5 inches each)
|
||||
|
||||
## BSP Configuration
|
||||
|
||||
The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CKIT-062S2-43012.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.
|
||||
|
||||
Components:
|
||||
* Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board.
|
||||
|
||||
Defines:
|
||||
* CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one.
|
||||
* CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers.
|
||||
* CYBSP_CUSTOM_SYSCLK_PM_CALLBACK - This define, disabled by default, causes the BSP to skip registering its default SysClk Power Management callback, if any, and instead to invoke the application-defined function `cybsp_register_custom_sysclk_pm_callback` to register an application-specific callback.
|
||||
|
||||
### Clock Configuration
|
||||
|
||||
| Clock | Source | Output Frequency |
|
||||
|----------|-----------|------------------|
|
||||
| FLL | IMO | 100.0 MHz |
|
||||
| PLL | IMO | 48.0 MHz |
|
||||
| CLK_HF0 | CLK_PATH0 | 100 MHz |
|
||||
|
||||
### Power Configuration
|
||||
|
||||
* System Active Power Mode: LP
|
||||
* System Idle Power Mode: Deep Sleep
|
||||
* VDDA Voltage: 3300 mV
|
||||
* VDDD Voltage: 3300 mV
|
||||
|
||||
See the [BSP Setttings][settings] for additional board specific configuration settings.
|
||||
|
||||
## API Reference Manual
|
||||
|
||||
The CY8CKIT-062S2-43012 Board Support Package provides a set of APIs to configure, initialize and use the board resources.
|
||||
|
||||
See the [BSP API Reference Manual][api] for the complete list of the provided interfaces.
|
||||
|
||||
## More information
|
||||
* [CY8CKIT-062S2-43012 BSP API Reference Manual][api]
|
||||
* [CY8CKIT-062S2-43012 Documentation](http://www.cypress.com/CY8CKIT-062S2-43012)
|
||||
* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
|
||||
* [Infineon GitHub](https://github.com/infineon)
|
||||
* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
|
||||
|
||||
[api]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/modules.html
|
||||
[settings]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/md_bsp_settings.html
|
||||
|
||||
---
|
||||
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2022.
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
# CY8CKIT-062S2-43012 BSP Release Notes
|
||||
The CY8CKIT-062S2-43012 PSoC™ 6S2 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC™ 6 MCUs. It comes with a Murata 1LV Module (CYW43012 Wi-Fi + Bluetooth Combo Chip), industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface.
|
||||
|
||||
NOTE: BSPs are versioned by family. This means that version 1.2.0 of any BSP in a family (eg: PSoC™ 6) will have the same software maturity level. However, not all updates are necessarily applicable for each BSP in the family so not all version numbers will exist for each board. Additionally, new BSPs may not start at version 1.0.0. In the event of adding a common feature across all BSPs, the libraries are assigned the same version number. For example if BSP_A is at v1.3.0 and BSP_B is at v1.2.0, the event will trigger a version update to v1.4.0 for both BSP_A and BSP_B. This allows the common feature to be tracked in a consistent way.
|
||||
|
||||
### What's Included?
|
||||
The CY8CKIT-062S2-43012 library includes the following:
|
||||
* BSP specific makefile to configure the build process for the board
|
||||
* cybsp.c/h files to initialize the board and any system peripherals
|
||||
* cybsp_types.h file describing basic board setup
|
||||
* CM4 Linker script & startup code for GCC, IAR, and ARM toolchains
|
||||
* CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
|
||||
* Configurator design files (and generated code) to setup board specific peripherals
|
||||
* .lib file references for all dependent libraries
|
||||
* API documentation
|
||||
|
||||
### What Changed?
|
||||
#### v4.2.0
|
||||
* Updated linker scripts and startup code to align with mtb-pdl-cat1 v3.4.0
|
||||
* Added functionality to enable BSP Assistant chip flow
|
||||
* Added capabilities to match BSPS created by BSP Assistant chip flow
|
||||
#### v4.1.0
|
||||
* Add macro `CYBSP_USER_BTN_DRIVE` indicating the drive mode that should be used for user buttons
|
||||
* PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TFM.
|
||||
#### v4.0.0
|
||||
Note: This revision is only compatible with ModusToolbox Tools 3.0 and newer.
|
||||
* Removed default dependency on CAPSENSE™ middleware. The library manager can be used to add this dependency if desired.
|
||||
* Updated recipe-make, core-make, and PDL to new major versions
|
||||
* Regenerated code with Configurators from ModusToolbox™ v3.0.0
|
||||
* Renamed top level board makefile to bsp.mk
|
||||
* Removed version.xml file in favor of new props.json
|
||||
#### v3.1.0
|
||||
* Added optional macro CYBSP_CUSTOM_SYSCLK_PM_CALLBACK to allow overriding default clock power management behavior.
|
||||
* Enable AIROC™ BLE stack for MCUs with an integrated BLE radio
|
||||
#### v3.0.0
|
||||
* Updated to HAL dependency to v2.0.0
|
||||
* Updated CAPSENSE™ dependency to v3.0.0
|
||||
* Regenerated code with Configurators from ModusToolbox™ v2.4.0
|
||||
#### v2.3.0
|
||||
* Add new connectivity components for easier board customization
|
||||
* Simplify BT configuration settings for boards that support it
|
||||
* Minor branding updates
|
||||
#### v2.2.0
|
||||
* Updated PSoC™ 64 linker sections to match secure policy settings
|
||||
* Minor documentation updates
|
||||
#### v2.1.0
|
||||
* Added component CAT1 to all boards
|
||||
* Added new components for connectivity chips
|
||||
* Added BT configuration settings for boards that support it
|
||||
* Minor documentation updates
|
||||
#### v2.0.1
|
||||
* Minor update to better handle when to include the SCL library in the build
|
||||
#### v2.0.0
|
||||
* Updated design files and GeneratedSource with ModusToolbox™ 2.2 release
|
||||
* Migrated pin definitions into design.modus file
|
||||
* Updated clock frequencies to 100 MHz (fast) / 50 MHz (slow)
|
||||
* Updated MPNs on some boards to non-obsolete parts
|
||||
* Switched psoc6pdl dependency to new mtb-pdl
|
||||
* Switched psoc6hal dependency to new mtb-hal
|
||||
* Switched psoc6make dependency to new core-make & recipe-make-cat1a
|
||||
NOTE: This version requires ModusToolbox™ tools 2.2 or later. This version is not backwards compatible with 1.X versions. Additional manual steps must be taken to successfully update a design using a 1.x version of the BSP to this version.
|
||||
#### v1.3.0
|
||||
* Minor update for documentation & branding
|
||||
* Updated design files to use latest personality files
|
||||
* Initialize VDDA voltage if set in configurator
|
||||
NOTE: This requires psoc6hal 1.3.0 or later
|
||||
#### v1.2.1
|
||||
* Added 43012/4343W/43438 component to appropriate BSPs
|
||||
* Added multi-image policy for secure (064) BSPs
|
||||
#### v1.2.0
|
||||
* Standardize version numbering for all boards in a family
|
||||
* Moved UDB SDIO implementation into its own library udb-sdio-whd library
|
||||
* Added call to setup HAL SysPM driver (requires HAL 1.2.0 or later)
|
||||
* Updated documentation
|
||||
NOTE: This requires psoc6hal 1.2.0 or later
|
||||
#### v1.1.0
|
||||
* Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core specific directories.
|
||||
* Minor updates to avoid potential warnings on some toolchains
|
||||
#### v1.0.1
|
||||
* Added pin references for the board's J2 Header (for appropriate boards)
|
||||
#### v1.0.0
|
||||
* Initial release
|
||||
|
||||
### Supported Software and Tools
|
||||
This version of the CY8CKIT-062S2-43012 BSP was validated for compatibility with the following Software and Tools:
|
||||
|
||||
| Software and Tools | Version |
|
||||
| :--- | :----: |
|
||||
| ModusToolbox™ Software Environment | 3.1.0 |
|
||||
| GCC Compiler | 12.2.1 |
|
||||
| IAR Compiler | 9.30.1 |
|
||||
| ARM Compiler | 6.16 |
|
||||
|
||||
Minimum required ModusToolbox™ Software Environment: v3.0.0
|
||||
|
||||
### More information
|
||||
* [CY8CKIT-062S2-43012 BSP API Reference Manual][api]
|
||||
* [CY8CKIT-062S2-43012 Documentation](http://www.cypress.com/CY8CKIT-062S2-43012)
|
||||
* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
|
||||
* [Infineon GitHub](https://github.com/infineon)
|
||||
* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
|
||||
|
||||
[api]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/modules.html
|
||||
|
||||
---
|
||||
© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2022.
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/***********************************************************************************************//**
|
||||
* \copyright
|
||||
* Copyright 2020-2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
**************************************************************************************************/
|
||||
|
||||
#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE)
|
||||
|
||||
#include "cybsp_bt_config.h"
|
||||
#include "cycfg_connectivity_bt.h"
|
||||
#include "wiced_bt_dev.h"
|
||||
|
||||
// Not all boards use all of these pins. Any that arn't defined we will fallback on No Connects.
|
||||
#if !defined(CYBSP_BT_POWER)
|
||||
#define CYBSP_BT_POWER (NC)
|
||||
#endif
|
||||
#if !defined(CYCFG_BT_DEV_WAKE_GPIO)
|
||||
#define CYCFG_BT_DEV_WAKE_GPIO (NC)
|
||||
#endif
|
||||
#if !defined(CYCFG_BT_HOST_WAKE_GPIO)
|
||||
#define CYCFG_BT_HOST_WAKE_GPIO (NC)
|
||||
#endif
|
||||
#if !defined(CYBSP_BT_UART_TX)
|
||||
#define CYBSP_BT_UART_TX (NC)
|
||||
#endif
|
||||
#if !defined(CYBSP_BT_UART_RX)
|
||||
#define CYBSP_BT_UART_RX (NC)
|
||||
#endif
|
||||
#if !defined(CYBSP_BT_UART_RTS)
|
||||
#define CYBSP_BT_UART_RTS (NC)
|
||||
#endif
|
||||
#if !defined(CYBSP_BT_UART_CTS)
|
||||
#define CYBSP_BT_UART_CTS (NC)
|
||||
#endif
|
||||
|
||||
const cybt_platform_config_t cybsp_bt_platform_cfg =
|
||||
{
|
||||
.hci_config =
|
||||
{
|
||||
.hci_transport = CYBT_HCI_UART,
|
||||
|
||||
.hci =
|
||||
{
|
||||
.hci_uart =
|
||||
{
|
||||
.uart_tx_pin = CYBSP_BT_UART_TX,
|
||||
.uart_rx_pin = CYBSP_BT_UART_RX,
|
||||
.uart_rts_pin = CYBSP_BT_UART_RTS,
|
||||
.uart_cts_pin = CYBSP_BT_UART_CTS,
|
||||
|
||||
.baud_rate_for_fw_download = CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD,
|
||||
.baud_rate_for_feature = CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE,
|
||||
|
||||
.data_bits = CYBSP_BT_PLATFORM_CFG_BITS_DATA,
|
||||
.stop_bits = CYBSP_BT_PLATFORM_CFG_BITS_STOP,
|
||||
.parity = CYHAL_UART_PARITY_NONE,
|
||||
.flow_control = true
|
||||
}
|
||||
}
|
||||
},
|
||||
|
||||
.controller_config =
|
||||
{
|
||||
.bt_power_pin = CYBSP_BT_POWER,
|
||||
.sleep_mode =
|
||||
{
|
||||
.sleep_mode_enabled = CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED,
|
||||
.device_wakeup_pin = CYCFG_BT_DEV_WAKE_GPIO,
|
||||
.host_wakeup_pin = CYCFG_BT_HOST_WAKE_GPIO,
|
||||
.device_wake_polarity = CYCFG_BT_DEV_WAKE_POLARITY,
|
||||
.host_wake_polarity = CYCFG_BT_HOST_WAKE_IRQ_EVENT
|
||||
}
|
||||
},
|
||||
|
||||
.task_mem_pool_size = CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES
|
||||
};
|
||||
|
||||
#endif /* defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) */
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/***********************************************************************************************//**
|
||||
* \copyright
|
||||
* Copyright 2020-2022 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
**************************************************************************************************/
|
||||
|
||||
/**
|
||||
* \addtogroup group_bsp_bt Bluetooth Configuration Structure
|
||||
* \{
|
||||
* Basic configuration structure for the Bluetooth interface on this board.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE)
|
||||
|
||||
#include "cybt_platform_config.h"
|
||||
#include "cycfg_pins.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !defined(CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD)
|
||||
/** If not already defined, the baud rate to download data at. */
|
||||
#define CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD (115200)
|
||||
#endif
|
||||
|
||||
#if !defined(CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE)
|
||||
/** If not already defined, the baud rate for general operation. */
|
||||
#define CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE (115200)
|
||||
#endif
|
||||
|
||||
#if !defined(CYBSP_BT_PLATFORM_CFG_BITS_DATA)
|
||||
/** If not already defined, the number of data bits to transmit. */
|
||||
#define CYBSP_BT_PLATFORM_CFG_BITS_DATA (8)
|
||||
#endif
|
||||
|
||||
#if !defined(CYBSP_BT_PLATFORM_CFG_BITS_STOP)
|
||||
/** If not already defined, the number of stop bits to transmit. */
|
||||
#define CYBSP_BT_PLATFORM_CFG_BITS_STOP (1)
|
||||
#endif
|
||||
|
||||
#if !defined(CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES)
|
||||
/** If not already defined, the number of bytes to allocated for the task memory pool. */
|
||||
#define CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES (2048)
|
||||
#endif
|
||||
|
||||
#if !defined(CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED)
|
||||
/** If not already defined, the sleep mode LP is enabled. */
|
||||
#define CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED (CYCFG_BT_LP_ENABLED)
|
||||
#endif
|
||||
|
||||
/** Bluetooth platform configuration settings for the board. */
|
||||
extern const cybt_platform_config_t cybsp_bt_platform_cfg;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif // __cplusplus
|
||||
|
||||
#endif /* defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) */
|
||||
|
||||
/** \} group_bsp_bt */
|
||||
|
|
@ -5,8 +5,8 @@
|
|||
* Wrapper function to initialize all generated code.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* Simple wrapper header containing all generated files.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -35,6 +35,7 @@ extern "C" {
|
|||
|
||||
#include "cycfg_notices.h"
|
||||
#include "cycfg_system.h"
|
||||
#include "cycfg_connectivity_bt.h"
|
||||
#include "cycfg_clocks.h"
|
||||
#include "cycfg_routing.h"
|
||||
#include "cycfg_peripherals.h"
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* Sentinel file for determining if generated source is up to date.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@
|
|||
* Description:
|
||||
* CAPSENSE Middleware configuration
|
||||
* This file should not be modified. It was automatically generated by
|
||||
* CAPSENSE Configurator 5.0.0.2684
|
||||
* CAPSENSE Configurator 6.10.0.3796
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company)
|
||||
* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company)
|
||||
* or an affiliate of Cypress Semiconductor Corporation.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -26,7 +26,7 @@
|
|||
|
||||
#include "cycfg_capsense.h"
|
||||
|
||||
/* This enables code only when the CAPSENSE(TM) Middleware is present in the project
|
||||
/* This enables code only when the CAPSENSE(TM) Middleware is present in the project
|
||||
* or the information about the Middleware presence cannot be obtained.
|
||||
*/
|
||||
#if (defined(COMPONENT_MW_CAPSENSE) || !defined(COMPONENT_MW_CORE_MAKE))
|
||||
|
|
@ -80,6 +80,10 @@ static cy_stc_capsense_internal_context_t cy_capsense_internalContext;
|
|||
static uint16_t cy_capsense_rawFilterHistory[CY_CAPSENSE_RAW_HISTORY_SIZE] = {0};
|
||||
#endif
|
||||
|
||||
#if (CY_CAPSENSE_RAW_ALP_HISTORY_SIZE > 0)
|
||||
static uint16_t cy_capsense_rawAlpFilterHistory[CY_CAPSENSE_RAW_ALP_HISTORY_SIZE] = {0};
|
||||
#endif
|
||||
|
||||
#if (CY_CAPSENSE_IIR_HISTORY_LOW_SIZE > 0)
|
||||
static uint8_t cy_capsense_iirHistoryLow[CY_CAPSENSE_IIR_HISTORY_LOW_SIZE] = {0};
|
||||
#endif
|
||||
|
|
@ -138,6 +142,7 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
|
|||
.numPin = CY_CAPSENSE_PIN_COUNT,
|
||||
.numSns = CY_CAPSENSE_SENSOR_COUNT,
|
||||
.numWd = CY_CAPSENSE_TOTAL_WIDGET_COUNT,
|
||||
#if (CY_CAPSENSE_MW_VERSION < 400)
|
||||
.csdEn = CY_CAPSENSE_ENABLE,
|
||||
.csxEn = CY_CAPSENSE_DISABLE,
|
||||
#if (CY_CAPSENSE_MW_VERSION < 300)
|
||||
|
|
@ -147,6 +152,7 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
|
|||
.bistEn = CY_CAPSENSE_DISABLE,
|
||||
#endif
|
||||
.positionFilterEn = CY_CAPSENSE_DISABLE,
|
||||
#endif
|
||||
.periDividerType = (uint8_t)CY_CAPSENSE_PERI_DIV_TYPE,
|
||||
.periDividerIndex = CY_CAPSENSE_PERI_DIV_INDEX,
|
||||
.analogWakeupDelay = 25u,
|
||||
|
|
@ -182,34 +188,46 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
|
|||
.pinCsh = 0u,
|
||||
.pinCintA = 0u,
|
||||
.pinCintB = 0u,
|
||||
#if (CY_CAPSENSE_MW_VERSION < 400)
|
||||
.csdShieldEn = CY_CAPSENSE_DISABLE,
|
||||
#endif
|
||||
.csdInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 300)
|
||||
.csxInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
|
||||
#endif
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 300)
|
||||
.csxInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
|
||||
#endif
|
||||
.csdShieldDelay = CY_CAPSENSE_SH_DELAY_0NS,
|
||||
.csdVref = 0u,
|
||||
.csdRConst = 1000u,
|
||||
#if (CY_CAPSENSE_MW_VERSION < 400)
|
||||
.csdCTankShieldEn = CY_CAPSENSE_DISABLE,
|
||||
#endif
|
||||
.csdShieldNumPin = 0u,
|
||||
.csdShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_MEDIUM,
|
||||
.csdInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM,
|
||||
.csdChargeTransfer = CY_CAPSENSE_IDAC_SOURCING,
|
||||
.csdRawTarget = 85u,
|
||||
#if (CY_CAPSENSE_MW_VERSION < 400)
|
||||
.csdAutotuneEn = CY_CAPSENSE_CSD_SS_HWTH_EN,
|
||||
.csdIdacAutocalEn = CY_CAPSENSE_ENABLE,
|
||||
.csdIdacAutoGainEn = CY_CAPSENSE_ENABLE,
|
||||
#endif
|
||||
.csdCalibrationError = 10u,
|
||||
.csdIdacGainInitIndex = 4u,
|
||||
.csdIdacMin = 20u,
|
||||
#if (CY_CAPSENSE_MW_VERSION < 400)
|
||||
.csdIdacCompEn = CY_CAPSENSE_ENABLE,
|
||||
#endif
|
||||
.csdFineInitTime = 10u,
|
||||
#if (CY_CAPSENSE_MW_VERSION < 400)
|
||||
.csdIdacRowColAlignEn = CY_CAPSENSE_ENABLE,
|
||||
#endif
|
||||
.csdMfsDividerOffsetF1 = 1u,
|
||||
.csdMfsDividerOffsetF2 = 2u,
|
||||
.csxRawTarget = 40u,
|
||||
#if (CY_CAPSENSE_MW_VERSION < 400)
|
||||
.csxIdacGainInitIndex = 2u,
|
||||
.csxIdacAutocalEn = CY_CAPSENSE_DISABLE,
|
||||
#endif
|
||||
.csxCalibrationError = 20u,
|
||||
.csxFineInitTime = 10u,
|
||||
.csxInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM,
|
||||
|
|
@ -385,6 +403,14 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
|
|||
|
||||
static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_COUNT] =
|
||||
{
|
||||
{ /* Button0_Sns0 */
|
||||
Button0_Sns0_PORT,
|
||||
Button0_Sns0_PIN,
|
||||
},
|
||||
{ /* Button1_Sns0 */
|
||||
Button1_Sns0_PORT,
|
||||
Button1_Sns0_PIN,
|
||||
},
|
||||
{ /* LinearSlider0_Sns0 */
|
||||
LinearSlider0_Sns0_PORT,
|
||||
LinearSlider0_Sns0_PIN,
|
||||
|
|
@ -416,37 +442,47 @@ static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_
|
|||
#if (CY_CAPSENSE_ELTD_COUNT > 0)
|
||||
static const cy_stc_capsense_electrode_config_t cy_capsense_electrodeConfig[CY_CAPSENSE_ELTD_COUNT] =
|
||||
{
|
||||
{ /* LinearSlider0_Sns0 */
|
||||
{ /* Button0_Sns0 */
|
||||
.ptrPin = &cy_capsense_pinConfig[0u],
|
||||
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
|
||||
.numPins = 1u,
|
||||
},
|
||||
{ /* LinearSlider0_Sns1 */
|
||||
{ /* Button1_Sns0 */
|
||||
.ptrPin = &cy_capsense_pinConfig[1u],
|
||||
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
|
||||
.numPins = 1u,
|
||||
},
|
||||
{ /* LinearSlider0_Sns2 */
|
||||
{ /* LinearSlider0_Sns0 */
|
||||
.ptrPin = &cy_capsense_pinConfig[2u],
|
||||
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
|
||||
.numPins = 1u,
|
||||
},
|
||||
{ /* LinearSlider0_Sns3 */
|
||||
{ /* LinearSlider0_Sns1 */
|
||||
.ptrPin = &cy_capsense_pinConfig[3u],
|
||||
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
|
||||
.numPins = 1u,
|
||||
},
|
||||
{ /* LinearSlider0_Sns4 */
|
||||
{ /* LinearSlider0_Sns2 */
|
||||
.ptrPin = &cy_capsense_pinConfig[4u],
|
||||
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
|
||||
.numPins = 1u,
|
||||
},
|
||||
{ /* LinearSlider0_Sns3 */
|
||||
.ptrPin = &cy_capsense_pinConfig[5u],
|
||||
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
|
||||
.numPins = 1u,
|
||||
},
|
||||
{ /* LinearSlider0_Sns4 */
|
||||
.ptrPin = &cy_capsense_pinConfig[6u],
|
||||
.type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
|
||||
.numPins = 1u,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENSE_WIDGET_COUNT] =
|
||||
{
|
||||
{ /* LinearSlider0 */
|
||||
{ /* Button0 */
|
||||
.ptrWdContext = &cy_capsense_tuner.widgetContext[0u],
|
||||
.ptrSnsContext = &cy_capsense_tuner.sensorContext[0u],
|
||||
.ptrEltdConfig = &cy_capsense_electrodeConfig[0u],
|
||||
|
|
@ -460,6 +496,126 @@ static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENS
|
|||
.iirCoeff = 128u,
|
||||
.ptrDebounceArr = &cy_capsense_debounce[0u],
|
||||
.ptrDiplexTable = NULL,
|
||||
.centroidConfig = 0u,
|
||||
.xResolution = 0u,
|
||||
.yResolution = 0u,
|
||||
.numSns = 1u,
|
||||
.numCols = 1u,
|
||||
.numRows = 0u,
|
||||
.ptrPosFilterHistory = NULL,
|
||||
.ptrCsxTouchHistory = NULL,
|
||||
.ptrCsxTouchBuffer = NULL,
|
||||
.ptrCsdTouchBuffer = NULL,
|
||||
.ptrGestureConfig = NULL,
|
||||
.ptrGestureContext = NULL,
|
||||
.ballisticConfig = {
|
||||
.accelCoeff = 9u,
|
||||
.speedCoeff = 2u,
|
||||
.divisorValue = 4u,
|
||||
.speedThresholdX = 3u,
|
||||
.speedThresholdY = 4u,
|
||||
},
|
||||
.ptrBallisticContext = NULL,
|
||||
.aiirConfig = {
|
||||
.maxK = 60u,
|
||||
.minK = 1u,
|
||||
.noMovTh = 3u,
|
||||
.littleMovTh = 7u,
|
||||
.largeMovTh = 12u,
|
||||
.divVal = 64u,
|
||||
},
|
||||
.advConfig = {
|
||||
.penultimateTh = 100u,
|
||||
.virtualSnsTh = 100u,
|
||||
.crossCouplingTh = 5u,
|
||||
},
|
||||
.posFilterConfig = 0u,
|
||||
.rawFilterConfig = 0u,
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 400)
|
||||
.alpOnThreshold = 15u,
|
||||
.alpOffThreshold = 5u,
|
||||
#endif
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 300)
|
||||
.senseMethod = CY_CAPSENSE_CSD_GROUP,
|
||||
#else
|
||||
.senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E,
|
||||
#endif
|
||||
.wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
|
||||
},
|
||||
{ /* Button1 */
|
||||
.ptrWdContext = &cy_capsense_tuner.widgetContext[1u],
|
||||
.ptrSnsContext = &cy_capsense_tuner.sensorContext[1u],
|
||||
.ptrEltdConfig = &cy_capsense_electrodeConfig[1u],
|
||||
#if (CY_CAPSENSE_BIST_SUPPORTED)
|
||||
.ptrEltdCapacitance = NULL,
|
||||
.ptrBslnInv = NULL,
|
||||
#endif
|
||||
.ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[1u],
|
||||
.ptrRawFilterHistory = NULL,
|
||||
.ptrRawFilterHistoryLow = NULL,
|
||||
.iirCoeff = 128u,
|
||||
.ptrDebounceArr = &cy_capsense_debounce[1u],
|
||||
.ptrDiplexTable = NULL,
|
||||
.centroidConfig = 0u,
|
||||
.xResolution = 0u,
|
||||
.yResolution = 0u,
|
||||
.numSns = 1u,
|
||||
.numCols = 1u,
|
||||
.numRows = 0u,
|
||||
.ptrPosFilterHistory = NULL,
|
||||
.ptrCsxTouchHistory = NULL,
|
||||
.ptrCsxTouchBuffer = NULL,
|
||||
.ptrCsdTouchBuffer = NULL,
|
||||
.ptrGestureConfig = NULL,
|
||||
.ptrGestureContext = NULL,
|
||||
.ballisticConfig = {
|
||||
.accelCoeff = 9u,
|
||||
.speedCoeff = 2u,
|
||||
.divisorValue = 4u,
|
||||
.speedThresholdX = 3u,
|
||||
.speedThresholdY = 4u,
|
||||
},
|
||||
.ptrBallisticContext = NULL,
|
||||
.aiirConfig = {
|
||||
.maxK = 60u,
|
||||
.minK = 1u,
|
||||
.noMovTh = 3u,
|
||||
.littleMovTh = 7u,
|
||||
.largeMovTh = 12u,
|
||||
.divVal = 64u,
|
||||
},
|
||||
.advConfig = {
|
||||
.penultimateTh = 100u,
|
||||
.virtualSnsTh = 100u,
|
||||
.crossCouplingTh = 5u,
|
||||
},
|
||||
.posFilterConfig = 0u,
|
||||
.rawFilterConfig = 0u,
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 400)
|
||||
.alpOnThreshold = 15u,
|
||||
.alpOffThreshold = 5u,
|
||||
#endif
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 300)
|
||||
.senseMethod = CY_CAPSENSE_CSD_GROUP,
|
||||
#else
|
||||
.senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E,
|
||||
#endif
|
||||
.wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
|
||||
},
|
||||
{ /* LinearSlider0 */
|
||||
.ptrWdContext = &cy_capsense_tuner.widgetContext[2u],
|
||||
.ptrSnsContext = &cy_capsense_tuner.sensorContext[2u],
|
||||
.ptrEltdConfig = &cy_capsense_electrodeConfig[2u],
|
||||
#if (CY_CAPSENSE_BIST_SUPPORTED)
|
||||
.ptrEltdCapacitance = NULL,
|
||||
.ptrBslnInv = NULL,
|
||||
#endif
|
||||
.ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[2u],
|
||||
.ptrRawFilterHistory = NULL,
|
||||
.ptrRawFilterHistoryLow = NULL,
|
||||
.iirCoeff = 128u,
|
||||
.ptrDebounceArr = &cy_capsense_debounce[2u],
|
||||
.ptrDiplexTable = NULL,
|
||||
.centroidConfig = 1u,
|
||||
.xResolution = 300u,
|
||||
.yResolution = 0u,
|
||||
|
|
@ -495,6 +651,10 @@ static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENS
|
|||
},
|
||||
.posFilterConfig = 0u,
|
||||
.rawFilterConfig = 0u,
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 400)
|
||||
.alpOnThreshold = 15u,
|
||||
.alpOffThreshold = 5u,
|
||||
#endif
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 300)
|
||||
.senseMethod = CY_CAPSENSE_CSD_GROUP,
|
||||
#else
|
||||
|
|
@ -508,11 +668,11 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
|
|||
{
|
||||
.commonContext = {
|
||||
#if (CY_CAPSENSE_MW_VERSION < 300)
|
||||
.configId = 0xcb38,
|
||||
.configId = 0xa368,
|
||||
#elif (CY_CAPSENSE_MW_VERSION < 400)
|
||||
.configId = 0xcb39,
|
||||
.configId = 0xa369,
|
||||
#else
|
||||
.configId = 0xcb3a,
|
||||
.configId = 0xa36a,
|
||||
#endif
|
||||
|
||||
.tunerCmd = 0u,
|
||||
|
|
@ -533,6 +693,70 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
|
|||
.tunerCnt = 0u,
|
||||
},
|
||||
.widgetContext = {
|
||||
{ /* Button0 */
|
||||
.fingerCap = 160u,
|
||||
.sigPFC = 0u,
|
||||
.resolution = 12u,
|
||||
.maxRawCount = 0u,
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 300)
|
||||
.maxRawCountRow = 0u,
|
||||
#endif
|
||||
.fingerTh = 100u,
|
||||
.proxTh = 200u,
|
||||
.lowBslnRst = 30u,
|
||||
.snsClk = 4u,
|
||||
.rowSnsClk = 4u,
|
||||
.gestureDetected = 0u,
|
||||
.gestureDirection = 0u,
|
||||
.xDelta = 0,
|
||||
.yDelta = 0,
|
||||
.noiseTh = 40u,
|
||||
.nNoiseTh = 40u,
|
||||
.hysteresis = 10u,
|
||||
.onDebounce = 3u,
|
||||
.snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
|
||||
.idacMod = { 32u, 32u, 32u, },
|
||||
.idacGainIndex = 4u,
|
||||
.rowIdacMod = { 32u, 32u, 32u, },
|
||||
.bslnCoeff = 1u,
|
||||
.status = 0u,
|
||||
.wdTouch = {
|
||||
.ptrPosition = NULL,
|
||||
.numPosition = 0,
|
||||
},
|
||||
},
|
||||
{ /* Button1 */
|
||||
.fingerCap = 160u,
|
||||
.sigPFC = 0u,
|
||||
.resolution = 12u,
|
||||
.maxRawCount = 0u,
|
||||
#if (CY_CAPSENSE_MW_VERSION >= 300)
|
||||
.maxRawCountRow = 0u,
|
||||
#endif
|
||||
.fingerTh = 100u,
|
||||
.proxTh = 200u,
|
||||
.lowBslnRst = 30u,
|
||||
.snsClk = 4u,
|
||||
.rowSnsClk = 4u,
|
||||
.gestureDetected = 0u,
|
||||
.gestureDirection = 0u,
|
||||
.xDelta = 0,
|
||||
.yDelta = 0,
|
||||
.noiseTh = 40u,
|
||||
.nNoiseTh = 40u,
|
||||
.hysteresis = 10u,
|
||||
.onDebounce = 3u,
|
||||
.snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
|
||||
.idacMod = { 32u, 32u, 32u, },
|
||||
.idacGainIndex = 4u,
|
||||
.rowIdacMod = { 32u, 32u, 32u, },
|
||||
.bslnCoeff = 1u,
|
||||
.status = 0u,
|
||||
.wdTouch = {
|
||||
.ptrPosition = NULL,
|
||||
.numPosition = 0,
|
||||
},
|
||||
},
|
||||
{ /* LinearSlider0 */
|
||||
.fingerCap = 160u,
|
||||
.sigPFC = 0u,
|
||||
|
|
@ -567,6 +791,24 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
|
|||
},
|
||||
},
|
||||
.sensorContext = {
|
||||
{ /* Button0_Sns0 */
|
||||
.raw = 0u,
|
||||
.bsln = 0u,
|
||||
.diff = 0u,
|
||||
.status = 0u,
|
||||
.negBslnRstCnt = 0u,
|
||||
.idacComp = 32u,
|
||||
.bslnExt = 0u,
|
||||
},
|
||||
{ /* Button1_Sns0 */
|
||||
.raw = 0u,
|
||||
.bsln = 0u,
|
||||
.diff = 0u,
|
||||
.status = 0u,
|
||||
.negBslnRstCnt = 0u,
|
||||
.idacComp = 32u,
|
||||
.bslnExt = 0u,
|
||||
},
|
||||
{ /* LinearSlider0_Sns0 */
|
||||
.raw = 0u,
|
||||
.bsln = 0u,
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,26 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cycfg_capsense.timestamp
|
||||
*
|
||||
* Description:
|
||||
* Sentinel file for determining if generated source is up to date.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* CAPSENSE Configurator 6.10.0.3796
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
********************************************************************************/
|
||||
|
||||
|
|
@ -4,14 +4,14 @@
|
|||
* Description:
|
||||
* CAPSENSE configuration defines.
|
||||
*
|
||||
* Note: This file is required for the CAPSENSE Middleware Library to build
|
||||
* Note: This file is required for the CAPSENSE Middleware Library to build
|
||||
* successfully.
|
||||
*
|
||||
* This file should not be modified. It was automatically generated by
|
||||
* CAPSENSE Configurator 5.0.0.2684
|
||||
* CAPSENSE Configurator 6.10.0.3796
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company)
|
||||
* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company)
|
||||
* or an affiliate of Cypress Semiconductor Corporation.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
|
|
@ -34,20 +34,21 @@
|
|||
#include <stddef.h>
|
||||
|
||||
/* General */
|
||||
#define CY_CAPSENSE_WIDGET_COUNT (1u)
|
||||
#define CY_CAPSENSE_WIDGET_COUNT (3u)
|
||||
#define CY_CAPSENSE_ACTIVE_WIDGET_COUNT (CY_CAPSENSE_WIDGET_COUNT)
|
||||
#define CY_CAPSENSE_LP_WIDGET_COUNT (0u)
|
||||
#define CY_CAPSENSE_TOTAL_WIDGET_COUNT (CY_CAPSENSE_WIDGET_COUNT)
|
||||
#define CY_CAPSENSE_SENSOR_COUNT (5u)
|
||||
#define CY_CAPSENSE_ELTD_COUNT (5u)
|
||||
#define CY_CAPSENSE_PIN_COUNT (5u)
|
||||
#define CY_CAPSENSE_SENSOR_COUNT (7u)
|
||||
#define CY_CAPSENSE_ELTD_COUNT (7u)
|
||||
#define CY_CAPSENSE_PIN_COUNT (7u)
|
||||
#define CY_CAPSENSE_SHIELD_PIN_COUNT (0u)
|
||||
#define CY_CAPSENSE_POSITION_SIZE (1u)
|
||||
#define CY_CAPSENSE_DEBOUNCE_SIZE (1u)
|
||||
#define CY_CAPSENSE_NOISE_ENVELOPE_SIZE (5u)
|
||||
#define CY_CAPSENSE_DEBOUNCE_SIZE (3u)
|
||||
#define CY_CAPSENSE_NOISE_ENVELOPE_SIZE (7u)
|
||||
#define CY_CAPSENSE_MFS_CH_NUMBER (1u)
|
||||
#define CY_CAPSENSE_RAW_HISTORY_SIZE (0u)
|
||||
#define CY_CAPSENSE_IIR_HISTORY_LOW_SIZE (0u)
|
||||
#define CY_CAPSENSE_RAW_ALP_HISTORY_SIZE (0u)
|
||||
#define CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE (0u)
|
||||
#define CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE (0u)
|
||||
#define CY_CAPSENSE_DIPLEX_SIZE (0u)
|
||||
|
|
@ -66,7 +67,7 @@
|
|||
#define CY_CAPSENSE_SMARTSENSE_FULL_EN (1u)
|
||||
#define CY_CAPSENSE_SMARTSENSE_HW_EN (0u)
|
||||
#define CY_CAPSENSE_SMARTSENSE_DISABLED (0u)
|
||||
#define CY_CAPSENSE_CSD_AUTOTUNE_EN (CY_CAPSENSE_SMARTSENSE_FULL_EN || CY_CAPSENSE_SMARTSENSE_HW_EN)
|
||||
#define CY_CAPSENSE_CSD_AUTOTUNE_EN (CY_CAPSENSE_SMARTSENSE_FULL_EN | CY_CAPSENSE_SMARTSENSE_HW_EN)
|
||||
#define CY_CAPSENSE_CSD_SHIELD_EN (0u)
|
||||
#define CY_CAPSENSE_CSD_SHIELD_CAP_EN (0u)
|
||||
#define CY_CAPSENSE_CSD_CHARGE_TRANSFER (0u)
|
||||
|
|
@ -81,14 +82,17 @@
|
|||
#define CY_CAPSENSE_ADAPTIVE_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN (0u)
|
||||
#define CY_CAPSENSE_RAWCOUNT_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_RC_ALP_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_REGULAR_RC_FILTER_EN (CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN || CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN)
|
||||
#define CY_CAPSENSE_REGULAR_RC_ALP_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_REGULAR_RC_FILTER_EN (CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN | CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN | CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN | CY_CAPSENSE_REGULAR_RC_ALP_FILTER_EN)
|
||||
#define CY_CAPSENSE_PROX_RC_IIR_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_PROX_RC_FILTER_EN (CY_CAPSENSE_PROX_RC_IIR_FILTER_EN || CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN)
|
||||
#define CY_CAPSENSE_PROX_RC_ALP_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_PROX_RC_FILTER_EN (CY_CAPSENSE_PROX_RC_IIR_FILTER_EN | CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN | CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN | CY_CAPSENSE_PROX_RC_ALP_FILTER_EN)
|
||||
#define CY_CAPSENSE_POSITION_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_CSD_POSITION_FILTER_EN (0u)
|
||||
#define CY_CAPSENSE_CSX_POSITION_FILTER_EN (0u)
|
||||
|
|
@ -98,7 +102,7 @@
|
|||
#define CY_CAPSENSE_POS_JITTER_FILTER_EN (0u)
|
||||
|
||||
/* Widgets */
|
||||
#define CY_CAPSENSE_CSD_BUTTON_EN (0u)
|
||||
#define CY_CAPSENSE_CSD_BUTTON_EN (1u)
|
||||
#define CY_CAPSENSE_CSD_MATRIX_EN (0u)
|
||||
#define CY_CAPSENSE_CSD_SLIDER_EN (1u)
|
||||
#define CY_CAPSENSE_CSD_TOUCHPAD_EN (0u)
|
||||
|
|
@ -120,7 +124,7 @@
|
|||
#define CY_CAPSENSE_GANGED_SNS_EN (0u)
|
||||
#define CY_CAPSENSE_CSD_GANGED_SNS_EN (0u)
|
||||
#define CY_CAPSENSE_CSX_GANGED_SNS_EN (0u)
|
||||
#define CY_CAPSENSE_BUTTON_EN (0u)
|
||||
#define CY_CAPSENSE_BUTTON_EN (1u)
|
||||
#define CY_CAPSENSE_MATRIX_EN (0u)
|
||||
#define CY_CAPSENSE_SLIDER_EN (1u)
|
||||
#define CY_CAPSENSE_LINEAR_SLIDER_EN (1u)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -5,8 +5,8 @@
|
|||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -29,25 +29,45 @@
|
|||
#include "cycfg_clocks.h"
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
|
||||
const cyhal_resource_inst_t peri_0_div_16_15_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = peri_0_div_16_15_HW,
|
||||
.channel_num = peri_0_div_16_15_NUM,
|
||||
};
|
||||
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_CSD_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
|
||||
};
|
||||
const cyhal_resource_inst_t CYBSP_TRACE_CLK_DIV_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLOCK,
|
||||
.block_num = CYBSP_TRACE_CLK_DIV_HW,
|
||||
.channel_num = CYBSP_TRACE_CLK_DIV_NUM,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
||||
void init_cycfg_clocks(void)
|
||||
{
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 15U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 15U, 0U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 15U);
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
|
||||
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 7U);
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 7U, 0U);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 7U);
|
||||
}
|
||||
|
||||
void reserve_cycfg_clocks(void)
|
||||
{
|
||||
#if defined (CY_USING_HAL)
|
||||
cyhal_hwmgr_reserve(&peri_0_div_16_15_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_TRACE_CLK_DIV_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* Clock configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -39,16 +39,24 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define peri_0_div_16_15_ENABLED 1U
|
||||
#define peri_0_div_16_15_HW CY_SYSCLK_DIV_16_BIT
|
||||
#define peri_0_div_16_15_NUM 15U
|
||||
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
|
||||
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_CS_CLK_DIV_HW CYBSP_CSD_CLK_DIV_HW
|
||||
#define CYBSP_CSD_CLK_DIV_NUM 0U
|
||||
#define CYBSP_CS_CLK_DIV_NUM CYBSP_CSD_CLK_DIV_NUM
|
||||
#define CYBSP_TRACE_CLK_DIV_ENABLED 1U
|
||||
#define CYBSP_TRACE_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
|
||||
#define CYBSP_TRACE_CLK_DIV_NUM 7U
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t peri_0_div_16_15_obj;
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
|
||||
#define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
|
||||
extern const cyhal_resource_inst_t CYBSP_TRACE_CLK_DIV_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_clocks(void);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,30 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cycfg_connectivity_bt.c
|
||||
*
|
||||
* Description:
|
||||
* Connectivity BT configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
********************************************************************************/
|
||||
|
||||
#include "cycfg_connectivity_bt.h"
|
||||
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cycfg_connectivity_bt.h
|
||||
*
|
||||
* Description:
|
||||
* Connectivity BT configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
********************************************************************************/
|
||||
|
||||
#if !defined(CYCFG_CONNECTIVITY_BT_H)
|
||||
#define CYCFG_CONNECTIVITY_BT_H
|
||||
|
||||
#include "cycfg_notices.h"
|
||||
#include "cycfg_pins.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define bt_0_power_0_ENABLED (0)
|
||||
#define CYCFG_BT_LP_ENABLED 0
|
||||
#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
|
||||
#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
|
||||
#define CYCFG_BT_HOST_WAKE_GPIO CYHAL_NC_PIN_VALUE
|
||||
#define CYCFG_BT_HOST_WAKE_IRQ_EVENT 0
|
||||
#define CYCFG_BT_DEV_WAKE_GPIO CYHAL_NC_PIN_VALUE
|
||||
#define CYCFG_BT_DEV_WAKE_POLARITY 0
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* CYCFG_CONNECTIVITY_BT_H */
|
||||
|
|
@ -6,8 +6,8 @@
|
|||
* design.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -38,7 +38,10 @@
|
|||
|
||||
#ifdef CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION
|
||||
#ifndef CY8C624ALQI_S2D42
|
||||
#error "Unexpected MPN; expected DEVICE:=CY8C624ALQI-S2D42. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
|
||||
#error "Unexpected MPN; expected DEVICE:=CY8C624ALQI-S2D42, ADDITIONAL_DEVICES:=CYW43012C0WKWBG. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
|
||||
#endif
|
||||
#ifndef CYW43012C0WKWBG
|
||||
#error "Unexpected MPN; expected DEVICE:=CY8C624ALQI-S2D42, ADDITIONAL_DEVICES:=CYW43012C0WKWBG. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
|
||||
#include "cycfg_peripherals.h"
|
||||
|
||||
cy_stc_csd_context_t cy_csd_0_context =
|
||||
cy_stc_csd_context_t cy_csd_0_context =
|
||||
{
|
||||
.lockKey = CY_CSD_NONE_KEY,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* Peripheral Hardware Block configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -45,17 +45,21 @@ extern "C" {
|
|||
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
|
||||
#define CY_CAPSENSE_PERI_DIV_INDEX 0u
|
||||
#define Cmod_PORT GPIO_PRT7
|
||||
#define LinearSlider0_Sns0_PORT GPIO_PRT7
|
||||
#define Button0_Sns0_PORT GPIO_PRT7
|
||||
#define Button1_Sns0_PORT GPIO_PRT9
|
||||
#define LinearSlider0_Sns0_PORT GPIO_PRT9
|
||||
#define LinearSlider0_Sns1_PORT GPIO_PRT9
|
||||
#define LinearSlider0_Sns2_PORT GPIO_PRT9
|
||||
#define LinearSlider0_Sns3_PORT GPIO_PRT9
|
||||
#define LinearSlider0_Sns4_PORT GPIO_PRT9
|
||||
#define Cmod_PIN 7u
|
||||
#define LinearSlider0_Sns0_PIN 3u
|
||||
#define LinearSlider0_Sns1_PIN 0u
|
||||
#define LinearSlider0_Sns2_PIN 1u
|
||||
#define LinearSlider0_Sns3_PIN 2u
|
||||
#define LinearSlider0_Sns4_PIN 3u
|
||||
#define Button0_Sns0_PIN 3u
|
||||
#define Button1_Sns0_PIN 0u
|
||||
#define LinearSlider0_Sns0_PIN 1u
|
||||
#define LinearSlider0_Sns1_PIN 2u
|
||||
#define LinearSlider0_Sns2_PIN 3u
|
||||
#define LinearSlider0_Sns3_PIN 0u
|
||||
#define LinearSlider0_Sns4_PIN 1u
|
||||
#define Cmod_PORT_NUM 7u
|
||||
#define CYBSP_CSD_HW CSD0
|
||||
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
|
||||
#include "cycfg_pins.h"
|
||||
|
||||
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_PULLUP,
|
||||
|
|
@ -45,14 +45,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
|
||||
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_SWDIO_PORT_NUM,
|
||||
.channel_num = CYBSP_SWDIO_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_PULLDOWN,
|
||||
|
|
@ -69,14 +69,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
|
||||
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_SWDCK_PORT_NUM,
|
||||
.channel_num = CYBSP_SWDCK_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
|
|
@ -93,14 +93,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CINA_obj =
|
||||
const cyhal_resource_inst_t CYBSP_CINA_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_CINA_PORT_NUM,
|
||||
.channel_num = CYBSP_CINA_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
|
|
@ -117,18 +117,18 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CINB_obj =
|
||||
const cyhal_resource_inst_t CYBSP_CINB_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_CINB_PORT_NUM,
|
||||
.channel_num = CYBSP_CINB_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_BLUE_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_CSD_SLD0_HSIOM,
|
||||
.hsiom = CYBSP_LED_RGB_BLUE_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
|
|
@ -141,14 +141,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
|
||||
const cyhal_resource_inst_t CYBSP_LED_RGB_BLUE_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
|
||||
.channel_num = CYBSP_CSD_SLD0_PIN,
|
||||
.block_num = CYBSP_LED_RGB_BLUE_PORT_NUM,
|
||||
.channel_num = CYBSP_LED_RGB_BLUE_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
|
|
@ -165,18 +165,18 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CMOD_obj =
|
||||
const cyhal_resource_inst_t CYBSP_CMOD_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_CMOD_PORT_NUM,
|
||||
.channel_num = CYBSP_CMOD_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_CSD_SLD1_HSIOM,
|
||||
.hsiom = CYBSP_CSD_BTN0_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
|
|
@ -189,18 +189,18 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
|
||||
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
|
||||
.channel_num = CYBSP_CSD_SLD1_PIN,
|
||||
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
|
||||
.channel_num = CYBSP_CSD_BTN0_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_A8_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_CSD_SLD2_HSIOM,
|
||||
.hsiom = CYBSP_A8_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
|
|
@ -213,18 +213,18 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
|
||||
const cyhal_resource_inst_t CYBSP_A8_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
|
||||
.channel_num = CYBSP_CSD_SLD2_PIN,
|
||||
.block_num = CYBSP_A8_PORT_NUM,
|
||||
.channel_num = CYBSP_A8_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_A9_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_CSD_SLD3_HSIOM,
|
||||
.hsiom = CYBSP_A9_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
|
|
@ -237,18 +237,18 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
|
||||
const cyhal_resource_inst_t CYBSP_A9_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
|
||||
.channel_num = CYBSP_CSD_SLD3_PIN,
|
||||
.block_num = CYBSP_A9_PORT_NUM,
|
||||
.channel_num = CYBSP_A9_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
|
||||
const cy_stc_gpio_pin_config_t CYBSP_A10_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_CSD_SLD4_HSIOM,
|
||||
.hsiom = CYBSP_A10_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
|
|
@ -261,11 +261,35 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
|
|||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
|
||||
const cyhal_resource_inst_t CYBSP_A10_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_CSD_SLD4_PORT_NUM,
|
||||
.channel_num = CYBSP_CSD_SLD4_PIN,
|
||||
.block_num = CYBSP_A10_PORT_NUM,
|
||||
.channel_num = CYBSP_A10_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
const cy_stc_gpio_pin_config_t CYBSP_A11_config =
|
||||
{
|
||||
.outVal = 1,
|
||||
.driveMode = CY_GPIO_DM_ANALOG,
|
||||
.hsiom = CYBSP_A11_HSIOM,
|
||||
.intEdge = CY_GPIO_INTR_DISABLE,
|
||||
.intMask = 0UL,
|
||||
.vtrip = CY_GPIO_VTRIP_CMOS,
|
||||
.slewRate = CY_GPIO_SLEW_FAST,
|
||||
.driveSel = CY_GPIO_DRIVE_1_2,
|
||||
.vregEn = 0UL,
|
||||
.ibufMode = 0UL,
|
||||
.vtripSel = 0UL,
|
||||
.vrefSel = 0UL,
|
||||
.vohSel = 0UL,
|
||||
};
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t CYBSP_A11_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_GPIO,
|
||||
.block_num = CYBSP_A11_PORT_NUM,
|
||||
.channel_num = CYBSP_A11_PIN,
|
||||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
|
|
@ -276,6 +300,7 @@ void init_cycfg_pins(void)
|
|||
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
|
||||
Cy_GPIO_Pin_Init(CYBSP_CINA_PORT, CYBSP_CINA_PIN, &CYBSP_CINA_config);
|
||||
Cy_GPIO_Pin_Init(CYBSP_CINB_PORT, CYBSP_CINB_PIN, &CYBSP_CINB_config);
|
||||
Cy_GPIO_Pin_Init(CYBSP_CSD_BTN0_PORT, CYBSP_CSD_BTN0_PIN, &CYBSP_CSD_BTN0_config);
|
||||
}
|
||||
|
||||
void reserve_cycfg_pins(void)
|
||||
|
|
@ -285,11 +310,12 @@ void reserve_cycfg_pins(void)
|
|||
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_LED_RGB_BLUE_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_A8_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_A9_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_A10_obj);
|
||||
cyhal_hwmgr_reserve(&CYBSP_A11_obj);
|
||||
#endif //defined (CY_USING_HAL)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* Pin configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -41,10 +41,11 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_USER_LED1 (P0_0)
|
||||
#define CYBSP_USER_LED2 (P0_1)
|
||||
#define CYBSP_SW2 (P0_4)
|
||||
#define CYBSP_USER_BTN1 CYBSP_SW2
|
||||
#define CYBSP_USER_BTN CYBSP_SW2
|
||||
#define CYBSP_D8 (P0_5)
|
||||
#define CYBSP_LED_RGB_GREEN (P0_5)
|
||||
#define CYBSP_A0 (P10_0)
|
||||
#define CYBSP_J2_1 CYBSP_A0
|
||||
#define CYBSP_A1 (P10_1)
|
||||
|
|
@ -57,12 +58,27 @@ extern "C" {
|
|||
#define CYBSP_J2_9 CYBSP_A4
|
||||
#define CYBSP_A5 (P10_5)
|
||||
#define CYBSP_J2_11 CYBSP_A5
|
||||
#define CYBSP_BT_UART_RX (P3_0)
|
||||
#define CYBSP_BT_UART_TX (P3_1)
|
||||
#define CYBSP_QSPI_FRAM_SSEL (P11_0)
|
||||
#define CYBSP_QSPI_SS (P11_2)
|
||||
#define CYBSP_QSPI_FLASH_SSEL CYBSP_QSPI_SS
|
||||
#define CYBSP_QSPI_D3 (P11_3)
|
||||
#define CYBSP_QSPI_D2 (P11_4)
|
||||
#define CYBSP_QSPI_D1 (P11_5)
|
||||
#define CYBSP_QSPI_D0 (P11_6)
|
||||
#define CYBSP_QSPI_SCK (P11_7)
|
||||
#define CYBSP_WIFI_HOST_WAKE (P12_6)
|
||||
#define CYBSP_WIFI_SDIO_D0 (P2_0)
|
||||
#define CYBSP_WIFI_SDIO_D1 (P2_1)
|
||||
#define CYBSP_WIFI_SDIO_D2 (P2_2)
|
||||
#define CYBSP_WIFI_SDIO_D3 (P2_3)
|
||||
#define CYBSP_WIFI_SDIO_CMD (P2_4)
|
||||
#define CYBSP_WIFI_SDIO_CLK (P2_5)
|
||||
#define CYBSP_WIFI_WL_REG_ON (P2_7)
|
||||
#define CYBSP_D0 (P5_0)
|
||||
#define CYBSP_D1 (P5_1)
|
||||
#define CYBSP_D6 (P5_6)
|
||||
#define CYBSP_D7 (P5_7)
|
||||
#define CYBSP_USER_BTN (P6_2)
|
||||
#define CYBSP_DEBUG_UART_RX (P6_4)
|
||||
#define CYBSP_DEBUG_UART_TX (P6_5)
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
|
@ -82,7 +98,7 @@ extern "C" {
|
|||
#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
|
||||
#define CYBSP_SWDIO P6_6
|
||||
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_SWDCK_ENABLED 1U
|
||||
|
|
@ -101,8 +117,9 @@ extern "C" {
|
|||
#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
|
||||
#define CYBSP_SWDCK P6_7
|
||||
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
|
||||
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
|
||||
#define CYBSP_TRACE_CLK (P7_0)
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CINA_ENABLED 1U
|
||||
#define CYBSP_CINA_PORT GPIO_PRT7
|
||||
|
|
@ -120,7 +137,7 @@ extern "C" {
|
|||
#define CYBSP_CINA_HAL_PORT_PIN P7_1
|
||||
#define CYBSP_CINA P7_1
|
||||
#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CINB_ENABLED 1U
|
||||
|
|
@ -139,41 +156,41 @@ extern "C" {
|
|||
#define CYBSP_CINB_HAL_PORT_PIN P7_2
|
||||
#define CYBSP_CINB P7_2
|
||||
#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD0_ENABLED 1U
|
||||
#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED
|
||||
#define CYBSP_CSD_SLD0_PORT GPIO_PRT7
|
||||
#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT
|
||||
#define CYBSP_CSD_SLD0_PORT_NUM 7U
|
||||
#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM
|
||||
#define CYBSP_CSD_SLD0_PIN 3U
|
||||
#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN
|
||||
#define CYBSP_CSD_SLD0_NUM 3U
|
||||
#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM
|
||||
#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE
|
||||
#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
|
||||
#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE
|
||||
#define CYBSP_LED_RGB_BLUE_ENABLED 1U
|
||||
#define CYBSP_USER_LED5_ENABLED CYBSP_LED_RGB_BLUE_ENABLED
|
||||
#define CYBSP_LED_RGB_BLUE_PORT GPIO_PRT7
|
||||
#define CYBSP_USER_LED5_PORT CYBSP_LED_RGB_BLUE_PORT
|
||||
#define CYBSP_LED_RGB_BLUE_PORT_NUM 7U
|
||||
#define CYBSP_USER_LED5_PORT_NUM CYBSP_LED_RGB_BLUE_PORT_NUM
|
||||
#define CYBSP_LED_RGB_BLUE_PIN 3U
|
||||
#define CYBSP_USER_LED5_PIN CYBSP_LED_RGB_BLUE_PIN
|
||||
#define CYBSP_LED_RGB_BLUE_NUM 3U
|
||||
#define CYBSP_USER_LED5_NUM CYBSP_LED_RGB_BLUE_NUM
|
||||
#define CYBSP_LED_RGB_BLUE_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_USER_LED5_DRIVEMODE CYBSP_LED_RGB_BLUE_DRIVEMODE
|
||||
#define CYBSP_LED_RGB_BLUE_INIT_DRIVESTATE 1
|
||||
#define CYBSP_USER_LED5_INIT_DRIVESTATE CYBSP_LED_RGB_BLUE_INIT_DRIVESTATE
|
||||
#ifndef ioss_0_port_7_pin_3_HSIOM
|
||||
#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_7_pin_3_HSIOM
|
||||
#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM
|
||||
#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_7_IRQn
|
||||
#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ
|
||||
#define CYBSP_LED_RGB_BLUE_HSIOM ioss_0_port_7_pin_3_HSIOM
|
||||
#define CYBSP_USER_LED5_HSIOM CYBSP_LED_RGB_BLUE_HSIOM
|
||||
#define CYBSP_LED_RGB_BLUE_IRQ ioss_interrupts_gpio_7_IRQn
|
||||
#define CYBSP_USER_LED5_IRQ CYBSP_LED_RGB_BLUE_IRQ
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD0_HAL_PORT_PIN P7_3
|
||||
#define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN
|
||||
#define CYBSP_CSD_SLD0 P7_3
|
||||
#define CYBSP_CS_SLD0 CYBSP_CSD_SLD0
|
||||
#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ
|
||||
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR
|
||||
#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE
|
||||
#define CYBSP_LED_RGB_BLUE_HAL_PORT_PIN P7_3
|
||||
#define CYBSP_USER_LED5_HAL_PORT_PIN CYBSP_LED_RGB_BLUE_HAL_PORT_PIN
|
||||
#define CYBSP_LED_RGB_BLUE P7_3
|
||||
#define CYBSP_USER_LED5 CYBSP_LED_RGB_BLUE
|
||||
#define CYBSP_LED_RGB_BLUE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_USER_LED5_HAL_IRQ CYBSP_LED_RGB_BLUE_HAL_IRQ
|
||||
#define CYBSP_LED_RGB_BLUE_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_USER_LED5_HAL_DIR CYBSP_LED_RGB_BLUE_HAL_DIR
|
||||
#define CYBSP_LED_RGB_BLUE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_USER_LED5_HAL_DRIVEMODE CYBSP_LED_RGB_BLUE_HAL_DRIVEMODE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CMOD_ENABLED 1U
|
||||
#define CYBSP_CMOD_PORT GPIO_PRT7
|
||||
|
|
@ -191,140 +208,187 @@ extern "C" {
|
|||
#define CYBSP_CMOD_HAL_PORT_PIN P7_7
|
||||
#define CYBSP_CMOD P7_7
|
||||
#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD1_ENABLED 1U
|
||||
#define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED
|
||||
#define CYBSP_CSD_SLD1_PORT GPIO_PRT9
|
||||
#define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT
|
||||
#define CYBSP_CSD_SLD1_PORT_NUM 9U
|
||||
#define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM
|
||||
#define CYBSP_CSD_SLD1_PIN 0U
|
||||
#define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN
|
||||
#define CYBSP_CSD_SLD1_NUM 0U
|
||||
#define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM
|
||||
#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE
|
||||
#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
|
||||
#define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE
|
||||
#define CYBSP_CSD_BTN0_ENABLED 1U
|
||||
#define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED
|
||||
#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
|
||||
#define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT
|
||||
#define CYBSP_CSD_BTN0_PORT_NUM 8U
|
||||
#define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM
|
||||
#define CYBSP_CSD_BTN0_PIN 1U
|
||||
#define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN
|
||||
#define CYBSP_CSD_BTN0_NUM 1U
|
||||
#define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM
|
||||
#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE
|
||||
#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
|
||||
#define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE
|
||||
#ifndef ioss_0_port_8_pin_1_HSIOM
|
||||
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
|
||||
#define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM
|
||||
#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
|
||||
#define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
|
||||
#define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN
|
||||
#define CYBSP_CSD_BTN0 P8_1
|
||||
#define CYBSP_CS_BTN0 CYBSP_CSD_BTN0
|
||||
#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ
|
||||
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR
|
||||
#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_A8_ENABLED 1U
|
||||
#define CYBSP_J2_2_ENABLED CYBSP_A8_ENABLED
|
||||
#define CYBSP_A8_PORT GPIO_PRT9
|
||||
#define CYBSP_J2_2_PORT CYBSP_A8_PORT
|
||||
#define CYBSP_A8_PORT_NUM 9U
|
||||
#define CYBSP_J2_2_PORT_NUM CYBSP_A8_PORT_NUM
|
||||
#define CYBSP_A8_PIN 0U
|
||||
#define CYBSP_J2_2_PIN CYBSP_A8_PIN
|
||||
#define CYBSP_A8_NUM 0U
|
||||
#define CYBSP_J2_2_NUM CYBSP_A8_NUM
|
||||
#define CYBSP_A8_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_J2_2_DRIVEMODE CYBSP_A8_DRIVEMODE
|
||||
#define CYBSP_A8_INIT_DRIVESTATE 1
|
||||
#define CYBSP_J2_2_INIT_DRIVESTATE CYBSP_A8_INIT_DRIVESTATE
|
||||
#ifndef ioss_0_port_9_pin_0_HSIOM
|
||||
#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_9_pin_0_HSIOM
|
||||
#define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM
|
||||
#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_9_IRQn
|
||||
#define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ
|
||||
#define CYBSP_A8_HSIOM ioss_0_port_9_pin_0_HSIOM
|
||||
#define CYBSP_J2_2_HSIOM CYBSP_A8_HSIOM
|
||||
#define CYBSP_A8_IRQ ioss_interrupts_gpio_9_IRQn
|
||||
#define CYBSP_J2_2_IRQ CYBSP_A8_IRQ
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD1_HAL_PORT_PIN P9_0
|
||||
#define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN
|
||||
#define CYBSP_CSD_SLD1 P9_0
|
||||
#define CYBSP_CS_SLD1 CYBSP_CSD_SLD1
|
||||
#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ
|
||||
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR
|
||||
#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE
|
||||
#define CYBSP_A8_HAL_PORT_PIN P9_0
|
||||
#define CYBSP_J2_2_HAL_PORT_PIN CYBSP_A8_HAL_PORT_PIN
|
||||
#define CYBSP_A8 P9_0
|
||||
#define CYBSP_J2_2 CYBSP_A8
|
||||
#define CYBSP_A8_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_J2_2_HAL_IRQ CYBSP_A8_HAL_IRQ
|
||||
#define CYBSP_A8_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_J2_2_HAL_DIR CYBSP_A8_HAL_DIR
|
||||
#define CYBSP_A8_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_J2_2_HAL_DRIVEMODE CYBSP_A8_HAL_DRIVEMODE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD2_ENABLED 1U
|
||||
#define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED
|
||||
#define CYBSP_CSD_SLD2_PORT GPIO_PRT9
|
||||
#define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT
|
||||
#define CYBSP_CSD_SLD2_PORT_NUM 9U
|
||||
#define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM
|
||||
#define CYBSP_CSD_SLD2_PIN 1U
|
||||
#define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN
|
||||
#define CYBSP_CSD_SLD2_NUM 1U
|
||||
#define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM
|
||||
#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE
|
||||
#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
|
||||
#define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE
|
||||
#define CYBSP_A9_ENABLED 1U
|
||||
#define CYBSP_J2_4_ENABLED CYBSP_A9_ENABLED
|
||||
#define CYBSP_A9_PORT GPIO_PRT9
|
||||
#define CYBSP_J2_4_PORT CYBSP_A9_PORT
|
||||
#define CYBSP_A9_PORT_NUM 9U
|
||||
#define CYBSP_J2_4_PORT_NUM CYBSP_A9_PORT_NUM
|
||||
#define CYBSP_A9_PIN 1U
|
||||
#define CYBSP_J2_4_PIN CYBSP_A9_PIN
|
||||
#define CYBSP_A9_NUM 1U
|
||||
#define CYBSP_J2_4_NUM CYBSP_A9_NUM
|
||||
#define CYBSP_A9_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_J2_4_DRIVEMODE CYBSP_A9_DRIVEMODE
|
||||
#define CYBSP_A9_INIT_DRIVESTATE 1
|
||||
#define CYBSP_J2_4_INIT_DRIVESTATE CYBSP_A9_INIT_DRIVESTATE
|
||||
#ifndef ioss_0_port_9_pin_1_HSIOM
|
||||
#define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_9_pin_1_HSIOM
|
||||
#define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM
|
||||
#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_9_IRQn
|
||||
#define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ
|
||||
#define CYBSP_A9_HSIOM ioss_0_port_9_pin_1_HSIOM
|
||||
#define CYBSP_J2_4_HSIOM CYBSP_A9_HSIOM
|
||||
#define CYBSP_A9_IRQ ioss_interrupts_gpio_9_IRQn
|
||||
#define CYBSP_J2_4_IRQ CYBSP_A9_IRQ
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD2_HAL_PORT_PIN P9_1
|
||||
#define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN
|
||||
#define CYBSP_CSD_SLD2 P9_1
|
||||
#define CYBSP_CS_SLD2 CYBSP_CSD_SLD2
|
||||
#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ
|
||||
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR
|
||||
#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE
|
||||
#define CYBSP_A9_HAL_PORT_PIN P9_1
|
||||
#define CYBSP_J2_4_HAL_PORT_PIN CYBSP_A9_HAL_PORT_PIN
|
||||
#define CYBSP_A9 P9_1
|
||||
#define CYBSP_J2_4 CYBSP_A9
|
||||
#define CYBSP_A9_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_J2_4_HAL_IRQ CYBSP_A9_HAL_IRQ
|
||||
#define CYBSP_A9_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_J2_4_HAL_DIR CYBSP_A9_HAL_DIR
|
||||
#define CYBSP_A9_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_J2_4_HAL_DRIVEMODE CYBSP_A9_HAL_DRIVEMODE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD3_ENABLED 1U
|
||||
#define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED
|
||||
#define CYBSP_CSD_SLD3_PORT GPIO_PRT9
|
||||
#define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT
|
||||
#define CYBSP_CSD_SLD3_PORT_NUM 9U
|
||||
#define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM
|
||||
#define CYBSP_CSD_SLD3_PIN 2U
|
||||
#define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN
|
||||
#define CYBSP_CSD_SLD3_NUM 2U
|
||||
#define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM
|
||||
#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE
|
||||
#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
|
||||
#define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE
|
||||
#define CYBSP_A10_ENABLED 1U
|
||||
#define CYBSP_J2_6_ENABLED CYBSP_A10_ENABLED
|
||||
#define CYBSP_A10_PORT GPIO_PRT9
|
||||
#define CYBSP_J2_6_PORT CYBSP_A10_PORT
|
||||
#define CYBSP_A10_PORT_NUM 9U
|
||||
#define CYBSP_J2_6_PORT_NUM CYBSP_A10_PORT_NUM
|
||||
#define CYBSP_A10_PIN 2U
|
||||
#define CYBSP_J2_6_PIN CYBSP_A10_PIN
|
||||
#define CYBSP_A10_NUM 2U
|
||||
#define CYBSP_J2_6_NUM CYBSP_A10_NUM
|
||||
#define CYBSP_A10_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_J2_6_DRIVEMODE CYBSP_A10_DRIVEMODE
|
||||
#define CYBSP_A10_INIT_DRIVESTATE 1
|
||||
#define CYBSP_J2_6_INIT_DRIVESTATE CYBSP_A10_INIT_DRIVESTATE
|
||||
#ifndef ioss_0_port_9_pin_2_HSIOM
|
||||
#define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_9_pin_2_HSIOM
|
||||
#define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM
|
||||
#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_9_IRQn
|
||||
#define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ
|
||||
#define CYBSP_A10_HSIOM ioss_0_port_9_pin_2_HSIOM
|
||||
#define CYBSP_J2_6_HSIOM CYBSP_A10_HSIOM
|
||||
#define CYBSP_A10_IRQ ioss_interrupts_gpio_9_IRQn
|
||||
#define CYBSP_J2_6_IRQ CYBSP_A10_IRQ
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD3_HAL_PORT_PIN P9_2
|
||||
#define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN
|
||||
#define CYBSP_CSD_SLD3 P9_2
|
||||
#define CYBSP_CS_SLD3 CYBSP_CSD_SLD3
|
||||
#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ
|
||||
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR
|
||||
#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE
|
||||
#define CYBSP_A10_HAL_PORT_PIN P9_2
|
||||
#define CYBSP_J2_6_HAL_PORT_PIN CYBSP_A10_HAL_PORT_PIN
|
||||
#define CYBSP_A10 P9_2
|
||||
#define CYBSP_J2_6 CYBSP_A10
|
||||
#define CYBSP_A10_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_J2_6_HAL_IRQ CYBSP_A10_HAL_IRQ
|
||||
#define CYBSP_A10_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_J2_6_HAL_DIR CYBSP_A10_HAL_DIR
|
||||
#define CYBSP_A10_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_J2_6_HAL_DRIVEMODE CYBSP_A10_HAL_DRIVEMODE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD4_ENABLED 1U
|
||||
#define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED
|
||||
#define CYBSP_CSD_SLD4_PORT GPIO_PRT9
|
||||
#define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT
|
||||
#define CYBSP_CSD_SLD4_PORT_NUM 9U
|
||||
#define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM
|
||||
#define CYBSP_CSD_SLD4_PIN 3U
|
||||
#define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN
|
||||
#define CYBSP_CSD_SLD4_NUM 3U
|
||||
#define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM
|
||||
#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE
|
||||
#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
|
||||
#define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE
|
||||
#define CYBSP_A11_ENABLED 1U
|
||||
#define CYBSP_J2_8_ENABLED CYBSP_A11_ENABLED
|
||||
#define CYBSP_TRACE_DATA0_ENABLED CYBSP_A11_ENABLED
|
||||
#define CYBSP_A11_PORT GPIO_PRT9
|
||||
#define CYBSP_J2_8_PORT CYBSP_A11_PORT
|
||||
#define CYBSP_TRACE_DATA0_PORT CYBSP_A11_PORT
|
||||
#define CYBSP_A11_PORT_NUM 9U
|
||||
#define CYBSP_J2_8_PORT_NUM CYBSP_A11_PORT_NUM
|
||||
#define CYBSP_TRACE_DATA0_PORT_NUM CYBSP_A11_PORT_NUM
|
||||
#define CYBSP_A11_PIN 3U
|
||||
#define CYBSP_J2_8_PIN CYBSP_A11_PIN
|
||||
#define CYBSP_TRACE_DATA0_PIN CYBSP_A11_PIN
|
||||
#define CYBSP_A11_NUM 3U
|
||||
#define CYBSP_J2_8_NUM CYBSP_A11_NUM
|
||||
#define CYBSP_TRACE_DATA0_NUM CYBSP_A11_NUM
|
||||
#define CYBSP_A11_DRIVEMODE CY_GPIO_DM_ANALOG
|
||||
#define CYBSP_J2_8_DRIVEMODE CYBSP_A11_DRIVEMODE
|
||||
#define CYBSP_TRACE_DATA0_DRIVEMODE CYBSP_A11_DRIVEMODE
|
||||
#define CYBSP_A11_INIT_DRIVESTATE 1
|
||||
#define CYBSP_J2_8_INIT_DRIVESTATE CYBSP_A11_INIT_DRIVESTATE
|
||||
#define CYBSP_TRACE_DATA0_INIT_DRIVESTATE CYBSP_A11_INIT_DRIVESTATE
|
||||
#ifndef ioss_0_port_9_pin_3_HSIOM
|
||||
#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_GPIO
|
||||
#endif
|
||||
#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_9_pin_3_HSIOM
|
||||
#define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM
|
||||
#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_9_IRQn
|
||||
#define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ
|
||||
#define CYBSP_A11_HSIOM ioss_0_port_9_pin_3_HSIOM
|
||||
#define CYBSP_J2_8_HSIOM CYBSP_A11_HSIOM
|
||||
#define CYBSP_TRACE_DATA0_HSIOM CYBSP_A11_HSIOM
|
||||
#define CYBSP_A11_IRQ ioss_interrupts_gpio_9_IRQn
|
||||
#define CYBSP_J2_8_IRQ CYBSP_A11_IRQ
|
||||
#define CYBSP_TRACE_DATA0_IRQ CYBSP_A11_IRQ
|
||||
#if defined (CY_USING_HAL)
|
||||
#define CYBSP_CSD_SLD4_HAL_PORT_PIN P9_3
|
||||
#define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN
|
||||
#define CYBSP_CSD_SLD4 P9_3
|
||||
#define CYBSP_CS_SLD4 CYBSP_CSD_SLD4
|
||||
#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ
|
||||
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR
|
||||
#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE
|
||||
#define CYBSP_A11_HAL_PORT_PIN P9_3
|
||||
#define CYBSP_J2_8_HAL_PORT_PIN CYBSP_A11_HAL_PORT_PIN
|
||||
#define CYBSP_TRACE_DATA0_HAL_PORT_PIN CYBSP_A11_HAL_PORT_PIN
|
||||
#define CYBSP_A11 P9_3
|
||||
#define CYBSP_J2_8 CYBSP_A11
|
||||
#define CYBSP_TRACE_DATA0 CYBSP_A11
|
||||
#define CYBSP_A11_HAL_IRQ CYHAL_GPIO_IRQ_NONE
|
||||
#define CYBSP_J2_8_HAL_IRQ CYBSP_A11_HAL_IRQ
|
||||
#define CYBSP_TRACE_DATA0_HAL_IRQ CYBSP_A11_HAL_IRQ
|
||||
#define CYBSP_A11_HAL_DIR CYHAL_GPIO_DIR_INPUT
|
||||
#define CYBSP_J2_8_HAL_DIR CYBSP_A11_HAL_DIR
|
||||
#define CYBSP_TRACE_DATA0_HAL_DIR CYBSP_A11_HAL_DIR
|
||||
#define CYBSP_A11_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
|
||||
#define CYBSP_J2_8_HAL_DRIVEMODE CYBSP_A11_HAL_DRIVEMODE
|
||||
#define CYBSP_TRACE_DATA0_HAL_DRIVEMODE CYBSP_A11_HAL_DRIVEMODE
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
|
||||
|
|
@ -343,39 +407,47 @@ extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
|
|||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CINB_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
|
||||
#define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_BLUE_config;
|
||||
#define CYBSP_USER_LED5_config CYBSP_LED_RGB_BLUE_config
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
|
||||
#define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj
|
||||
extern const cyhal_resource_inst_t CYBSP_LED_RGB_BLUE_obj;
|
||||
#define CYBSP_USER_LED5_obj CYBSP_LED_RGB_BLUE_obj
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
|
||||
#define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
|
||||
#define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
|
||||
#define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
|
||||
#define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
|
||||
#define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_A8_config;
|
||||
#define CYBSP_J2_2_config CYBSP_A8_config
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
|
||||
#define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj
|
||||
extern const cyhal_resource_inst_t CYBSP_A8_obj;
|
||||
#define CYBSP_J2_2_obj CYBSP_A8_obj
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
|
||||
#define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_A9_config;
|
||||
#define CYBSP_J2_4_config CYBSP_A9_config
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
|
||||
#define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj
|
||||
extern const cyhal_resource_inst_t CYBSP_A9_obj;
|
||||
#define CYBSP_J2_4_obj CYBSP_A9_obj
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
|
||||
#define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_A10_config;
|
||||
#define CYBSP_J2_6_config CYBSP_A10_config
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
|
||||
#define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj
|
||||
extern const cyhal_resource_inst_t CYBSP_A10_obj;
|
||||
#define CYBSP_J2_6_obj CYBSP_A10_obj
|
||||
#endif //defined (CY_USING_HAL)
|
||||
extern const cy_stc_gpio_pin_config_t CYBSP_A11_config;
|
||||
#define CYBSP_J2_8_config CYBSP_A11_config
|
||||
#define CYBSP_TRACE_DATA0_config CYBSP_A11_config
|
||||
#if defined (CY_USING_HAL)
|
||||
extern const cyhal_resource_inst_t CYBSP_A11_obj;
|
||||
#define CYBSP_J2_8_obj CYBSP_A11_obj
|
||||
#define CYBSP_TRACE_DATA0_obj CYBSP_A11_obj
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
||||
void init_cycfg_pins(void);
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Description:
|
||||
* Provides definitions of the SMIF-driver memory configuration.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* QSPI Configurator 4.0.0.985
|
||||
* QSPI Configurator 4.10.0.1343
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
|
|||
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
|
||||
.commandH = 0x00,
|
||||
/* The Data rate of command */
|
||||
.cmdRate = CY_SMIF_SDR
|
||||
.cmdRate = CY_SMIF_SDR,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
|
|
@ -98,7 +98,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
|
|||
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
|
||||
.commandH = 0x00,
|
||||
/* The Data rate of command */
|
||||
.cmdRate = CY_SMIF_SDR
|
||||
.cmdRate = CY_SMIF_SDR,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
|
|
@ -136,7 +136,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
|
|||
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
|
||||
.commandH = 0x00,
|
||||
/* The Data rate of command */
|
||||
.cmdRate = CY_SMIF_SDR
|
||||
.cmdRate = CY_SMIF_SDR,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
|
|
@ -174,7 +174,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
|
|||
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
|
||||
.commandH = 0x00,
|
||||
/* The Data rate of command */
|
||||
.cmdRate = CY_SMIF_SDR
|
||||
.cmdRate = CY_SMIF_SDR,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
|
|
@ -212,7 +212,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
|
|||
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
|
||||
.commandH = 0x00,
|
||||
/* The Data rate of command */
|
||||
.cmdRate = CY_SMIF_SDR
|
||||
.cmdRate = CY_SMIF_SDR,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
|
|
@ -250,7 +250,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
|
|||
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
|
||||
.commandH = 0x00,
|
||||
/* The Data rate of command */
|
||||
.cmdRate = CY_SMIF_SDR
|
||||
.cmdRate = CY_SMIF_SDR,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
|
|
@ -288,7 +288,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
|
|||
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
|
||||
.commandH = 0x00,
|
||||
/* The Data rate of command */
|
||||
.cmdRate = CY_SMIF_SDR
|
||||
.cmdRate = CY_SMIF_SDR,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
|
|
@ -326,7 +326,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
|
|||
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
|
||||
.commandH = 0x00,
|
||||
/* The Data rate of command */
|
||||
.cmdRate = CY_SMIF_SDR
|
||||
.cmdRate = CY_SMIF_SDR,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
|
|
@ -364,7 +364,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
|
|||
/* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
|
||||
.commandH = 0x00,
|
||||
/* The Data rate of command */
|
||||
.cmdRate = CY_SMIF_SDR
|
||||
.cmdRate = CY_SMIF_SDR,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
|
|
@ -409,7 +409,29 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
|
|||
#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
|
||||
/* Points to NULL or to structure with info about sectors for hybrid memory. */
|
||||
.hybridRegionCount = 0U,
|
||||
.hybridRegionInfo = NULL
|
||||
.hybridRegionInfo = 0,
|
||||
#endif
|
||||
/* Specifies the command to read variable latency cycles configuration register */
|
||||
.readLatencyCmd = 0,
|
||||
/* Specifies the command to write variable latency cycles configuration register */
|
||||
.writeLatencyCmd = 0,
|
||||
/* Specifies the address for variable latency cycle address */
|
||||
.latencyCyclesRegAddr = 0x00U,
|
||||
/* Specifies variable latency cycles Mask */
|
||||
.latencyCyclesMask = 0x00U,
|
||||
#if (CY_IP_MXSMIF_VERSION >= 2)
|
||||
/* Specifies data for memory with hybrid sectors */
|
||||
.octalDDREnableSeq = 0,
|
||||
/* Specifies the command to read the OE-containing status register. */
|
||||
.readStsRegOeCmd = 0,
|
||||
/* Specifies the command to write the OE-containing status register. */
|
||||
.writeStsRegOeCmd = 0,
|
||||
/* QE mask for the status registers */
|
||||
.stsRegOctalEnableMask = 0x00U,
|
||||
/* Octal enable register address */
|
||||
.octalEnableRegAddr = 0x00U,
|
||||
/* Frequency of operation used in Octal mode */
|
||||
.freq_of_operation = CY_SMIF_100MHZ_OPERATION,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
|
@ -441,12 +463,12 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
|
|||
* After this period the memory device is deselected. A later transfer, even from a
|
||||
* continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
|
||||
* This configuration parameter is available for CAT1B devices. */
|
||||
.mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
|
||||
.mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE,
|
||||
#endif /* CY_IP_MXSMIF_VERSION */
|
||||
};
|
||||
|
||||
const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM] = {
|
||||
&S25FL512S_SlaveSlot_0
|
||||
&S25FL512S_SlaveSlot_0,
|
||||
};
|
||||
|
||||
const cy_stc_smif_block_config_t smifBlockConfig =
|
||||
|
|
@ -458,5 +480,5 @@ const cy_stc_smif_block_config_t smifBlockConfig =
|
|||
/* The version of the SMIF driver. */
|
||||
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
|
||||
/* The version of the SMIF driver. */
|
||||
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
|
||||
.minorVersion = CY_SMIF_DRV_VERSION_MINOR,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* Description:
|
||||
* Provides declarations of the SMIF-driver memory configuration.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* QSPI Configurator 4.0.0.985
|
||||
* QSPI Configurator 4.10.0.1343
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
#define CYCFG_QSPI_MEMSLOT_H
|
||||
#include "cy_smif_memslot.h"
|
||||
|
||||
#define CY_SMIF_CFG_TOOL_VERSION (400)
|
||||
#define CY_SMIF_CFG_TOOL_VERSION (410)
|
||||
|
||||
/* Supported QSPI Driver version */
|
||||
#define CY_SMIF_DRV_VERSION_REQUIRED (100)
|
||||
|
|
@ -42,6 +42,9 @@
|
|||
#error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
|
||||
#endif
|
||||
|
||||
typedef cy_stc_smif_mem_config_t cy_serial_flash_mem_config_t;
|
||||
typedef cy_stc_smif_block_config_t cy_serial_flash_block_config_t;
|
||||
|
||||
#define CY_SMIF_DEVICE_NUM 1
|
||||
|
||||
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,26 @@
|
|||
/*******************************************************************************
|
||||
* File Name: cycfg_qspi_memslot.timestamp
|
||||
*
|
||||
* Description:
|
||||
* Sentinel file for determining if generated source is up to date.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* QSPI Configurator 4.10.0.1343
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
* an affiliate of Cypress Semiconductor Corporation.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
********************************************************************************/
|
||||
|
||||
|
|
@ -5,8 +5,8 @@
|
|||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* Establishes all necessary connections between hardware elements.
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -33,6 +33,13 @@
|
|||
#define CY_CFG_SYSCLK_PLL_ERROR 3
|
||||
#define CY_CFG_SYSCLK_FLL_ERROR 4
|
||||
#define CY_CFG_SYSCLK_WCO_ERROR 5
|
||||
#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_LF
|
||||
#define CY_CFG_SYSCLK_CLKALTSYSTICK_INTERVAL 0
|
||||
#define CY_CFG_SYSCLK_CLKALTSYSTICK_FREQUENCY 32768
|
||||
#define CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS ((0)/1000000.0)*32768
|
||||
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
|
||||
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0
|
||||
#define CY_CFG_SYSCLK_FLL_ENABLED 1
|
||||
|
|
@ -51,21 +58,10 @@
|
|||
#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
|
||||
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
|
||||
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
|
||||
#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKHF1_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
|
||||
#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 100UL
|
||||
#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
|
||||
#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
|
||||
#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
|
||||
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
|
||||
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
|
||||
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
|
||||
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
|
||||
#define CY_CFG_SYSCLK_ILO_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_ILO_HIBERNATE true
|
||||
#define CY_CFG_SYSCLK_IMO_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
|
||||
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
|
||||
|
|
@ -93,13 +89,6 @@
|
|||
#define CY_CFG_SYSCLK_PLL0_LF_MODE false
|
||||
#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
|
||||
#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 48000000
|
||||
#define CY_CFG_SYSCLK_PLL1_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 25
|
||||
#define CY_CFG_SYSCLK_PLL1_REFERENCE_DIV 1
|
||||
#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 2
|
||||
#define CY_CFG_SYSCLK_PLL1_LF_MODE false
|
||||
#define CY_CFG_SYSCLK_PLL1_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
|
||||
#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 100000000
|
||||
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
|
||||
#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0
|
||||
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
|
||||
|
|
@ -118,7 +107,7 @@
|
|||
static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig;
|
||||
#endif //defined (CY_DEVICE_SECURE)
|
||||
#if (!defined(CY_DEVICE_SECURE))
|
||||
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
|
||||
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
|
||||
{
|
||||
.fllMult = 500U,
|
||||
.refDiv = 20U,
|
||||
|
|
@ -133,37 +122,37 @@
|
|||
};
|
||||
#endif //(!defined(CY_DEVICE_SECURE))
|
||||
#if defined (CY_USING_HAL)
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLKPATH,
|
||||
.block_num = 0U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLKPATH,
|
||||
.block_num = 1U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLKPATH,
|
||||
.block_num = 2U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLKPATH,
|
||||
.block_num = 3U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLKPATH,
|
||||
.block_num = 4U,
|
||||
.channel_num = 0U,
|
||||
};
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj =
|
||||
const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj =
|
||||
{
|
||||
.type = CYHAL_RSC_CLKPATH,
|
||||
.block_num = 5U,
|
||||
|
|
@ -171,7 +160,7 @@
|
|||
};
|
||||
#endif //defined (CY_USING_HAL)
|
||||
#if (!defined(CY_DEVICE_SECURE))
|
||||
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
|
||||
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
|
||||
{
|
||||
.feedbackDiv = 30,
|
||||
.referenceDiv = 1,
|
||||
|
|
@ -179,14 +168,6 @@
|
|||
.lfMode = false,
|
||||
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
|
||||
};
|
||||
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
|
||||
{
|
||||
.feedbackDiv = 25,
|
||||
.referenceDiv = 1,
|
||||
.outputDiv = 2,
|
||||
.lfMode = false,
|
||||
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
|
||||
};
|
||||
#endif //(!defined(CY_DEVICE_SECURE))
|
||||
|
||||
__WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
|
||||
|
|
@ -206,473 +187,481 @@ __WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
|
|||
#ifdef CY_CFG_PWR_ENABLED
|
||||
secure_config->powerEnable = CY_CFG_PWR_ENABLED;
|
||||
#endif /* CY_CFG_PWR_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_PWR_USING_LDO
|
||||
secure_config->ldoEnable = CY_CFG_PWR_USING_LDO;
|
||||
#endif /* CY_CFG_PWR_USING_LDO */
|
||||
|
||||
|
||||
#ifdef CY_CFG_PWR_USING_PMIC
|
||||
secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC;
|
||||
#endif /* CY_CFG_PWR_USING_PMIC */
|
||||
|
||||
|
||||
#ifdef CY_CFG_PWR_VBACKUP_USING_VDDD
|
||||
secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD;
|
||||
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
|
||||
|
||||
|
||||
#ifdef CY_CFG_PWR_USING_ULP
|
||||
secure_config->ulpEnable = CY_CFG_PWR_USING_ULP;
|
||||
#endif /* CY_CFG_PWR_USING_ULP */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
|
||||
secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_ECO_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
|
||||
secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
|
||||
secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_ILO_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
|
||||
secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_WCO_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
|
||||
secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
|
||||
secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_PLL0_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
|
||||
secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_PLL1_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
|
||||
secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
|
||||
secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
|
||||
secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
|
||||
secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
|
||||
secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
|
||||
secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
|
||||
secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
|
||||
secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
|
||||
secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED
|
||||
secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
|
||||
secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
|
||||
secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
|
||||
secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
|
||||
secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
|
||||
secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
|
||||
secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
|
||||
secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
|
||||
secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
|
||||
secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
|
||||
#error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices.
|
||||
#error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices.
|
||||
#endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
|
||||
secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_PILO_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
|
||||
secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED;
|
||||
#endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_PWR_LDO_VOLTAGE
|
||||
secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE;
|
||||
#endif /* CY_CFG_PWR_LDO_VOLTAGE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_PWR_REGULATOR_MODE_MIN
|
||||
secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN;
|
||||
#endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
|
||||
|
||||
|
||||
#ifdef CY_CFG_PWR_BUCK_VOLTAGE
|
||||
secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE;
|
||||
#endif /* CY_CFG_PWR_BUCK_VOLTAGE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_FREQ
|
||||
secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ;
|
||||
#endif /* CY_CFG_SYSCLK_ECO_FREQ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_CLOAD
|
||||
secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD;
|
||||
#endif /* CY_CFG_SYSCLK_ECO_CLOAD */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_ESR
|
||||
secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR;
|
||||
#endif /* CY_CFG_SYSCLK_ECO_ESR */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL
|
||||
secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL;
|
||||
#endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT
|
||||
secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT;
|
||||
#endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT
|
||||
secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT;
|
||||
#endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN
|
||||
secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN;
|
||||
#endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN
|
||||
secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN;
|
||||
#endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_EXTCLK_FREQ
|
||||
secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ;
|
||||
#endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT
|
||||
secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT;
|
||||
#endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN
|
||||
secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN;
|
||||
#endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM
|
||||
secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM;
|
||||
#endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ILO_HIBERNATE
|
||||
secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE;
|
||||
#endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_WCO_BYPASS
|
||||
secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS;
|
||||
#endif /* CY_CFG_SYSCLK_WCO_BYPASS */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_WCO_IN_PRT
|
||||
secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT;
|
||||
#endif /* CY_CFG_SYSCLK_WCO_IN_PRT */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_WCO_OUT_PRT
|
||||
secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT;
|
||||
#endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_WCO_IN_PIN
|
||||
secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN;
|
||||
#endif /* CY_CFG_SYSCLK_WCO_IN_PIN */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_WCO_OUT_PIN
|
||||
secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN;
|
||||
#endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ
|
||||
secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_MULT
|
||||
secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_MULT */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_REFDIV
|
||||
secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_REFDIV */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE
|
||||
secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV
|
||||
secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE
|
||||
secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_IGAIN
|
||||
secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_IGAIN */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_PGAIN
|
||||
secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_PGAIN */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT
|
||||
secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE
|
||||
secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ
|
||||
secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ;
|
||||
#endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV
|
||||
secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV;
|
||||
#endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV
|
||||
secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV;
|
||||
#endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV
|
||||
secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV;
|
||||
#endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_LF_MODE
|
||||
secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE;
|
||||
#endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE
|
||||
secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE;
|
||||
#endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ
|
||||
secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ;
|
||||
#endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV
|
||||
secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV;
|
||||
#endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV
|
||||
secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV;
|
||||
#endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV
|
||||
secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV;
|
||||
#endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL1_LF_MODE
|
||||
secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE;
|
||||
#endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE
|
||||
secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE;
|
||||
#endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ
|
||||
secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ;
|
||||
#endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE
|
||||
secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE
|
||||
secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE
|
||||
secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE
|
||||
secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE
|
||||
secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE
|
||||
secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER
|
||||
secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER
|
||||
secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER
|
||||
secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH
|
||||
secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER
|
||||
secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ
|
||||
secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH
|
||||
secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER
|
||||
secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ
|
||||
secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH
|
||||
secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER
|
||||
secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ
|
||||
secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH
|
||||
secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER
|
||||
secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ
|
||||
secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH
|
||||
secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER
|
||||
secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ
|
||||
secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH
|
||||
secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER
|
||||
secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ
|
||||
secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ;
|
||||
#endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE
|
||||
secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER
|
||||
secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKLF_SOURCE
|
||||
secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE
|
||||
secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE
|
||||
secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER
|
||||
secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER;
|
||||
#endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE
|
||||
secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE;
|
||||
#endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD
|
||||
secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD;
|
||||
#endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME
|
||||
secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME;
|
||||
#endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ
|
||||
secure_config->altHFclkFreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ;
|
||||
#endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV
|
||||
secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV;
|
||||
#endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR
|
||||
secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR;
|
||||
#endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */
|
||||
}
|
||||
#endif //defined (CY_DEVICE_SECURE)
|
||||
__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
|
||||
{
|
||||
Cy_SysTick_Init(CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE, CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS);
|
||||
}
|
||||
#if (!defined(CY_DEVICE_SECURE))
|
||||
__STATIC_INLINE void Cy_SysClk_ClkBakInit()
|
||||
{
|
||||
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_ClkFastInit()
|
||||
{
|
||||
Cy_SysClk_ClkFastSetDivider(0U);
|
||||
|
|
@ -693,30 +682,17 @@ __WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
|
|||
Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
|
||||
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
|
||||
{
|
||||
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
|
||||
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
|
||||
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
|
||||
{
|
||||
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
|
||||
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
|
||||
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
|
||||
{
|
||||
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
|
||||
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
|
||||
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_IloInit()
|
||||
{
|
||||
/* The WDT is unlocked in the default startup code */
|
||||
Cy_SysClk_IloEnable();
|
||||
Cy_SysClk_IloHibernateOn(true);
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_ClkLfInit()
|
||||
{
|
||||
/* The WDT is unlocked in the default startup code */
|
||||
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
|
||||
{
|
||||
Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
|
||||
|
|
@ -756,17 +732,6 @@ __WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
|
|||
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
|
||||
}
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_Pll1Init()
|
||||
{
|
||||
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
|
||||
{
|
||||
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
|
||||
}
|
||||
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
|
||||
{
|
||||
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
|
||||
}
|
||||
}
|
||||
__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
|
||||
{
|
||||
Cy_SysClk_ClkSlowSetDivider(0U);
|
||||
|
|
@ -853,7 +818,7 @@ void init_cycfg_system(void)
|
|||
#if (((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL))
|
||||
#error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
|
||||
#endif
|
||||
|
||||
|
||||
configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC,
|
||||
CY_PRA_FUNC_INIT_CYCFG_DEVICE,
|
||||
&srss_0_clock_0_secureConfig);
|
||||
|
|
@ -865,7 +830,7 @@ void init_cycfg_system(void)
|
|||
Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ);
|
||||
#endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
|
||||
#else /* defined(CY_DEVICE_SECURE) */
|
||||
|
||||
|
||||
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
|
||||
Cy_SysLib_SetWaitStates(false, 150UL);
|
||||
#ifdef CY_CFG_PWR_ENABLED
|
||||
|
|
@ -875,10 +840,10 @@ void init_cycfg_system(void)
|
|||
#warning Power system will not be configured. Update power personality to v1.20 or later.
|
||||
#endif /* CY_CFG_PWR_INIT */
|
||||
#endif /* CY_CFG_PWR_ENABLED */
|
||||
|
||||
/* Disable FLL */
|
||||
Cy_SysClk_FllDeInit();
|
||||
|
||||
|
||||
/* Disable FLL */
|
||||
Cy_SysClk_FllDeInit();
|
||||
|
||||
/* Reset the core clock path to default and disable all the FLLs/PLLs */
|
||||
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
|
||||
Cy_SysClk_ClkFastSetDivider(0U);
|
||||
|
|
@ -889,58 +854,58 @@ void init_cycfg_system(void)
|
|||
(void)Cy_SysClk_PllDisable(pll);
|
||||
}
|
||||
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
|
||||
|
||||
|
||||
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
|
||||
(CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
|
||||
{
|
||||
Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
|
||||
}
|
||||
|
||||
|
||||
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
|
||||
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
|
||||
#ifdef CY_IP_MXBLESS
|
||||
(void)Cy_BLE_EcoReset();
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/* Enable all source clocks */
|
||||
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
|
||||
Cy_SysClk_PiloInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
|
||||
Cy_SysClk_WcoInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
|
||||
Cy_SysClk_ClkLfInit();
|
||||
#endif
|
||||
|
||||
|
||||
#if (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED)
|
||||
Cy_SysClk_AltHfInit();
|
||||
#endif /* (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
|
||||
Cy_SysClk_EcoInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
|
||||
Cy_SysClk_ExtClkInit();
|
||||
#endif
|
||||
|
||||
|
||||
/* Configure CPU clock dividers */
|
||||
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
|
||||
Cy_SysClk_ClkFastInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
|
||||
Cy_SysClk_ClkPeriInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
|
||||
Cy_SysClk_ClkSlowInit();
|
||||
#endif
|
||||
|
||||
|
||||
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
|
||||
/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
|
||||
Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
|
||||
|
|
@ -950,7 +915,7 @@ void init_cycfg_system(void)
|
|||
Cy_SysClk_ClkPath1Init();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Configure Path Clocks */
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
|
||||
Cy_SysClk_ClkPath0Init();
|
||||
|
|
@ -997,21 +962,21 @@ void init_cycfg_system(void)
|
|||
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
|
||||
Cy_SysClk_ClkPath15Init();
|
||||
#endif
|
||||
|
||||
|
||||
/* Configure and enable FLL */
|
||||
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
|
||||
Cy_SysClk_FllInit();
|
||||
#endif
|
||||
|
||||
|
||||
Cy_SysClk_ClkHf0Init();
|
||||
|
||||
|
||||
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
|
||||
/* Apply the ClkPath1 user setting */
|
||||
Cy_SysClk_ClkPath1Init();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Configure and enable PLLs */
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
|
||||
Cy_SysClk_Pll0Init();
|
||||
|
|
@ -1058,7 +1023,7 @@ void init_cycfg_system(void)
|
|||
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
|
||||
Cy_SysClk_Pll14Init();
|
||||
#endif
|
||||
|
||||
|
||||
/* Configure HF clocks */
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
|
||||
Cy_SysClk_ClkHf1Init();
|
||||
|
|
@ -1105,53 +1070,53 @@ void init_cycfg_system(void)
|
|||
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
|
||||
Cy_SysClk_ClkHf15Init();
|
||||
#endif
|
||||
|
||||
|
||||
/* Configure miscellaneous clocks */
|
||||
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
|
||||
Cy_SysClk_ClkTimerInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
|
||||
Cy_SysClk_ClkAltSysTickInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
|
||||
Cy_SysClk_ClkPumpInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
|
||||
Cy_SysClk_ClkBakInit();
|
||||
#endif
|
||||
|
||||
|
||||
/* Configure default enabled clocks */
|
||||
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
|
||||
Cy_SysClk_IloInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
|
||||
#error the IMO must be enabled for proper chip operation
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef CY_CFG_SYSCLK_CLKHF0_ENABLED
|
||||
#error the CLKHF0 must be enabled for proper chip operation
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* defined(CY_DEVICE_SECURE) */
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
|
||||
Cy_SysClk_MfoInit();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
|
||||
Cy_SysClk_ClkMfInit();
|
||||
#endif
|
||||
|
||||
|
||||
#if (!defined(CY_DEVICE_SECURE))
|
||||
/* Set accurate flash wait states */
|
||||
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
|
||||
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
|
||||
#endif
|
||||
|
||||
|
||||
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
|
||||
SystemCoreClockUpdate();
|
||||
#ifndef CY_CFG_SYSCLK_ILO_ENABLED
|
||||
|
|
@ -1162,9 +1127,9 @@ void init_cycfg_system(void)
|
|||
Cy_SysClk_IloDisable();
|
||||
Cy_SysClk_IloHibernateOn(false);
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* (!defined(CY_DEVICE_SECURE)) */
|
||||
|
||||
|
||||
#if defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
|
||||
Cy_SysClk_EcoPrescalerInit();
|
||||
#endif //defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
* System configuration
|
||||
* This file was automatically generated and should not be modified.
|
||||
* Configurator Backend 3.0.0
|
||||
* device-db 4.1.0.3437
|
||||
* mtb-pdl-cat1 3.3.0.21979
|
||||
* device-db 4.3.0.3855
|
||||
* mtb-pdl-cat1 3.4.0.24948
|
||||
*
|
||||
********************************************************************************
|
||||
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
@ -33,6 +33,7 @@
|
|||
#include "cy_sysclk.h"
|
||||
#include "cy_pra.h"
|
||||
#include "cy_pra_cfg.h"
|
||||
#include "cy_systick.h"
|
||||
#if defined (CY_USING_HAL)
|
||||
#include "cyhal_hwmgr.h"
|
||||
#endif //defined (CY_USING_HAL)
|
||||
|
|
@ -44,22 +45,18 @@ extern "C" {
|
|||
|
||||
#define cpuss_0_dap_0_ENABLED 1U
|
||||
#define srss_0_clock_0_ENABLED 1U
|
||||
#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
|
||||
#define srss_0_clock_0_bakclk_0_ENABLED 1U
|
||||
#define srss_0_clock_0_fastclk_0_ENABLED 1U
|
||||
#define srss_0_clock_0_fll_0_ENABLED 1U
|
||||
#define srss_0_clock_0_hfclk_0_ENABLED 1U
|
||||
#define CY_CFG_SYSCLK_CLKHF0 0UL
|
||||
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
|
||||
#define srss_0_clock_0_hfclk_1_ENABLED 1U
|
||||
#define CY_CFG_SYSCLK_CLKHF1 1UL
|
||||
#define CY_CFG_SYSCLK_CLKHF1_CLKPATH_NUM 0UL
|
||||
#define srss_0_clock_0_hfclk_3_ENABLED 1U
|
||||
#define CY_CFG_SYSCLK_CLKHF3 3UL
|
||||
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 0UL
|
||||
#define srss_0_clock_0_hfclk_4_ENABLED 1U
|
||||
#define CY_CFG_SYSCLK_CLKHF4 4UL
|
||||
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 0UL
|
||||
#define srss_0_clock_0_ilo_0_ENABLED 1U
|
||||
#define srss_0_clock_0_imo_0_ENABLED 1U
|
||||
#define srss_0_clock_0_lfclk_0_ENABLED 1U
|
||||
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
|
||||
#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_ILO
|
||||
#define srss_0_clock_0_pathmux_0_ENABLED 1U
|
||||
#define srss_0_clock_0_pathmux_1_ENABLED 1U
|
||||
#define srss_0_clock_0_pathmux_2_ENABLED 1U
|
||||
|
|
@ -68,7 +65,6 @@ extern "C" {
|
|||
#define srss_0_clock_0_pathmux_5_ENABLED 1U
|
||||
#define srss_0_clock_0_periclk_0_ENABLED 1U
|
||||
#define srss_0_clock_0_pll_0_ENABLED 1U
|
||||
#define srss_0_clock_0_pll_1_ENABLED 1U
|
||||
#define srss_0_clock_0_slowclk_0_ENABLED 1U
|
||||
#define srss_0_clock_0_timerclk_0_ENABLED 1U
|
||||
#define srss_0_power_0_ENABLED 1U
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
# Description:
|
||||
# This file contains a SMIF Bank layout for use with OpenOCD.
|
||||
# This file was automatically generated and should not be modified.
|
||||
# QSPI Configurator: 4.0.0.985
|
||||
# QSPI Configurator: 4.10.0.1343
|
||||
#
|
||||
################################################################################
|
||||
# Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
|
||||
|
|
|
|||
|
|
@ -95,6 +95,198 @@
|
|||
<Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
|
||||
</CsxProperties>
|
||||
<Widgets>
|
||||
<Widget id="Button0" type="CSD_BUTTON">
|
||||
<WidgetProperties>
|
||||
<Property id="DIPLEXING" value="false"/>
|
||||
<Property id="MAX_POS_X" value="100"/>
|
||||
<Property id="MAX_POS_Y" value="100"/>
|
||||
<Property id="FINGER_CP" value="0.16"/>
|
||||
<Property id="SNS_CLK" value="4"/>
|
||||
<Property id="ROW_SNS_CLK" value="4"/>
|
||||
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
|
||||
<Property id="TX_CLK" value="4"/>
|
||||
<Property id="TX_CLK_SOURCE" value="AUTO"/>
|
||||
<Property id="RESOLUTION" value="RES12BIT"/>
|
||||
<Property id="NUM_CONV" value="100"/>
|
||||
<Property id="IDAC_MOD0" value="32"/>
|
||||
<Property id="IDAC_MOD1" value="32"/>
|
||||
<Property id="IDAC_MOD2" value="32"/>
|
||||
<Property id="ROW_IDAC_MOD0" value="32"/>
|
||||
<Property id="ROW_IDAC_MOD1" value="32"/>
|
||||
<Property id="ROW_IDAC_MOD2" value="32"/>
|
||||
<Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
|
||||
<Property id="MAX_RAW_COUNT" value="0"/>
|
||||
<Property id="ROW_MAX_RAW_COUNT" value="0"/>
|
||||
<Property id="FINGER_TH" value="100"/>
|
||||
<Property id="PROX_TOUCH_TH" value="200"/>
|
||||
<Property id="NOISE_TH" value="40"/>
|
||||
<Property id="NNOISE_TH" value="40"/>
|
||||
<Property id="LOW_BSLN_RST" value="30"/>
|
||||
<Property id="HYSTERESIS" value="10"/>
|
||||
<Property id="ON_DEBOUNCE" value="3"/>
|
||||
<Property id="VELOCITY" value="2500"/>
|
||||
<Property id="IIR_FILTER" value="false"/>
|
||||
<Property id="IIR_FILTER_COEFF" value="128"/>
|
||||
<Property id="MEDIAN_FILTER" value="false"/>
|
||||
<Property id="AVG_FILTER" value="false"/>
|
||||
<Property id="JITTER_FILTER" value="false"/>
|
||||
<Property id="AIIR_FILTER" value="false"/>
|
||||
<Property id="AIIR_NO_MOV_TH" value="3"/>
|
||||
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
|
||||
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
|
||||
<Property id="AIIR_MAXK" value="60"/>
|
||||
<Property id="AIIR_MINK" value="1"/>
|
||||
<Property id="AIIR_DIV_VAL" value="64"/>
|
||||
<Property id="CENTROID_TYPE" value="CSD3X3"/>
|
||||
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
|
||||
<Property id="EDGE_CORRECTION" value="true"/>
|
||||
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
|
||||
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
|
||||
<Property id="TWO_FINGER_DETECTION" value="false"/>
|
||||
<Property id="BALLISTIC_MULT" value="false"/>
|
||||
<Property id="ACCEL_COEFF" value="9"/>
|
||||
<Property id="SPEED_COEFF" value="2"/>
|
||||
<Property id="DIVISOR" value="4"/>
|
||||
<Property id="SPEED_TH_X" value="3"/>
|
||||
<Property id="SPEED_TH_Y" value="4"/>
|
||||
<Property id="GESTURE_ENABLE" value="false"/>
|
||||
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
|
||||
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
|
||||
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
|
||||
<Property id="CLICK_DISTANCE_MAX" value="100"/>
|
||||
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
|
||||
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
|
||||
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
|
||||
<Property id="SCROLL_DEBOUNCE" value="3"/>
|
||||
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
|
||||
<Property id="ROTATE_DEBOUNCE" value="10"/>
|
||||
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
|
||||
<Property id="ZOOM_DEBOUNCE" value="3"/>
|
||||
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
|
||||
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
|
||||
<Property id="FLICK_DISTANCE_MIN" value="100"/>
|
||||
<Property id="EDGE_EDGE_SIZE" value="200"/>
|
||||
<Property id="EDGE_DISTANCE_MIN" value="200"/>
|
||||
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
|
||||
<Property id="EDGE_ANGLE_MAX" value="45"/>
|
||||
</WidgetProperties>
|
||||
<Electrodes>
|
||||
<Electrode id="Sns0" kind="Sensor">
|
||||
<ElectrodeProperties>
|
||||
<Property id="IDAC0" value="32"/>
|
||||
<Property id="IDAC1" value="32"/>
|
||||
<Property id="IDAC2" value="32"/>
|
||||
<Property id="PINS" value="Dedicated pin"/>
|
||||
</ElectrodeProperties>
|
||||
</Electrode>
|
||||
</Electrodes>
|
||||
</Widget>
|
||||
<Widget id="Button1" type="CSD_BUTTON">
|
||||
<WidgetProperties>
|
||||
<Property id="DIPLEXING" value="false"/>
|
||||
<Property id="MAX_POS_X" value="100"/>
|
||||
<Property id="MAX_POS_Y" value="100"/>
|
||||
<Property id="FINGER_CP" value="0.16"/>
|
||||
<Property id="SNS_CLK" value="4"/>
|
||||
<Property id="ROW_SNS_CLK" value="4"/>
|
||||
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
|
||||
<Property id="TX_CLK" value="4"/>
|
||||
<Property id="TX_CLK_SOURCE" value="AUTO"/>
|
||||
<Property id="RESOLUTION" value="RES12BIT"/>
|
||||
<Property id="NUM_CONV" value="100"/>
|
||||
<Property id="IDAC_MOD0" value="32"/>
|
||||
<Property id="IDAC_MOD1" value="32"/>
|
||||
<Property id="IDAC_MOD2" value="32"/>
|
||||
<Property id="ROW_IDAC_MOD0" value="32"/>
|
||||
<Property id="ROW_IDAC_MOD1" value="32"/>
|
||||
<Property id="ROW_IDAC_MOD2" value="32"/>
|
||||
<Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
|
||||
<Property id="MAX_RAW_COUNT" value="0"/>
|
||||
<Property id="ROW_MAX_RAW_COUNT" value="0"/>
|
||||
<Property id="FINGER_TH" value="100"/>
|
||||
<Property id="PROX_TOUCH_TH" value="200"/>
|
||||
<Property id="NOISE_TH" value="40"/>
|
||||
<Property id="NNOISE_TH" value="40"/>
|
||||
<Property id="LOW_BSLN_RST" value="30"/>
|
||||
<Property id="HYSTERESIS" value="10"/>
|
||||
<Property id="ON_DEBOUNCE" value="3"/>
|
||||
<Property id="VELOCITY" value="2500"/>
|
||||
<Property id="IIR_FILTER" value="false"/>
|
||||
<Property id="IIR_FILTER_COEFF" value="128"/>
|
||||
<Property id="MEDIAN_FILTER" value="false"/>
|
||||
<Property id="AVG_FILTER" value="false"/>
|
||||
<Property id="JITTER_FILTER" value="false"/>
|
||||
<Property id="AIIR_FILTER" value="false"/>
|
||||
<Property id="AIIR_NO_MOV_TH" value="3"/>
|
||||
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
|
||||
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
|
||||
<Property id="AIIR_MAXK" value="60"/>
|
||||
<Property id="AIIR_MINK" value="1"/>
|
||||
<Property id="AIIR_DIV_VAL" value="64"/>
|
||||
<Property id="CENTROID_TYPE" value="CSD3X3"/>
|
||||
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
|
||||
<Property id="EDGE_CORRECTION" value="true"/>
|
||||
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
|
||||
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
|
||||
<Property id="TWO_FINGER_DETECTION" value="false"/>
|
||||
<Property id="BALLISTIC_MULT" value="false"/>
|
||||
<Property id="ACCEL_COEFF" value="9"/>
|
||||
<Property id="SPEED_COEFF" value="2"/>
|
||||
<Property id="DIVISOR" value="4"/>
|
||||
<Property id="SPEED_TH_X" value="3"/>
|
||||
<Property id="SPEED_TH_Y" value="4"/>
|
||||
<Property id="GESTURE_ENABLE" value="false"/>
|
||||
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
|
||||
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
|
||||
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
|
||||
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
|
||||
<Property id="CLICK_DISTANCE_MAX" value="100"/>
|
||||
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
|
||||
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
|
||||
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
|
||||
<Property id="SCROLL_DEBOUNCE" value="3"/>
|
||||
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
|
||||
<Property id="ROTATE_DEBOUNCE" value="10"/>
|
||||
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
|
||||
<Property id="ZOOM_DEBOUNCE" value="3"/>
|
||||
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
|
||||
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
|
||||
<Property id="FLICK_DISTANCE_MIN" value="100"/>
|
||||
<Property id="EDGE_EDGE_SIZE" value="200"/>
|
||||
<Property id="EDGE_DISTANCE_MIN" value="200"/>
|
||||
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
|
||||
<Property id="EDGE_ANGLE_MAX" value="45"/>
|
||||
</WidgetProperties>
|
||||
<Electrodes>
|
||||
<Electrode id="Sns0" kind="Sensor">
|
||||
<ElectrodeProperties>
|
||||
<Property id="IDAC0" value="32"/>
|
||||
<Property id="IDAC1" value="32"/>
|
||||
<Property id="IDAC2" value="32"/>
|
||||
<Property id="PINS" value="Dedicated pin"/>
|
||||
</ElectrodeProperties>
|
||||
</Electrode>
|
||||
</Electrodes>
|
||||
</Widget>
|
||||
<Widget id="LinearSlider0" type="LINEAR_SLIDER">
|
||||
<WidgetProperties>
|
||||
<Property id="DIPLEXING" value="false"/>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<?xml version="1.0"?>
|
||||
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.20.0.3018-->
|
||||
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.20.0.2857-->
|
||||
<Configuration app="QSPI" major="2" minor="20">
|
||||
<DevicePath>PSoC 6.xml</DevicePath>
|
||||
<SlotConfigs>
|
||||
|
|
|
|||
|
|
@ -15,14 +15,16 @@
|
|||
<Personality template="mxs40csd" version="3.0">
|
||||
<Param id="CapSenseEnable" value="true"/>
|
||||
<Param id="CapSenseCore" value="4"/>
|
||||
<Param id="SensorCount" value="6"/>
|
||||
<Param id="SensorCount" value="8"/>
|
||||
<Param id="CapacitorCount" value="1"/>
|
||||
<Param id="SensorName0" value="Cmod"/>
|
||||
<Param id="SensorName1" value="LinearSlider0_Sns0"/>
|
||||
<Param id="SensorName2" value="LinearSlider0_Sns1"/>
|
||||
<Param id="SensorName3" value="LinearSlider0_Sns2"/>
|
||||
<Param id="SensorName4" value="LinearSlider0_Sns3"/>
|
||||
<Param id="SensorName5" value="LinearSlider0_Sns4"/>
|
||||
<Param id="SensorName1" value="Button0_Sns0"/>
|
||||
<Param id="SensorName2" value="Button1_Sns0"/>
|
||||
<Param id="SensorName3" value="LinearSlider0_Sns0"/>
|
||||
<Param id="SensorName4" value="LinearSlider0_Sns1"/>
|
||||
<Param id="SensorName5" value="LinearSlider0_Sns2"/>
|
||||
<Param id="SensorName6" value="LinearSlider0_Sns3"/>
|
||||
<Param id="SensorName7" value="LinearSlider0_Sns4"/>
|
||||
<Param id="CapSenseConfigurator" value="0"/>
|
||||
<Param id="CapSenseTuner" value="0"/>
|
||||
<Param id="CsdAdcEnable" value="false"/>
|
||||
|
|
@ -32,7 +34,7 @@
|
|||
<Param id="acqTime" value="10"/>
|
||||
<Param id="autoCalibrInterval" value="30"/>
|
||||
<Param id="vref" value="-1"/>
|
||||
<Param id="operClkDivider" value="1"/>
|
||||
<Param id="operClkDivider" value="2"/>
|
||||
<Param id="azTime" value="5"/>
|
||||
<Param id="csdInitTime" value="25"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
|
|
@ -43,13 +45,18 @@
|
|||
<Param id="idacInFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[0].pin[0]">
|
||||
<Alias value="CYBSP_USER_LED1"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[0].pin[1]">
|
||||
<Alias value="CYBSP_USER_LED2"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[0].pin[4]">
|
||||
<Alias value="CYBSP_SW2"/>
|
||||
<Alias value="CYBSP_USER_BTN1"/>
|
||||
<Alias value="CYBSP_USER_BTN"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[0].pin[5]">
|
||||
<Alias value="CYBSP_D8"/>
|
||||
<Alias value="CYBSP_LED_RGB_GREEN"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[10].pin[0]">
|
||||
<Alias value="CYBSP_A0"/>
|
||||
|
|
@ -83,7 +90,28 @@
|
|||
<Block location="ioss[0].port[10].pin[7]">
|
||||
<Alias value="CYBSP_A7"/>
|
||||
<Alias value="CYBSP_J2_15"/>
|
||||
<Alias value="CYBSP_MIKROBUS_AN"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[0]">
|
||||
<Alias value="CYBSP_QSPI_FRAM_SSEL"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[2]">
|
||||
<Alias value="CYBSP_QSPI_SS"/>
|
||||
<Alias value="CYBSP_QSPI_FLASH_SSEL"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[3]">
|
||||
<Alias value="CYBSP_QSPI_D3"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[4]">
|
||||
<Alias value="CYBSP_QSPI_D2"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[5]">
|
||||
<Alias value="CYBSP_QSPI_D1"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[6]">
|
||||
<Alias value="CYBSP_QSPI_D0"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[11].pin[7]">
|
||||
<Alias value="CYBSP_QSPI_SCK"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[12].pin[0]">
|
||||
<Alias value="CYBSP_SPI_MOSI"/>
|
||||
|
|
@ -107,6 +135,9 @@
|
|||
<Block location="ioss[0].port[12].pin[5]">
|
||||
<Alias value="CYBSP_SDHC_CLK"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[12].pin[6]">
|
||||
<Alias value="CYBSP_WIFI_HOST_WAKE"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[13].pin[0]">
|
||||
<Alias value="CYBSP_SDHC_IO0"/>
|
||||
</Block>
|
||||
|
|
@ -119,44 +150,47 @@
|
|||
<Block location="ioss[0].port[13].pin[3]">
|
||||
<Alias value="CYBSP_SDHC_IO3"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[13].pin[4]">
|
||||
<Alias value="CYBSP_MIKROBUS_UART_RX"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[13].pin[5]">
|
||||
<Alias value="CYBSP_MIKROBUS_UART_TX"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[13].pin[6]">
|
||||
<Alias value="CYBSP_USER_LED2"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[13].pin[7]">
|
||||
<Alias value="CYBSP_SDHC_DETECT"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[1].pin[0]">
|
||||
<Alias value="CYBSP_MIKROBUS_SPI_MOSI"/>
|
||||
<Alias value="CYBSP_CSD_RX"/>
|
||||
<Alias value="CYBSP_CS_RX"/>
|
||||
<Alias value="CYBSP_CS_TX_RX"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[1].pin[1]">
|
||||
<Alias value="CYBSP_MIKROBUS_SPI_MISO"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[1].pin[2]">
|
||||
<Alias value="CYBSP_MIKROBUS_SPI_SCK"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[1].pin[3]">
|
||||
<Alias value="CYBSP_MIKROBUS_SPI_CS"/>
|
||||
<Alias value="CYBSP_LED_RGB_RED"/>
|
||||
<Alias value="CYBSP_USER_LED3"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[1].pin[4]">
|
||||
<Alias value="CYBSP_SW4"/>
|
||||
<Alias value="CYBSP_USER_BTN2"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[1].pin[5]">
|
||||
<Alias value="CYBSP_CSD_RX"/>
|
||||
<Alias value="CYBSP_CS_RX"/>
|
||||
<Alias value="CYBSP_CS_TX_RX"/>
|
||||
<Alias value="CYBSP_LED8"/>
|
||||
<Alias value="CYBSP_USER_LED1"/>
|
||||
<Alias value="CYBSP_USER_LED"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[3].pin[0]">
|
||||
<Alias value="CYBSP_BT_UART_RX"/>
|
||||
<Block location="ioss[0].port[2].pin[0]">
|
||||
<Alias value="CYBSP_WIFI_SDIO_D0"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[3].pin[1]">
|
||||
<Alias value="CYBSP_BT_UART_TX"/>
|
||||
<Block location="ioss[0].port[2].pin[1]">
|
||||
<Alias value="CYBSP_WIFI_SDIO_D1"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[2].pin[2]">
|
||||
<Alias value="CYBSP_WIFI_SDIO_D2"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[2].pin[3]">
|
||||
<Alias value="CYBSP_WIFI_SDIO_D3"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[2].pin[4]">
|
||||
<Alias value="CYBSP_WIFI_SDIO_CMD"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[2].pin[5]">
|
||||
<Alias value="CYBSP_WIFI_SDIO_CLK"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[2].pin[7]">
|
||||
<Alias value="CYBSP_WIFI_WL_REG_ON"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[3].pin[2]">
|
||||
<Alias value="CYBSP_BT_UART_RTS"/>
|
||||
|
|
@ -183,9 +217,11 @@
|
|||
<Alias value="CYBSP_D1"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[5].pin[2]">
|
||||
<Alias value="CYBSP_DEBUG_UART_RTS"/>
|
||||
<Alias value="CYBSP_D2"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[5].pin[3]">
|
||||
<Alias value="CYBSP_DEBUG_UART_CTS"/>
|
||||
<Alias value="CYBSP_D3"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[5].pin[4]">
|
||||
|
|
@ -203,14 +239,13 @@
|
|||
<Block location="ioss[0].port[6].pin[0]">
|
||||
<Alias value="CYBSP_I2C_SCL"/>
|
||||
<Alias value="CYBSP_D15"/>
|
||||
<Alias value="CYBSP_MIKROBUS_I2C_SCL"/>
|
||||
<Alias value="CYBSP_TRUSTM_I2C_SCL"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[1]">
|
||||
<Alias value="CYBSP_I2C_SDA"/>
|
||||
<Alias value="CYBSP_D14"/>
|
||||
<Alias value="CYBSP_MIKROBUS_I2C_SDA"/>
|
||||
<Alias value="CYBSP_TRUSTM_I2C_SDA"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[2]">
|
||||
<Alias value="CYBSP_USER_BTN"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[4]">
|
||||
<Alias value="CYBSP_DEBUG_UART_RX"/>
|
||||
|
|
@ -248,6 +283,9 @@
|
|||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[0]">
|
||||
<Alias value="CYBSP_TRACE_CLK"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[1]">
|
||||
<Alias value="CYBSP_CINA"/>
|
||||
<Personality template="pin" version="3.0">
|
||||
|
|
@ -279,8 +317,8 @@
|
|||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[3]">
|
||||
<Alias value="CYBSP_CSD_SLD0"/>
|
||||
<Alias value="CYBSP_CS_SLD0"/>
|
||||
<Alias value="CYBSP_LED_RGB_BLUE"/>
|
||||
<Alias value="CYBSP_USER_LED5"/>
|
||||
<Personality template="pin" version="3.0">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
|
|
@ -294,11 +332,16 @@
|
|||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[4]">
|
||||
<Alias value="CYBSP_TRACE_DATA3"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[5]">
|
||||
<Alias value="CYBSP_MIKROBUS_RST"/>
|
||||
<Alias value="CYBSP_D8"/>
|
||||
<Alias value="CYBSP_TRACE_DATA2"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[6]">
|
||||
<Alias value="CYBSP_D9"/>
|
||||
<Alias value="CYBSP_TRACE_DATA1"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[7].pin[7]">
|
||||
<Alias value="CYBSP_CMOD"/>
|
||||
|
|
@ -315,6 +358,22 @@
|
|||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[8].pin[1]">
|
||||
<Alias value="CYBSP_CSD_BTN0"/>
|
||||
<Alias value="CYBSP_CS_BTN0"/>
|
||||
<Personality template="pin" version="3.0">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="nonSec" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[8].pin[2]">
|
||||
<Alias value="CYBSP_CSD_BTN1"/>
|
||||
<Alias value="CYBSP_CS_BTN1"/>
|
||||
|
|
@ -340,8 +399,8 @@
|
|||
<Alias value="CYBSP_CS_SLD4"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[9].pin[0]">
|
||||
<Alias value="CYBSP_CSD_SLD1"/>
|
||||
<Alias value="CYBSP_CS_SLD1"/>
|
||||
<Alias value="CYBSP_A8"/>
|
||||
<Alias value="CYBSP_J2_2"/>
|
||||
<Personality template="pin" version="3.0">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
|
|
@ -356,8 +415,8 @@
|
|||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[9].pin[1]">
|
||||
<Alias value="CYBSP_CSD_SLD2"/>
|
||||
<Alias value="CYBSP_CS_SLD2"/>
|
||||
<Alias value="CYBSP_A9"/>
|
||||
<Alias value="CYBSP_J2_4"/>
|
||||
<Personality template="pin" version="3.0">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
|
|
@ -372,8 +431,8 @@
|
|||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[9].pin[2]">
|
||||
<Alias value="CYBSP_CSD_SLD3"/>
|
||||
<Alias value="CYBSP_CS_SLD3"/>
|
||||
<Alias value="CYBSP_A10"/>
|
||||
<Alias value="CYBSP_J2_6"/>
|
||||
<Personality template="pin" version="3.0">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
|
|
@ -388,8 +447,9 @@
|
|||
</Personality>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[9].pin[3]">
|
||||
<Alias value="CYBSP_CSD_SLD4"/>
|
||||
<Alias value="CYBSP_CS_SLD4"/>
|
||||
<Alias value="CYBSP_A11"/>
|
||||
<Alias value="CYBSP_J2_8"/>
|
||||
<Alias value="CYBSP_TRACE_DATA0"/>
|
||||
<Personality template="pin" version="3.0">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
|
|
@ -414,13 +474,17 @@
|
|||
<Block location="ioss[0].port[9].pin[6]">
|
||||
<Alias value="CYBSP_A14"/>
|
||||
<Alias value="CYBSP_J2_14"/>
|
||||
<Alias value="CYBSP_TRUSTM_VDD"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[9].pin[7]">
|
||||
<Alias value="CYBSP_A15"/>
|
||||
<Alias value="CYBSP_J2_16"/>
|
||||
<Alias value="CYBSP_LED_RGB_GREEN"/>
|
||||
<Alias value="CYBSP_USER_LED4"/>
|
||||
</Block>
|
||||
<Block location="peri[0].div_16[15]">
|
||||
<Personality template="pclk" version="3.0">
|
||||
<Param id="intDivider" value="1"/>
|
||||
<Param id="fracDivider" value="0"/>
|
||||
<Param id="startOnReset" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="peri[0].div_8[0]">
|
||||
<Alias value="CYBSP_CSD_CLK_DIV"/>
|
||||
|
|
@ -431,9 +495,28 @@
|
|||
<Param id="startOnReset" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="peri[0].div_8[7]">
|
||||
<Alias value="CYBSP_TRACE_CLK_DIV"/>
|
||||
<Personality template="pclk" version="3.0">
|
||||
<Param id="intDivider" value="1"/>
|
||||
<Param id="fracDivider" value="0"/>
|
||||
<Param id="startOnReset" value="true"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0]">
|
||||
<Personality template="sysclocks" version="3.0"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].altsystickclk[0]">
|
||||
<Personality template="altsystick" version="3.0">
|
||||
<Param id="sourceClock" value="lfclk"/>
|
||||
<Param id="interval" value="0"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].bakclk[0]">
|
||||
<Personality template="bakclk" version="3.0">
|
||||
<Param id="sourceClock" value="lfclk"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].fastclk[0]">
|
||||
<Personality template="fastclk" version="2.0">
|
||||
<Param id="divider" value="1"/>
|
||||
|
|
@ -454,24 +537,6 @@
|
|||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].hfclk[1]">
|
||||
<Personality template="hfclk" version="3.0">
|
||||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].hfclk[3]">
|
||||
<Personality template="hfclk" version="3.0">
|
||||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].hfclk[4]">
|
||||
<Personality template="hfclk" version="3.0">
|
||||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].ilo[0]">
|
||||
<Personality template="ilo" version="3.0">
|
||||
<Param id="hibernate" value="true"/>
|
||||
|
|
@ -482,6 +547,11 @@
|
|||
<Param id="trim" value="1"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].lfclk[0]">
|
||||
<Personality template="lfclk" version="3.0">
|
||||
<Param id="sourceClock" value="ilo"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pathmux[0]">
|
||||
<Personality template="pathmux" version="3.0">
|
||||
<Param id="sourceClock" value="imo"/>
|
||||
|
|
@ -525,14 +595,6 @@
|
|||
<Param id="optimization" value="MinPower"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pll[1]">
|
||||
<Personality template="pll" version="3.0">
|
||||
<Param id="lowFrequencyMode" value="false"/>
|
||||
<Param id="configuration" value="auto"/>
|
||||
<Param id="desiredFrequency" value="100.000"/>
|
||||
<Param id="optimization" value="MinPower"/>
|
||||
</Personality>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].slowclk[0]">
|
||||
<Personality template="slowclk" version="2.0">
|
||||
<Param id="divider" value="1"/>
|
||||
|
|
@ -594,9 +656,19 @@
|
|||
<Arm>
|
||||
<Port name="ioss[0].port[9].pin[3].analog[0]"/>
|
||||
</Arm>
|
||||
<Arm>
|
||||
<Port name="ioss[0].port[9].pin[0].analog[0]"/>
|
||||
</Arm>
|
||||
<Arm>
|
||||
<Port name="ioss[0].port[9].pin[1].analog[0]"/>
|
||||
</Arm>
|
||||
</Mux>
|
||||
</Netlist>
|
||||
</Device>
|
||||
<Device mpn="LBEE59B1LV/CYW43012C0WKWBG">
|
||||
<BlockConfig/>
|
||||
<Netlist/>
|
||||
</Device>
|
||||
</Devices>
|
||||
<ConfiguratorData/>
|
||||
</Configuration>
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
#if defined(CY_USING_HAL)
|
||||
#include "cyhal_pin_package.h"
|
||||
#endif
|
||||
/* CAT4 does not have configurators so the BSP defines pins in a non-generated header */
|
||||
/* CAT4 and CAT5 do not have configurators so the BSP defines pins in a non-generated header */
|
||||
#if defined(COMPONENT_CAT4)
|
||||
#include "cybsp_pins.h"
|
||||
#else
|
||||
|
|
@ -739,7 +739,7 @@ extern "C" {
|
|||
/**
|
||||
* \addtogroup group_bsp_pins_capsense Capsense
|
||||
* \{
|
||||
* Pins connected to CAPSENSEâ„¢ sensors on the board.
|
||||
* Pins connected to CAPSENSE™ sensors on the board.
|
||||
*/
|
||||
|
||||
#ifdef CYBSP_CSD_TX
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
|
||||
#include "cy_result.h"
|
||||
#include "cybsp_types.h"
|
||||
#include "cycfg_pins.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
|
|
@ -37,6 +38,13 @@ extern "C" {
|
|||
#define CYBSP_USER_BTN_DRIVE (CYHAL_GPIO_DRIVE_PULLUP)
|
||||
#endif
|
||||
|
||||
#ifndef CYBSP_DEBUG_UART_CTS
|
||||
#define CYBSP_DEBUG_UART_CTS (NC)
|
||||
#endif
|
||||
#ifndef CYBSP_DEBUG_UART_RTS
|
||||
#define CYBSP_DEBUG_UART_RTS (NC)
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,80 @@
|
|||
[Device=$$TARGET_MPN$$]
|
||||
|
||||
# The "reserved resources" feature is used to ensure that the device configurator reserves the listed items
|
||||
# (blocks and routing resources) for exclusive use by the udb-sdio-whd driver's internals. If the UDB_SDIO_P<n> component
|
||||
# is changed to use a different port for the SDIO interface, the section of this file which is uncommented must be updated
|
||||
|
||||
# Uncomment this section for UDB_SDIO_P2
|
||||
#[Blocks]
|
||||
#udb[0]
|
||||
#peri[0].div_8[0]
|
||||
#cpuss[0].dw0[0].chan[0]
|
||||
#cpuss[0].dw0[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[3]
|
||||
#
|
||||
#[RoutingResources]
|
||||
#cpuss[0].dw0_tr_in[0]
|
||||
#cpuss[0].dw0_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[3]
|
||||
#
|
||||
#udb[0].tr_udb[0]
|
||||
#udb[0].tr_udb[1]
|
||||
#udb[0].tr_udb[3]
|
||||
#udb[0].tr_udb[7]
|
||||
#
|
||||
#tr_group[0].input[43]
|
||||
#tr_group[0].input[44]
|
||||
#tr_group[0].input[47]
|
||||
#tr_group[0].input[48]
|
||||
|
||||
# Uncomment this section for UDB_SDIO_P9
|
||||
#[Blocks]
|
||||
#udb[0]
|
||||
#peri[0].div_8[0]
|
||||
#cpuss[0].dw0[0].chan[0]
|
||||
#cpuss[0].dw0[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[3]
|
||||
#
|
||||
#[RoutingResources]
|
||||
#cpuss[0].dw0_tr_in[0]
|
||||
#cpuss[0].dw0_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[3]
|
||||
#
|
||||
#udb[0].tr_udb[0]
|
||||
#udb[0].tr_udb[1]
|
||||
#udb[0].tr_udb[3]
|
||||
#udb[0].tr_udb[7]
|
||||
#
|
||||
#tr_group[0].input[43]
|
||||
#tr_group[0].input[44]
|
||||
#tr_group[0].input[47]
|
||||
#tr_group[0].input[48]
|
||||
|
||||
# Uncomment this section for UDB_SDIO_P12
|
||||
[Blocks]
|
||||
udb[0]
|
||||
peri[0].div_8[0]
|
||||
cpuss[0].dw0[0].chan[0]
|
||||
cpuss[0].dw0[0].chan[1]
|
||||
cpuss[0].dw1[0].chan[1]
|
||||
cpuss[0].dw1[0].chan[3]
|
||||
|
||||
[RoutingResources]
|
||||
cpuss[0].dw0_tr_in[0]
|
||||
cpuss[0].dw0_tr_in[1]
|
||||
cpuss[0].dw1_tr_in[1]
|
||||
cpuss[0].dw1_tr_in[3]
|
||||
|
||||
udb[0].tr_udb[3]
|
||||
udb[0].tr_udb[9]
|
||||
udb[0].tr_udb[10]
|
||||
udb[0].tr_udb[14]
|
||||
|
||||
tr_group[0].input[46]
|
||||
tr_group[0].input[47]
|
||||
tr_group[0].input[48]
|
||||
tr_group[0].input[49]
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
[Device=$$TARGET_MPN$$]
|
||||
|
||||
# The "reserved resources" feature is used to ensure that the device configurator reserves the listed items
|
||||
# (blocks and routing resources) for exclusive use by the udb-sdio-whd driver's internals. If the UDB_SDIO_P<n> component
|
||||
# is changed to use a different port for the SDIO interface, the section of this file which is uncommented must be updated
|
||||
|
||||
# Uncomment this section for UDB_SDIO_P2
|
||||
[Blocks]
|
||||
udb[0]
|
||||
peri[0].div_8[0]
|
||||
cpuss[0].dw0[0].chan[0]
|
||||
cpuss[0].dw0[0].chan[1]
|
||||
cpuss[0].dw1[0].chan[1]
|
||||
cpuss[0].dw1[0].chan[3]
|
||||
|
||||
[RoutingResources]
|
||||
cpuss[0].dw0_tr_in[0]
|
||||
cpuss[0].dw0_tr_in[1]
|
||||
cpuss[0].dw1_tr_in[1]
|
||||
cpuss[0].dw1_tr_in[3]
|
||||
|
||||
udb[0].tr_udb[0]
|
||||
udb[0].tr_udb[1]
|
||||
udb[0].tr_udb[3]
|
||||
udb[0].tr_udb[7]
|
||||
|
||||
tr_group[0].input[43]
|
||||
tr_group[0].input[44]
|
||||
tr_group[0].input[47]
|
||||
tr_group[0].input[48]
|
||||
|
||||
# Uncomment this section for UDB_SDIO_P9
|
||||
#[Blocks]
|
||||
#udb[0]
|
||||
#peri[0].div_8[0]
|
||||
#cpuss[0].dw0[0].chan[0]
|
||||
#cpuss[0].dw0[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[3]
|
||||
#
|
||||
#[RoutingResources]
|
||||
#cpuss[0].dw0_tr_in[0]
|
||||
#cpuss[0].dw0_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[3]
|
||||
#
|
||||
#udb[0].tr_udb[0]
|
||||
#udb[0].tr_udb[1]
|
||||
#udb[0].tr_udb[3]
|
||||
#udb[0].tr_udb[7]
|
||||
#
|
||||
#tr_group[0].input[43]
|
||||
#tr_group[0].input[44]
|
||||
#tr_group[0].input[47]
|
||||
#tr_group[0].input[48]
|
||||
|
||||
# Uncomment this section for UDB_SDIO_P12
|
||||
#[Blocks]
|
||||
#udb[0]
|
||||
#peri[0].div_8[0]
|
||||
#cpuss[0].dw0[0].chan[0]
|
||||
#cpuss[0].dw0[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[3]
|
||||
#
|
||||
#[RoutingResources]
|
||||
#cpuss[0].dw0_tr_in[0]
|
||||
#cpuss[0].dw0_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[3]
|
||||
#
|
||||
#udb[0].tr_udb[3]
|
||||
#udb[0].tr_udb[9]
|
||||
#udb[0].tr_udb[10]
|
||||
#udb[0].tr_udb[14]
|
||||
#
|
||||
#tr_group[0].input[46]
|
||||
#tr_group[0].input[47]
|
||||
#tr_group[0].input[48]
|
||||
#tr_group[0].input[49]
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
[Device=$$TARGET_MPN$$]
|
||||
|
||||
# The "reserved resources" feature is used to ensure that the device configurator reserves the listed items
|
||||
# (blocks and routing resources) for exclusive use by the udb-sdio-whd driver's internals. If the UDB_SDIO_P<n> component
|
||||
# is changed to use a different port for the SDIO interface, the section of this file which is uncommented must be updated
|
||||
|
||||
# Uncomment this section for UDB_SDIO_P2
|
||||
#[Blocks]
|
||||
#udb[0]
|
||||
#peri[0].div_8[0]
|
||||
#cpuss[0].dw0[0].chan[0]
|
||||
#cpuss[0].dw0[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[3]
|
||||
#
|
||||
#[RoutingResources]
|
||||
#cpuss[0].dw0_tr_in[0]
|
||||
#cpuss[0].dw0_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[3]
|
||||
#
|
||||
#udb[0].tr_udb[0]
|
||||
#udb[0].tr_udb[1]
|
||||
#udb[0].tr_udb[3]
|
||||
#udb[0].tr_udb[7]
|
||||
#
|
||||
#tr_group[0].input[43]
|
||||
#tr_group[0].input[44]
|
||||
#tr_group[0].input[47]
|
||||
#tr_group[0].input[48]
|
||||
|
||||
# Uncomment this section for UDB_SDIO_P9
|
||||
[Blocks]
|
||||
udb[0]
|
||||
peri[0].div_8[0]
|
||||
cpuss[0].dw0[0].chan[0]
|
||||
cpuss[0].dw0[0].chan[1]
|
||||
cpuss[0].dw1[0].chan[1]
|
||||
cpuss[0].dw1[0].chan[3]
|
||||
|
||||
[RoutingResources]
|
||||
cpuss[0].dw0_tr_in[0]
|
||||
cpuss[0].dw0_tr_in[1]
|
||||
cpuss[0].dw1_tr_in[1]
|
||||
cpuss[0].dw1_tr_in[3]
|
||||
|
||||
udb[0].tr_udb[0]
|
||||
udb[0].tr_udb[1]
|
||||
udb[0].tr_udb[3]
|
||||
udb[0].tr_udb[7]
|
||||
|
||||
tr_group[0].input[43]
|
||||
tr_group[0].input[44]
|
||||
tr_group[0].input[47]
|
||||
tr_group[0].input[48]
|
||||
|
||||
# Uncomment this section for UDB_SDIO_P12
|
||||
#[Blocks]
|
||||
#udb[0]
|
||||
#peri[0].div_8[0]
|
||||
#cpuss[0].dw0[0].chan[0]
|
||||
#cpuss[0].dw0[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[1]
|
||||
#cpuss[0].dw1[0].chan[3]
|
||||
#
|
||||
#[RoutingResources]
|
||||
#cpuss[0].dw0_tr_in[0]
|
||||
#cpuss[0].dw0_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[1]
|
||||
#cpuss[0].dw1_tr_in[3]
|
||||
#
|
||||
#udb[0].tr_udb[3]
|
||||
#udb[0].tr_udb[9]
|
||||
#udb[0].tr_udb[10]
|
||||
#udb[0].tr_udb[14]
|
||||
#
|
||||
#tr_group[0].input[46]
|
||||
#tr_group[0].input[47]
|
||||
#tr_group[0].input[48]
|
||||
#tr_group[0].input[49]
|
||||
|
|
@ -1 +1 @@
|
|||
https://github.com/Infineon/cat1cm0p#release-v1.0.0#$$ASSET_REPO$$/cat1cm0p/release-v1.0.0
|
||||
https://github.com/Infineon/cat1cm0p#release-v1.1.0#$$ASSET_REPO$$/cat1cm0p/release-v1.1.0
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
https://github.com/cypresssemiconductorco/core-lib#release-v1.3.1#$$ASSET_REPO$$/core-lib/release-v1.3.1
|
||||
https://github.com/cypresssemiconductorco/core-lib#release-v1.4.0#$$ASSET_REPO$$/core-lib/release-v1.4.0
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
https://github.com/cypresssemiconductorco/core-make#release-v3.0.3#$$ASSET_REPO$$/core-make/release-v3.0.3
|
||||
https://github.com/cypresssemiconductorco/core-make#release-v3.2.1#$$ASSET_REPO$$/core-make/release-v3.2.1
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
https://github.com/cypresssemiconductorco/mtb-pdl-cat1#release-v3.3.0#$$ASSET_REPO$$/mtb-pdl-cat1/release-v3.3.0
|
||||
https://github.com/cypresssemiconductorco/mtb-pdl-cat1#release-v3.4.0#$$ASSET_REPO$$/mtb-pdl-cat1/release-v3.4.0
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
https://github.com/cypresssemiconductorco/recipe-make-cat1a#release-v2.0.0#$$ASSET_REPO$$/recipe-make-cat1a/release-v2.0.0
|
||||
https://github.com/cypresssemiconductorco/recipe-make-cat1a#release-v2.1.1#$$ASSET_REPO$$/recipe-make-cat1a/release-v2.1.1
|
||||
|
|
|
|||
|
|
@ -1,13 +1,15 @@
|
|||
{
|
||||
"core": {
|
||||
"version": "4.1.0.30528"
|
||||
"version": "4.2.0.33410"
|
||||
},
|
||||
"opt": {
|
||||
"props": {
|
||||
"capabilities": [
|
||||
"adc",
|
||||
"anycloud",
|
||||
"arduino",
|
||||
"bsp_gen4",
|
||||
"bt",
|
||||
"capsense",
|
||||
"capsense_button",
|
||||
"capsense_linear_slider",
|
||||
|
|
@ -15,7 +17,9 @@
|
|||
"cat1a",
|
||||
"comp",
|
||||
"csd",
|
||||
"cy8ceval_062s2",
|
||||
"cy8ckit_062s2_43012",
|
||||
"cyw43012",
|
||||
"cyw43xxx",
|
||||
"dma",
|
||||
"flash_2048k",
|
||||
"fram",
|
||||
|
|
@ -31,8 +35,8 @@
|
|||
"memory_qspi",
|
||||
"multi_core",
|
||||
"nor_flash",
|
||||
"optiga_trust_m",
|
||||
"pdm",
|
||||
"pot",
|
||||
"psoc6",
|
||||
"qspi",
|
||||
"rgb_led",
|
||||
|
|
@ -45,22 +49,23 @@
|
|||
"switch",
|
||||
"uart",
|
||||
"usb_device",
|
||||
"usb_host"
|
||||
"usb_host",
|
||||
"wifi"
|
||||
],
|
||||
"dependencies": {
|
||||
"cat1cm0p": "release-v1.0.0",
|
||||
"core-lib": "release-v1.3.1",
|
||||
"core-make": "release-v3.0.3",
|
||||
"cat1cm0p": "release-v1.1.0",
|
||||
"core-lib": "release-v1.4.0",
|
||||
"core-make": "release-v3.2.1",
|
||||
"mtb-hal-cat1": "release-v2.3.0",
|
||||
"mtb-pdl-cat1": "release-v3.3.0",
|
||||
"recipe-make-cat1a": "release-v2.0.0"
|
||||
"mtb-pdl-cat1": "release-v3.4.0",
|
||||
"recipe-make-cat1a": "release-v2.1.1"
|
||||
},
|
||||
"docs_dir": "docs",
|
||||
"flow_version": "2.0",
|
||||
"min_tools": "3.0.0",
|
||||
"template": {
|
||||
"id": "mtb-template-cat1",
|
||||
"version": "release-v1.0.0"
|
||||
"version": "release-v1.2.1"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -632,7 +632,6 @@ extern void Cy_SystemInitFpuEnable(void);
|
|||
|
||||
extern uint32_t cy_delayFreqKhz;
|
||||
extern uint8_t cy_delayFreqMhz;
|
||||
extern uint32_t cy_delay32kMs;
|
||||
/** \endcond */
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -3,7 +3,7 @@ import os
|
|||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='armclang'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
|
|
|||
Loading…
Reference in New Issue