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bsp: cvitek: Canonically rename some macro definitions 

Analysis: Some macro definition names are not standardized
and lack prefixes.

Solution: Add BSP_ prefix to GPIO_IRQ_BASE SYS_GPIO_IRQ_BASE
PLIC_PHY_ADDR TIMER_CLK_FREQ UART_IRQ_BASE I2C_IRQ_BASE.

Signed-off-by: Shicheng Chu <1468559561@qq.com>
This commit is contained in:
Z8MAN8 2024-08-18 16:24:05 +08:00 committed by Rbb666
parent fea231407b
commit f5156774b2
17 changed files with 56 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
bsp/cvitek/c906_little/.config
View File

@ -1170,7 +1170,7 @@ CONFIG_BSP_UART1_TX_PINNAME="IIC0_SCL"
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
CONFIG_UART_IRQ_BASE=30
CONFIG_BSP_UART_IRQ_BASE=30
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_SPI is not set
@ -1180,11 +1180,11 @@ CONFIG_UART_IRQ_BASE=30
# end of General Drivers Configuration
CONFIG_BSP_USING_C906_LITTLE=y
CONFIG_PLIC_PHY_ADDR=0x70000000
CONFIG_BSP_PLIC_PHY_ADDR=0x70000000
CONFIG_IRQ_MAX_NR=61
CONFIG_TIMER_CLK_FREQ=25000000
CONFIG_GPIO_IRQ_BASE=41
CONFIG_SYS_GPIO_IRQ_BASE=47
CONFIG_BSP_TIMER_CLK_FREQ=25000000
CONFIG_BSP_GPIO_IRQ_BASE=41
CONFIG_BSP_SYS_GPIO_IRQ_BASE=47
CONFIG_SOC_TYPE_SG2002=y
# CONFIG_BOARD_TYPE_MILKV_DUO is not set
# CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR is not set

8
bsp/cvitek/c906_little/Kconfig
View File

@ -18,7 +18,7 @@ config BSP_USING_C906_LITTLE
select RT_USING_USER_MAIN
default y
config PLIC_PHY_ADDR
config BSP_PLIC_PHY_ADDR
hex
default 0x70000000
@ -26,15 +26,15 @@ config IRQ_MAX_NR
int
default 61
config TIMER_CLK_FREQ
config BSP_TIMER_CLK_FREQ
int
default 25000000
config GPIO_IRQ_BASE
config BSP_GPIO_IRQ_BASE
int
default 41
config SYS_GPIO_IRQ_BASE
config BSP_SYS_GPIO_IRQ_BASE
int
default 47

4
bsp/cvitek/c906_little/board/Kconfig
View File

@ -71,7 +71,7 @@ menu "General Drivers Configuration"
default ""
endif
config UART_IRQ_BASE
config BSP_UART_IRQ_BASE
int
default 30
endif
@ -149,7 +149,7 @@ menu "General Drivers Configuration"
default ""
endif
config I2C_IRQ_BASE
config BSP_I2C_IRQ_BASE
int
default 32
endif

6
bsp/cvitek/c906_little/board/interrupt.h
View File

@ -45,9 +45,9 @@
#define PLIC_ENABLE_STRIDE 0x80
#define PLIC_CONTEXT_STRIDE 0x1000
#define PLIC_PRIORITY(id) (PLIC_PHY_ADDR + PLIC_PRIORITY_OFFSET + (id) * 4)
#define PLIC_PENDING(id) (PLIC_PHY_ADDR + PLIC_PENDING_OFFSET + ((id) / 32))
#define PLIC_ENABLE(id) (PLIC_PHY_ADDR + PLIC_ENABLE_OFFSET + ((id) / 32))
#define PLIC_PRIORITY(id) (BSP_PLIC_PHY_ADDR + PLIC_PRIORITY_OFFSET + (id) * 4)
#define PLIC_PENDING(id) (BSP_PLIC_PHY_ADDR + PLIC_PENDING_OFFSET + ((id) / 32))
#define PLIC_ENABLE(id) (BSP_PLIC_PHY_ADDR + PLIC_ENABLE_OFFSET + ((id) / 32))
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);

6
bsp/cvitek/c906_little/board/tick.c
View File

@ -17,7 +17,7 @@
static volatile rt_uint64_t time_elapsed = 0;
static volatile unsigned long tick_cycles = 0;
#define CLINT_BASE (PLIC_PHY_ADDR + 0x4000000UL)
#define CLINT_BASE (BSP_PLIC_PHY_ADDR + 0x4000000UL)
static volatile rt_uint32_t *mtimecmp_l = (volatile rt_uint32_t *)(CLINT_BASE + 0x4000UL);
static volatile rt_uint32_t *mtimecmp_h = (volatile rt_uint32_t *)(CLINT_BASE + 0x4004UL);
@ -50,7 +50,7 @@ int rt_hw_tick_init(void)
/* Clear the Machine-Timer bit in MIE */
clear_csr(mie, MIP_MTIP);
tick_cycles = TIMER_CLK_FREQ / RT_TICK_PER_SECOND;
tick_cycles = BSP_TIMER_CLK_FREQ / RT_TICK_PER_SECOND;
set_ticks(get_ticks() + tick_cycles);
@ -74,7 +74,7 @@ void rt_hw_us_delay(rt_uint32_t us)
unsigned long run_time;
start_time = get_ticks();
end_time = start_time + us * (TIMER_CLK_FREQ / 1000000);
end_time = start_time + us * (BSP_TIMER_CLK_FREQ / 1000000);
do{
run_time = get_ticks();
} while(run_time < end_time);

10
bsp/cvitek/c906_little/rtconfig.h
View File

@ -326,14 +326,14 @@
#define BSP_USING_UART1
#define BSP_UART1_RX_PINNAME "IIC0_SDA"
#define BSP_UART1_TX_PINNAME "IIC0_SCL"
#define UART_IRQ_BASE 30
#define BSP_UART_IRQ_BASE 30
/* end of General Drivers Configuration */
#define BSP_USING_C906_LITTLE
#define PLIC_PHY_ADDR 0x70000000
#define BSP_PLIC_PHY_ADDR 0x70000000
#define IRQ_MAX_NR 61
#define TIMER_CLK_FREQ 25000000
#define GPIO_IRQ_BASE 41
#define SYS_GPIO_IRQ_BASE 47
#define BSP_TIMER_CLK_FREQ 25000000
#define BSP_GPIO_IRQ_BASE 41
#define BSP_SYS_GPIO_IRQ_BASE 47
#define SOC_TYPE_SG2002
#define BOARD_TYPE_MILKV_DUO256M

6
bsp/cvitek/cv18xx_aarch64/.config
View File

@ -1255,8 +1255,8 @@ CONFIG_RT_USING_MEMBLOCK=y
# end of RT-Thread online packages
CONFIG_SOC_CV18XX_AARCH64=y
CONFIG_GPIO_IRQ_BASE=76
CONFIG_SYS_GPIO_IRQ_BASE=86
CONFIG_BSP_GPIO_IRQ_BASE=76
CONFIG_BSP_SYS_GPIO_IRQ_BASE=86
CONFIG_SOC_TYPE_SG2002=y
CONFIG_BOARD_TYPE_MILKV_DUO256M=y
# CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set
@ -1276,7 +1276,7 @@ CONFIG_BSP_UART0_TX_PINNAME="UART0_TX"
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
CONFIG_UART_IRQ_BASE=60
CONFIG_BSP_UART_IRQ_BASE=60
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_PWM is not set

4
bsp/cvitek/cv18xx_aarch64/Kconfig
View File

@ -22,11 +22,11 @@ config SOC_CV18XX_AARCH64
select ARCH_MM_MMU
default y
config GPIO_IRQ_BASE
config BSP_GPIO_IRQ_BASE
int
default 76
config SYS_GPIO_IRQ_BASE
config BSP_SYS_GPIO_IRQ_BASE
int
default 86

2
bsp/cvitek/cv18xx_aarch64/board/Kconfig
View File

@ -89,7 +89,7 @@ menu "General Drivers Configuration"
default ""
endif
config UART_IRQ_BASE
config BSP_UART_IRQ_BASE
int
default 60
endif

6
bsp/cvitek/cv18xx_aarch64/rtconfig.h
View File

@ -407,8 +407,8 @@
/* end of Arduino libraries */
/* end of RT-Thread online packages */
#define SOC_CV18XX_AARCH64
#define GPIO_IRQ_BASE 76
#define SYS_GPIO_IRQ_BASE 86
#define BSP_GPIO_IRQ_BASE 76
#define BSP_SYS_GPIO_IRQ_BASE 86
#define SOC_TYPE_SG2002
#define BOARD_TYPE_MILKV_DUO256M
@ -421,7 +421,7 @@
#define BSP_USING_UART0
#define BSP_UART0_RX_PINNAME "UART0_RX"
#define BSP_UART0_TX_PINNAME "UART0_TX"
#define UART_IRQ_BASE 60
#define BSP_UART_IRQ_BASE 60
/* end of General Drivers Configuration */
#endif

7
bsp/cvitek/cv18xx_risc-v/.config
View File

@ -1315,7 +1315,7 @@ CONFIG_BSP_UART0_TX_PINNAME="UART0_TX"
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
CONFIG_UART_IRQ_BASE=44
CONFIG_BSP_UART_IRQ_BASE=44
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_SPI is not set
@ -1329,9 +1329,8 @@ CONFIG_UART_IRQ_BASE=44
CONFIG_BSP_USING_CV18XX=y
CONFIG_C906_PLIC_PHY_ADDR=0x70000000
CONFIG_IRQ_MAX_NR=101
CONFIG_TIMER_CLK_FREQ=25000000
CONFIG_GPIO_IRQ_BASE=60
CONFIG_SYS_GPIO_IRQ_BASE=70
CONFIG_BSP_GPIO_IRQ_BASE=60
CONFIG_BSP_SYS_GPIO_IRQ_BASE=70
CONFIG___STACKSIZE__=8192
CONFIG_SOC_TYPE_SG2002=y
# CONFIG_BOARD_TYPE_MILKV_DUO is not set

8
bsp/cvitek/cv18xx_risc-v/Kconfig
View File

@ -31,15 +31,11 @@ config IRQ_MAX_NR
int
default 101
config TIMER_CLK_FREQ
int
default 25000000
config GPIO_IRQ_BASE
config BSP_GPIO_IRQ_BASE
int
default 60
config SYS_GPIO_IRQ_BASE
config BSP_SYS_GPIO_IRQ_BASE
int
default 70

4
bsp/cvitek/cv18xx_risc-v/board/Kconfig
View File

@ -71,7 +71,7 @@ menu "General Drivers Configuration"
default ""
endif
config UART_IRQ_BASE
config BSP_UART_IRQ_BASE
int
default 44
endif
@ -149,7 +149,7 @@ menu "General Drivers Configuration"
default ""
endif
config I2C_IRQ_BASE
config BSP_I2C_IRQ_BASE
int
default 49
endif

7
bsp/cvitek/cv18xx_risc-v/rtconfig.h
View File

@ -448,14 +448,13 @@
#define BSP_USING_UART0
#define BSP_UART0_RX_PINNAME "UART0_RX"
#define BSP_UART0_TX_PINNAME "UART0_TX"
#define UART_IRQ_BASE 44
#define BSP_UART_IRQ_BASE 44
/* end of General Drivers Configuration */
#define BSP_USING_CV18XX
#define C906_PLIC_PHY_ADDR 0x70000000
#define IRQ_MAX_NR 101
#define TIMER_CLK_FREQ 25000000
#define GPIO_IRQ_BASE 60
#define SYS_GPIO_IRQ_BASE 70
#define BSP_GPIO_IRQ_BASE 60
#define BSP_SYS_GPIO_IRQ_BASE 70
#define __STACKSIZE__ 8192
#define SOC_TYPE_SG2002
#define BOARD_TYPE_MILKV_DUO256M

10
bsp/cvitek/drivers/drv_gpio.c
View File

@ -271,7 +271,7 @@ static void rt_hw_gpio_isr(int irqno, void *param)
rt_uint32_t pending, mask;
mask = 0;
port = (irqno == SYS_GPIO_IRQ_BASE ? 4 : (irqno - GPIO_IRQ_BASE));
port = (irqno == BSP_SYS_GPIO_IRQ_BASE ? 4 : (irqno - BSP_GPIO_IRQ_BASE));
base_addr = (port == 4 ? dwapb_gpio_base_e : (dwapb_gpio_base + DWAPB_GPIO_SIZE * port));
pending = dwapb_read32(base_addr + GPIO_INTSTATUS);
@ -306,16 +306,16 @@ int rt_hw_gpio_init(void)
rt_device_pin_register("gpio", &_dwapb_ops, RT_NULL);
#define INT_INSTALL_GPIO_DEVICE(no) \
rt_hw_interrupt_install(GPIO_IRQ_BASE + (no), rt_hw_gpio_isr, RT_NULL, "gpio"); \
rt_hw_interrupt_umask(GPIO_IRQ_BASE + (no));
rt_hw_interrupt_install(BSP_GPIO_IRQ_BASE + (no), rt_hw_gpio_isr, RT_NULL, "gpio"); \
rt_hw_interrupt_umask(BSP_GPIO_IRQ_BASE + (no));
INT_INSTALL_GPIO_DEVICE(0);
INT_INSTALL_GPIO_DEVICE(1);
INT_INSTALL_GPIO_DEVICE(2);
INT_INSTALL_GPIO_DEVICE(3);
rt_hw_interrupt_install(SYS_GPIO_IRQ_BASE, rt_hw_gpio_isr, RT_NULL, "gpio");
rt_hw_interrupt_umask(SYS_GPIO_IRQ_BASE);
rt_hw_interrupt_install(BSP_SYS_GPIO_IRQ_BASE, rt_hw_gpio_isr, RT_NULL, "gpio");
rt_hw_interrupt_umask(BSP_SYS_GPIO_IRQ_BASE);
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_gpio_init);

10
bsp/cvitek/drivers/drv_hw_i2c.h
View File

@ -29,11 +29,11 @@
#define I2C3_BASE 0x4030000
#define I2C4_BASE 0x4040000
#define I2C0_IRQ (I2C_IRQ_BASE + 0)
#define I2C1_IRQ (I2C_IRQ_BASE + 1)
#define I2C2_IRQ (I2C_IRQ_BASE + 2)
#define I2C3_IRQ (I2C_IRQ_BASE + 3)
#define I2C4_IRQ (I2C_IRQ_BASE + 4)
#define I2C0_IRQ (BSP_I2C_IRQ_BASE + 0)
#define I2C1_IRQ (BSP_I2C_IRQ_BASE + 1)
#define I2C2_IRQ (BSP_I2C_IRQ_BASE + 2)
#define I2C3_IRQ (BSP_I2C_IRQ_BASE + 3)
#define I2C4_IRQ (BSP_I2C_IRQ_BASE + 4)
#if !defined(IC_CLK)

10
bsp/cvitek/drivers/drv_uart.h
View File

@ -26,11 +26,11 @@
#define UART3_BASE 0x04170000
#define UART4_BASE 0x041C0000
#define UART0_IRQ (UART_IRQ_BASE + 0)
#define UART1_IRQ (UART_IRQ_BASE + 1)
#define UART2_IRQ (UART_IRQ_BASE + 2)
#define UART3_IRQ (UART_IRQ_BASE + 3)
#define UART4_IRQ (UART_IRQ_BASE + 4)
#define UART0_IRQ (BSP_UART_IRQ_BASE + 0)
#define UART1_IRQ (BSP_UART_IRQ_BASE + 1)
#define UART2_IRQ (BSP_UART_IRQ_BASE + 2)
#define UART3_IRQ (BSP_UART_IRQ_BASE + 3)
#define UART4_IRQ (BSP_UART_IRQ_BASE + 4)
/*
* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the