From c0f0c2322f9439fda4fc98f5b13e6cbb98cf92a5 Mon Sep 17 00:00:00 2001 From: Grissiom Date: Tue, 8 Apr 2014 11:24:04 +0800 Subject: [PATCH 1/2] [libcpu/arm] remove useless cpsr updating in rt_hw_context_switch_to This piece of code will enable the interrupt early before switching to the first thread. Although it is harmless, but not prefect. --- libcpu/arm/realview-a8-vmm/context_gcc.S | 3 --- 1 file changed, 3 deletions(-) diff --git a/libcpu/arm/realview-a8-vmm/context_gcc.S b/libcpu/arm/realview-a8-vmm/context_gcc.S index 9bb31e3f10..dba0095632 100644 --- a/libcpu/arm/realview-a8-vmm/context_gcc.S +++ b/libcpu/arm/realview-a8-vmm/context_gcc.S @@ -57,9 +57,6 @@ rt_hw_context_switch_to: ldmfd sp!, {r4} @ pop new task spsr msr spsr_cxsf, r4 - bic r4, r4, #0x20 @ must be ARM mode - msr cpsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc .section .bss.share.isr From 2b7be29cade03e7648f00500d8f8993442222485 Mon Sep 17 00:00:00 2001 From: Grissiom Date: Tue, 8 Apr 2014 11:54:03 +0800 Subject: [PATCH 2/2] [bsp/rva8] enable group{0,1} interrupt forwarding in gic initialization When RT-Thread is running stand alone, it forgot to enable the distributor of GIC. --- libcpu/arm/realview-a8-vmm/gic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/libcpu/arm/realview-a8-vmm/gic.c b/libcpu/arm/realview-a8-vmm/gic.c index db26fc5dcf..4cff1bad3e 100644 --- a/libcpu/arm/realview-a8-vmm/gic.c +++ b/libcpu/arm/realview-a8-vmm/gic.c @@ -249,6 +249,9 @@ int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) for (i = 0; i < _gic_max_irq; i += 32) GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; + /* Enable group0 and group1 interrupt forwarding. */ + GIC_DIST_CTRL(dist_base) = 0x03; + return 0; }