1. [bsp][sam9260] Fix the path of gcc tool chain for travis-ci
2. [bsp][sam9260] Remove unused ld file 3. [bsp][sam9260] Add J-Link debug scripts
This commit is contained in:
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cf3d639fcb
commit
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x20000000;
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.text :
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*(.init)
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*(.text)
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*(.gnu.linkonce.t*)
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/* section information for finsh shell */
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(4);
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. = ALIGN(4);
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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. = ALIGN(4);
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/* section information for modules */
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. = ALIGN(4);
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__rtmsymtab_start = .;
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KEEP(*(RTMSymTab))
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__rtmsymtab_end = .;
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}
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. = ALIGN(4);
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.rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
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. = ALIGN(4);
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.ctors :
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{
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PROVIDE(__ctors_start__ = .);
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KEEP(*(SORT(.ctors.*)))
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KEEP(*(.ctors))
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PROVIDE(__ctors_end__ = .);
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}
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.dtors :
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{
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PROVIDE(__dtors_start__ = .);
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KEEP(*(SORT(.dtors.*)))
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KEEP(*(.dtors))
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PROVIDE(__dtors_end__ = .);
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}
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. = ALIGN(4);
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.data :
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{
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d*)
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}
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. = ALIGN(4);
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.nobss : { *(.nobss) }
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. = 0x20300000;
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. = ALIGN(4);
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__bss_start = .;
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.bss : { *(.bss) }
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__bss_end = .;
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/* stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_info 0 : { *(.debug_info) }
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.debug_line 0 : { *(.debug_line) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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_end = .;
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}
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@ -0,0 +1,248 @@
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// ----------------------------------------------------------------------------
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// ATMEL Microcontroller Software Support
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// ----------------------------------------------------------------------------
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// Copyright (c) 2008, Atmel Corporation
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the disclaimer below.
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//
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// Atmel's name may not be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// File Name : at91sam9260-ek-sdram.ini
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// Object : Generic Macro File for KEIL
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// _MapRAMAt0()
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// Function description: Maps RAM at 0.
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//----------------------------------------------------------------------------
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DEFINE INT __mac_i;
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FUNC void _MapRAMAt0(){
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printf ("Changing mapping: RAM mapped to 0 \n");
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// Test and set Remap
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__mac_i = _RDWORD(0xFFFFEF00);
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if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0))
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{
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_WDWORD(0xFFFFEF00,0x03); // toggle remap bits
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}
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else
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{
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printf ("------------------------------- The Remap is done -----------------------------------\n");
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}
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}
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//----------------------------------------------------------------------------
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// _InitRSTC()
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// Function description
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// Initializes the RSTC (Reset controller).
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// This makes sense since the default is to not allow user resets, which makes it impossible to
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// apply a second RESET via J-Link
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//----------------------------------------------------------------------------
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FUNC void _InitRSTC() {
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_WDWORD(0xFFFFFD08,0xA5000001); // Allow user reset
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}
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//----------------------------------------------------------------------------
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//
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// _PllSetting()
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// Function description
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// Initializes the PMC.
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// 1. Enable the Main Oscillator
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// 2. Configure PLL
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// 3. Switch Master
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//----------------------------------------------------------------------------
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FUNC void __PllSetting()
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{
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if ((_RDWORD(0xFFFFFC30)&0x3) != 0 )
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{
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// Disable all PMC interrupt ( $$ JPP)
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// AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
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// pPmc->PMC_IDR = 0xFFFFFFFF;
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_WDWORD(0xFFFFFC64,0xFFFFFFFF);
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// AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
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_WDWORD(0xFFFFFC14,0xFFFFFFFF);
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// Disable all clock only Processor clock is enabled.
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_WDWORD(0xFFFFFC04,0xFFFFFFFE);
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// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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_WDWORD(0xFFFFFC30,0x00000001);
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_sleep_(10);
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// write reset value to PLLA and PLLB
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// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
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_WDWORD(0xFFFFFC28,0x00003F00);
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// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
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_WDWORD(0xFFFFFC2C,0x00003F00);
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_sleep_(10);
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printf ( "------------------------------- PLL Enable -----------------------------------------");
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}
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else {
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printf( " ********* Core in SLOW CLOCK mode ********* ");
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}
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}
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//----------------------------------------------------------------------------
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//
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// __PllSetting100MHz()
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// Function description
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||||
// Set core at 200 MHz and MCK at 100 MHz
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//----------------------------------------------------------------------------
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FUNC void __PllSetting100MHz()
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{
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printf( "------------------------------- PLL Set at 100 MHz ----------------------------------");
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//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
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_WDWORD(0xFFFFFC20,0x00004001);
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_sleep_(10);
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// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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_WDWORD(0xFFFFFC30,0x00000001);
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_sleep_(10);
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//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
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// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
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_WDWORD(0xFFFFFC28,0x2060BF09);
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_sleep_(10);
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// Configure PLLB
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_WDWORD(0xFFFFFC2C,0x207C3F0C);
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_sleep_(10);
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//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
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_WDWORD(0xFFFFFC30,0x00000102);
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_sleep_(10);
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}
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//----------------------------------------------------------------------------
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// __initSDRAM()
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// Function description
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// Set SDRAM for works at 100 MHz
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//----------------------------------------------------------------------------
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FUNC void __initSDRAM()
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{
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// Configure EBI Chip select
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// pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
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// AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
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_WDWORD(0xFFFFEF1C,0x0001003A);
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// Configure PIOs
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// AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
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// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
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// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
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// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
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_WDWORD(0xFFFFF870,0xFFFF0000);
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_WDWORD(0xFFFFF874,0x00000000);
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_WDWORD(0xFFFFF804,0xFFFF0000);
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// psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |
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// AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
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// AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
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_WDWORD(0xFFFFEA08,0x85227259);
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_sleep_(10);
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// psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL
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_WDWORD(0xFFFFEA00,0x00000002);
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// *AT91C_SDRAM = 0x00000000; // Perform PRCHG
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_WDWORD(0x20000000,0x00000000);
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_sleep_(10);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+4) = 0x00000001; // Perform CBR
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_WDWORD(0x20000010,0x00000001);
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// psdrc->SDRAMC_MR = 0x00000004; // Set 2 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+8) = 0x00000002; // Perform CBR
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_WDWORD(0x20000020,0x00000002);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0xc) = 0x00000003; // Perform CBR
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_WDWORD(0x20000030,0x00000003);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x10) = 0x00000004; // Perform CBR
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_WDWORD(0x20000040,0x00000004);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x14) = 0x00000005; // Perform CBR
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_WDWORD(0x20000050,0x00000005);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x18) = 0x00000006; // Perform CBR
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_WDWORD(0x20000060,0x00000006);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x1c) = 0x00000007; // Perform CBR
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_WDWORD(0x20000070,0x00000007);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x20) = 0x00000008; // Perform CBR
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_WDWORD(0x20000080,0x00000008);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
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_WDWORD(0xFFFFEA00,0x00000003);
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// *(AT91C_SDRAM+0x24) = 0xcafedede; // Perform LMR burst=1, lat=2
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_WDWORD(0x20000090,0xCAFEDEDE);
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// psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
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_WDWORD(0xFFFFEA04,0x000002B9);
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
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_WDWORD(0xFFFFEA00,0x00000000);
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//* *AT91C_SDRAM = 0x00000000; // Perform Normal mode
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_WDWORD(0x20000000,0x00000000);
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printf( "------------------------------- SDRAM Done at 100 MHz -------------------------------");
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}
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__PllSetting(); //* Init PLL
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__PllSetting100MHz();
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__initSDRAM();
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_MapRAMAt0(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
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_InitRSTC();
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DEBUG_CLOCK = 2000000;
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LOAD Objects\\template.axf INCREMENTAL
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PC = 0x20000000;
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//g,main
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@ -0,0 +1,252 @@
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// ---------------------------------------------------------
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||||
// ATMEL Microcontroller Software Support - ROUSSET -
|
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// ---------------------------------------------------------
|
||||
// The software is delivered "AS IS" without warranty or
|
||||
// condition of any kind, either express, implied or
|
||||
// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
|
||||
// for any particular purpose, or against the infringements of
|
||||
// intellectual property rights of others.
|
||||
// ---------------------------------------------------------
|
||||
// File: SAM9_SDRAM.mac
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||||
// User setup file for CSPY debugger.
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||||
// 1.1 08/Aug/06 jpp : Creation
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||||
//
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||||
// $Revision: 1.1.2.1 $
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//
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// ---------------------------------------------------------
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__var __mac_i;
|
||||
__var __mac_pt;
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* execUserReset() : JTAG set initially to Full Speed
|
||||
*/
|
||||
execUserReset()
|
||||
{
|
||||
__message "------------------------------ execUserReset ---------------------------------";
|
||||
_MapRAMAt0(); //* Set the RAM memory at 0x00200000 & 0x00000000
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||||
__PllSetting(); //* Init PLL
|
||||
__PllSetting100MHz();
|
||||
__message "-------------------------------Set PC Reset ----------------------------------";
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* execUserPreload() : JTAG set initially to 32kHz
|
||||
*/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload ---------------------------------";
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||||
__hwReset(0); //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
|
||||
__writeMemory32(0xD3,0x98,"Register"); //* Set CPSR
|
||||
__PllSetting(); //* Init PLL
|
||||
__PllSetting100MHz();
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||||
__initSDRAM(); //* Init SDRAM before load
|
||||
_MapRAMAt0(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
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||||
_InitRSTC(); //* Enable User Reset to allow execUserReset() execution
|
||||
}
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||||
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||||
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||||
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||||
/*********************************************************************
|
||||
*
|
||||
* _InitRSTC()
|
||||
*
|
||||
* Function description
|
||||
* Initializes the RSTC (Reset controller).
|
||||
* This makes sense since the default is to not allow user resets, which makes it impossible to
|
||||
* apply a second RESET via J-Link
|
||||
*/
|
||||
_InitRSTC() {
|
||||
__writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user reset
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* __initSDRAM()
|
||||
* Function description
|
||||
* Set SDRAM for works at 100 MHz
|
||||
*/
|
||||
__initSDRAM()
|
||||
{
|
||||
//* Configure EBI Chip select
|
||||
// pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC | (1 << 16);
|
||||
// AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
|
||||
__writeMemory32(0x0001003A,0xFFFFEF1C,"Memory");
|
||||
|
||||
|
||||
//* Configure PIOs
|
||||
//* AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
|
||||
// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
|
||||
// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
|
||||
// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
|
||||
__writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");
|
||||
__writeMemory32(0x00000000,0xFFFFF874,"Memory");
|
||||
__writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |
|
||||
// AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
|
||||
// AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
|
||||
__writeMemory32(0x85227259,0xFFFFEA08,"Memory");
|
||||
__delay(1); //100
|
||||
//* psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL
|
||||
__writeMemory32(0x00000002,0xFFFFEA00,"Memory");
|
||||
//* *AT91C_SDRAM = 0x00000000; // Perform PRCHG
|
||||
__writeMemory32(0x00000000,0x20000000,"Memory");
|
||||
__delay(1); //100
|
||||
|
||||
|
||||
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
|
||||
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
|
||||
|
||||
//* *(AT91C_SDRAM+4) = 0x00000001; // Perform CBR
|
||||
__writeMemory32(0x00000001,0x20000010,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_MR = 0x00000004; // Set 2 CBR
|
||||
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
|
||||
//* *(AT91C_SDRAM+8) = 0x00000002; // Perform CBR
|
||||
__writeMemory32(0x00000002,0x20000020,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR
|
||||
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
|
||||
//* *(AT91C_SDRAM+0xc) = 0x00000003; // Perform CBR
|
||||
__writeMemory32(0x00000003,0x20000030,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR
|
||||
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
|
||||
//* *(AT91C_SDRAM+0x10) = 0x00000004; // Perform CBR
|
||||
__writeMemory32(0x00000004,0x20000040,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR
|
||||
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
|
||||
//* *(AT91C_SDRAM+0x14) = 0x00000005; // Perform CBR
|
||||
__writeMemory32(0x00000005,0x20000050,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR
|
||||
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
|
||||
//* *(AT91C_SDRAM+0x18) = 0x00000006; // Perform CBR
|
||||
__writeMemory32(0x00000006,0x20000060,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR
|
||||
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
|
||||
//* *(AT91C_SDRAM+0x1c) = 0x00000007; // Perform CBR
|
||||
__writeMemory32(0x00000007,0x20000070,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR
|
||||
__writeMemory32(0x00000004,0xFFFFEA00,"Memory");
|
||||
//* *(AT91C_SDRAM+0x20) = 0x00000008; // Perform CBR
|
||||
__writeMemory32(0x00000008,0x20000080,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
|
||||
__writeMemory32(0x00000003,0xFFFFEA00,"Memory");
|
||||
//* *(AT91C_SDRAM+0x24) = 0xcafedede; // Perform LMR burst=1, lat=2
|
||||
__writeMemory32(0xCAFEDEDE,0x20000090,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
|
||||
// // (F : system clock freq. MHz
|
||||
|
||||
__writeMemory32(0x000002B7,0xFFFFEA04,"Memory");
|
||||
|
||||
//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
|
||||
__writeMemory32(0x00000000,0xFFFFEA00,"Memory");
|
||||
|
||||
//* *AT91C_SDRAM = 0x00000000; // Perform Normal mode
|
||||
__writeMemory32(0x00000000,0x20000000,"Memory");
|
||||
__message "------------------------------- SDRAM Done at 100 MHz -------------------------------";
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* _MapRAMAt0()
|
||||
* Function description
|
||||
* Remap RAM at 0
|
||||
*/
|
||||
_MapRAMAt0()
|
||||
{
|
||||
// AT91C_MATRIX_MRCR ((AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
|
||||
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
|
||||
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
|
||||
|
||||
if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
|
||||
__message "------------------------------- The Remap is NOT & REMAP ----------------------------";
|
||||
__writeMemory32(0x00000003,0xFFFFEF00,"Memory");
|
||||
__mac_i=__readMemory32(0xFFFFEF00,"Memory");
|
||||
__message "----- AT91C_MATRIX_MRCR : 0x",__mac_i:%X;
|
||||
} else {
|
||||
__message "------------------------------- The Remap is done -----------------------------------";
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* __PllSetting()
|
||||
* Function description
|
||||
* Initializes the PMC.
|
||||
* 1. Enable the Main Oscillator
|
||||
* 2. Configure PLL
|
||||
* 3. Switch Master
|
||||
*/
|
||||
__PllSetting()
|
||||
{
|
||||
if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
|
||||
//* Disable all PMC interrupt ( $$ JPP)
|
||||
//* AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
|
||||
//* pPmc->PMC_IDR = 0xFFFFFFFF;
|
||||
__writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
|
||||
//* AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
|
||||
__writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
|
||||
// Disable all clock only Processor clock is enabled.
|
||||
__writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
|
||||
|
||||
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
|
||||
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
|
||||
__delay(10); //10000
|
||||
|
||||
// write reset value to PLLA and PLLB
|
||||
// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
|
||||
__writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
|
||||
|
||||
// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
|
||||
__writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
|
||||
__delay(10); //10000
|
||||
|
||||
__message "------------------------------- PLL Enable -----------------------------------------";
|
||||
} else {
|
||||
__message " ********* Core in SLOW CLOCK mode ********* "; }
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* __PllSetting100MHz()
|
||||
* Function description
|
||||
* Set core at 200 MHz and MCK at 100 MHz
|
||||
*/
|
||||
__PllSetting100MHz()
|
||||
{
|
||||
|
||||
__message "------------------------------- PLL Set at 100 MHz ----------------------------------";
|
||||
|
||||
//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
|
||||
__writeMemory32(0x00004001,0xFFFFFC20,"Memory");
|
||||
__delay(10); //10000
|
||||
// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
|
||||
__writeMemory32(0x00000001,0xFFFFFC30,"Memory");
|
||||
__delay(10); //10000
|
||||
//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
|
||||
// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
|
||||
__writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
|
||||
__delay(10); //10000
|
||||
// AT91C_BASE_PMC->PMC_PLLBR = BOARD_USBDIV| BOARD_CKGR_PLLB | BOARD_PLLBCOUNT | BOARD_MULB| BOARD_DIVB;
|
||||
__writeMemory32(0x207C3F0C,0xFFFFFC2C,"Memory");
|
||||
__delay(10); //10000
|
||||
//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
|
||||
__writeMemory32(0x00000102,0xFFFFFC30,"Memory");
|
||||
__delay(10); //10000
|
||||
|
||||
}
|
||||
|
|
@ -10,8 +10,8 @@ if os.getenv('RTT_CC'):
|
|||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = 'D:/ArdaArmTools/Sourcery_Lite'
|
||||
#EXEC_PATH = 'D:/ArdaArmTools/GNUARM_4.9_2015q1'
|
||||
EXEC_PATH = 'D:/ArdaArmTools/Sourcery_Lite/bin'
|
||||
#EXEC_PATH = 'D:/ArdaArmTools/GNUARM_4.9_2015q1/bin'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = 'C:/Keil_v5'
|
||||
|
@ -43,7 +43,6 @@ if PLATFORM == 'gcc':
|
|||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
EXEC_PATH += '/bin/'
|
||||
|
||||
DEVICE = ' -mcpu=arm926ej-s'
|
||||
CFLAGS = DEVICE
|
||||
|
|
Loading…
Reference in New Issue