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https://github.com/RT-Thread/rt-thread.git
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更新rk3568 bsp 支持PSCI、amp模式
This commit is contained in:
wangqinglin
Man, Jianting (Meco)
parent
780806feb4
commit
edaa0d9c8a
@ -25,6 +25,7 @@ config SOC_RK3568
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select RT_USING_CACHE
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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select ARCH_ARM_BOOTWITH_FLUSH_CACHE
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default y
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source "$BSP_DIR/driver/Kconfig"
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@ -51,8 +51,9 @@ menu "Hardware Drivers Config"
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bool
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default y
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config BSP_USING_GICV3
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bool
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default y
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config BSP_USING_GICV3
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bool
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default y
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select ARCH_ARM_CORTEX_A55
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endmenu
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@ -17,17 +17,29 @@
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#include <gtimer.h>
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#include <cpuport.h>
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#include <interrupt.h>
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#include <ioremap.h>
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#include <psci_api.h>
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#include <board.h>
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#include <drv_uart.h>
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#include "mm_page.h"
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#define PLATFORM_MEM_TALBE(va, size) va, ((unsigned long)va + size - 1)
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struct mem_desc platform_mem_desc[] =
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{
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{0x200000, 0x80000000, 0x200000, NORMAL_MEM},
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{UART0_MMIO_BASE, UART0_MMIO_BASE + 0x10000, UART0_MMIO_BASE, DEVICE_MEM},
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{UART1_MMIO_BASE, UART1_MMIO_BASE + 0x90000, UART1_MMIO_BASE, DEVICE_MEM},
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{GIC_PL600_DISTRIBUTOR_PPTR, GIC_PL600_DISTRIBUTOR_PPTR + 0x10000, GIC_PL600_DISTRIBUTOR_PPTR, DEVICE_MEM},
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{GIC_PL600_REDISTRIBUTOR_PPTR, GIC_PL600_REDISTRIBUTOR_PPTR + 0xc0000, GIC_PL600_REDISTRIBUTOR_PPTR, DEVICE_MEM},
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{PLATFORM_MEM_TALBE(0x20000000, 0x10000000), 0x20000000, NORMAL_MEM},
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{PLATFORM_MEM_TALBE(GRF_PMU_BASE, 0x10000), GRF_PMU_BASE, DEVICE_MEM},
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{PLATFORM_MEM_TALBE(GRF_SYS_BASE, 0x10000), GRF_SYS_BASE, DEVICE_MEM},
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{PLATFORM_MEM_TALBE(CRU_BASE, 0x10000), CRU_BASE, DEVICE_MEM},
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{PLATFORM_MEM_TALBE(UART0_MMIO_BASE, 0x10000), UART0_MMIO_BASE, DEVICE_MEM},
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{PLATFORM_MEM_TALBE(UART1_MMIO_BASE, 0x90000), UART1_MMIO_BASE, DEVICE_MEM},
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{PLATFORM_MEM_TALBE(GIC_PL600_DISTRIBUTOR_PPTR, 0x10000), GIC_PL600_DISTRIBUTOR_PPTR, DEVICE_MEM},
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{PLATFORM_MEM_TALBE(GIC_PL600_REDISTRIBUTOR_PPTR, 0xc0000), GIC_PL600_REDISTRIBUTOR_PPTR, DEVICE_MEM},
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#ifdef PKG_USING_RT_OPENAMP
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{PLATFORM_MEM_TALBE(AMP_SHARE_MEMORY_ADDRESS, AMP_SHARE_MEMORY_SIZE), AMP_SHARE_MEMORY_ADDRESS, NORMAL_MEM},
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#endif /* PKG_USING_RT_OPENAMP */
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};
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const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
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@ -39,20 +51,30 @@ void idle_wfi(void)
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void rt_hw_board_init(void)
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{
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extern void *MMUTable;
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rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
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extern unsigned long MMUTable[512];
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rt_region_t init_page_region;
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rt_hw_mmu_map_init(&rt_kernel_space, (void *) 0x20000000, 0xE0000000 - 1, MMUTable, 0);
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init_page_region.start = RT_HW_PAGE_START;
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init_page_region.end = RT_HW_PAGE_END;
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rt_page_init(init_page_region);
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rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
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/* initialize hardware interrupt */
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rt_hw_interrupt_init();
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/* initialize uart */
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rt_hw_uart_init();
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/* initialize timer for os tick */
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rt_hw_gtimer_init();
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rt_thread_idle_sethook(idle_wfi);
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// TODO porting to FDT-driven PSCI: arm_psci_init(PSCI_METHOD_SMC, RT_NULL, RT_NULL);
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psci_init();
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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/* set console device */
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@ -79,18 +101,60 @@ void rt_hw_board_init(void)
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void reboot(void)
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{
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// TODO poring to FDT to use new PSCI: arm_psci_system_reboot();
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if (psci_ops.system_reset)
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{
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psci_ops.system_reset();
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}
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else
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{
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void *cur_base = rt_ioremap((void *) CRU_BASE, 0x100);
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HWREG32(cur_base + 0x00D4) = 0xfdb9;
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HWREG32(cur_base + 0x00D8) = 0xeca8;
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}
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}
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MSH_CMD_EXPORT(reboot, reboot...);
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#ifdef RT_USING_SMP
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static void print_cpu_id(int argc, char *argv[])
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{
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rt_kprintf("rt_hw_cpu_id:%d\n", rt_hw_cpu_id());
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}
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MSH_CMD_EXPORT_ALIAS(print_cpu_id, cpuid, print_cpu_id);
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#ifdef RT_USING_AMP
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void start_cpu(int argc, char *argv[])
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{
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rt_uint32_t status;
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if (psci_ops.cpu_on)
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{
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status = psci_ops.cpu_on(0x3, (rt_uint64_t) 0x7A000000);
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rt_kprintf("arm_psci_cpu_on 0x%X\n", status);
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}
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}
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MSH_CMD_EXPORT(start_cpu, start_cpu);
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#ifdef RT_AMP_SLAVE
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void rt_hw_cpu_shutdown()
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{
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if (psci_ops.cpu_off)
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{
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psci_ops.cpu_off(0);
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}
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}
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#endif /* RT_AMP_SLAVE */
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#endif /* RT_USING_AMP */
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#if defined(RT_USING_SMP) || defined(RT_USING_AMP)
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rt_uint64_t rt_cpu_mpidr_early[] =
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{
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[0] = 0x81000000,
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[1] = 0x81000100,
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[2] = 0x81000200,
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[3] = 0x81000300,
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[0] = 0x80000000,
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[1] = 0x80000100,
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[2] = 0x80000200,
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[3] = 0x80000300,
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[RT_CPUS_NR] = 0
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};
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#endif
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#ifdef RT_USING_SMP
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void rt_hw_secondary_cpu_up(void)
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{
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int i;
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@ -98,7 +162,7 @@ void rt_hw_secondary_cpu_up(void)
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for (i = 1; i < RT_CPUS_NR; ++i)
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{
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arm_psci_cpu_on(rt_cpu_mpidr_early[i], (rt_uint64_t)secondary_cpu_start);
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arm_psci_cpu_on(rt_cpu_mpidr_early[i], (rt_uint64_t) secondary_cpu_start);
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}
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}
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@ -16,13 +16,11 @@
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extern unsigned char __bss_start;
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extern unsigned char __bss_end;
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#define RT_HW_HEAP_BEGIN (void *)&__bss_end
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#define RT_HW_HEAP_END (void *)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
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#define RT_HW_PAGE_START RT_ALIGN((unsigned long)&__bss_end, 0x1000)
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#define RT_HW_PAGE_END (RT_HW_PAGE_START + 0x100000)
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#ifndef RT_USING_SMART
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#define PV_OFFSET 0
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#define KERNEL_VADDR_START 0
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#endif
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#define RT_HW_HEAP_BEGIN (void *)(RT_HW_PAGE_END)
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#define RT_HW_HEAP_END (void *)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
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void rt_hw_board_init(void);
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@ -302,10 +302,12 @@ static void rt_hw_uart_isr(int irqno, void *param)
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int rt_hw_uart_init(void)
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{
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struct hw_uart_device *uart;
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rt_uint32_t value;
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struct hw_uart_device* uart;
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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RT_UNUSED(value);
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config.baud_rate = 1500000;
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config.baud_rate = 115200;
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#define BSP_INSTALL_UART_DEVICE(no) \
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uart = &_uart##no##_device; \
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@ -331,6 +333,12 @@ int rt_hw_uart_init(void)
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#endif
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#ifdef RT_USING_UART4
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HWREG32(CRU_BASE + 0x370) = 0xFFFF0000 | (0x600) |(HWREG32(CRU_BASE + 0x370) & 0xF0FF);
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value = HWREG32(0xFDC60000 + 0x48);
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value &= ~((7 << 8) | (7 << 4));
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value |= 0xFFFF0000 | (4 << 8) | (4 << 4);
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HWREG32(0xFDC60000 + 0x48) = value;
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HWREG32(0xFDC60000 + 0x30C) = 0xFFFF0000 | (1 << 14) | HWREG32(0xFDC60000 + 0x30C);
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BSP_INSTALL_UART_DEVICE(4);
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#endif
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@ -13,7 +13,11 @@
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#include <rtthread.h>
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/* UART */
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#define GRF_PMU_BASE 0xFDC20000
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#define GRF_SYS_BASE 0xFDC60000
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#define CRU_BASE 0xFDD20000
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/* UART */
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#define UART_MMIO_BASE 0xfe650000
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#define UART0_MMIO_BASE 0xfdd50000
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#define UART1_MMIO_BASE (UART_MMIO_BASE + 0)
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@ -13,7 +13,7 @@ OUTPUT_ARCH(aarch64)
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SECTIONS
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{
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. = 0x208000;
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. = 0x20000000;
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. = ALIGN(4096);
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.text :
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{
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@ -238,5 +238,5 @@
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#define RT_USING_UART2
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#define BSP_USING_GIC
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#define BSP_USING_GICV3
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#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
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#endif
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