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[libcpu] [cortex-a] Revert RT_SMP_AUTO_BOOT. (#7549)

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Co-authored-by: Wayne Lin <wclin@nuvoton.com>
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Wayne 2023-05-29 15:23:42 +08:00 committed by GitHub
parent 0cbb665a1c
commit ed4b4ca9e6
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1 changed files with 35 additions and 3 deletions
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38
libcpu/arm/cortex-a/start_gcc.S
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@ -157,6 +157,38 @@ after_enable_mmu:
#endif /* RT_USING_SMART */ #endif /* RT_USING_SMART */
mcr p15, 0, r1, c1, c0, 0 mcr p15, 0, r1, c1, c0, 0
#ifndef RT_USING_SMART
#ifdef RT_USING_SMP
/* Use spin-table to start secondary cores */
@ get cpu id, and subtract the offset from the stacks base address
bl rt_hw_cpu_id
mov r5, r0
cmp r5, #0 @ cpu id == 0
beq normal_setup
@ cpu id > 0, stop or wait
#ifdef RT_SMP_AUTO_BOOT
ldr r0, =secondary_cpu_entry
mov r1, #0
str r1, [r0] /* clean secondary_cpu_entry */
#endif /* RT_SMP_AUTO_BOOT */
secondary_loop:
@ cpu core 1 goes into sleep until core 0 wakeup it
wfe
#ifdef RT_SMP_AUTO_BOOT
ldr r1, =secondary_cpu_entry
ldr r0, [r1]
cmp r0, #0
blxne r0 /* if(secondary_cpu_entry) secondary_cpu_entry(); */
#endif /* RT_SMP_AUTO_BOOT */
b secondary_loop
normal_setup:
#endif /* RT_USING_SMP */
#endif /* RT_USING_SMART */
/* enable I cache + branch prediction */ /* enable I cache + branch prediction */
mrc p15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #(1<<12) orr r0, r0, #(1<<12)
@ -208,7 +240,7 @@ bss_loop:
_rtthread_startup: _rtthread_startup:
.word rtthread_startup .word rtthread_startup
.weak rt_asm_cpu_id .weak rt_asm_cpu_id
rt_asm_cpu_id: rt_asm_cpu_id:
mrc p15, 0, r0, c0, c0, 5 mrc p15, 0, r0, c0, c0, 5
and r0, r0, #0xf and r0, r0, #0xf
@ -222,7 +254,7 @@ stack_setup:
bl rt_asm_cpu_id bl rt_asm_cpu_id
mov lr, r10 mov lr, r10
add r0, r0, #1 add r0, r0, #1
#else #else
mov r0, #1 mov r0, #1
#endif #endif
@ -292,7 +324,7 @@ rt_hw_mmu_switch:
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c8, c7, 0 mcr p15, 0, r0, c8, c7, 0
mcr p15, 0, r0, c7, c5, 0 //iciallu mcr p15, 0, r0, c7, c5, 0 //iciallu
mcr p15, 0, r0, c7, c5, 6 //bpiall mcr p15, 0, r0, c7, c5, 6 //bpiall
dsb dsb
isb isb