mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2025-02-28 03:42:39 +08:00
[bsp][rtduino] 新增HMI-Board对RTduino支持、HMI-Board支持C++特性、修复一些驱动问题 (#8205)
This commit is contained in:
Yuqiang Wang
GitHub
parent
1d3fc71c79
commit
ebc9582c07
@ -26,7 +26,7 @@ if GetDepend(['BSP_USING_ONCHIP_RTC']):
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src += ['drv_rtc.c']
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if GetDepend(['BSP_USING_I2C', 'RT_USING_I2C_BITOPS']):
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if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
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if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'):
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src += ['drv_soft_i2c.c']
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if GetDepend(['BSP_USING_I2C', 'BSP_USING_HW_I2C']):
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@ -41,7 +41,7 @@ struct rt_adc_device adc1_device;
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struct ra_dev _ra_adc1_device = {.ra_adc_device_t = &adc1_device, .ra_adc_dev = &ra_adc[1]};
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#endif
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static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
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static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
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{
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RT_ASSERT(device != RT_NULL);
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struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
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@ -78,7 +78,7 @@ rt_err_t ra_adc_close(struct rt_adc_device *device)
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return RT_EOK;
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}
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static rt_err_t ra_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
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static rt_err_t ra_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
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{
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RT_ASSERT(device != RT_NULL);
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struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
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@ -21,7 +21,7 @@
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#define DBG_LVL DBG_INFO
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#endif /* DRV_DEBUG */
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#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1)
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#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2)
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#error "Please define at least one BSP_USING_I2Cx"
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/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
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#endif
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@ -34,6 +34,9 @@ static const struct ra_soft_i2c_config soft_i2c_config[] =
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#ifdef BSP_USING_I2C1
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I2C1_BUS_CONFIG,
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#endif
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#ifdef BSP_USING_I2C2
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I2C2_BUS_CONFIG,
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#endif
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};
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static struct ra_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
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@ -30,6 +30,15 @@ struct ra_i2c
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struct rt_i2c_bus_device i2c2_bus;
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};
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#ifdef BSP_USING_I2C0
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#define I2C0_BUS_CONFIG \
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{ \
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.scl = BSP_I2C0_SCL_PIN, \
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.sda = BSP_I2C0_SDA_PIN, \
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.bus_name = "i2c0", \
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}
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#endif
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#ifdef BSP_USING_I2C1
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#define I2C1_BUS_CONFIG \
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{ \
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@ -1,19 +1,24 @@
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#Tue Apr 18 17:25:03 CST 2023
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#Tue Oct 31 10:46:22 CST 2023
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/libraries=
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com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/all=3427620923,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|143358381,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|2743353138,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/all=143358381,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|3427620923,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|2743353138,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_adc\#\#\#\#3.5.0/libraries=
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com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.552817864=false
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1728953905,ra/fsp/inc/fsp_features.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2208590403,ra/fsp/inc/instances/r_ioport.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3297195641,ra/fsp/inc/fsp_version.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2425160085,ra/fsp/inc/api/bsp_api.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|546480625,ra/fsp/inc/fsp_common_api.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=546480625,ra/fsp/inc/fsp_common_api.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|2425160085,ra/fsp/inc/api/bsp_api.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3297195641,ra/fsp/inc/fsp_version.h|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|2208590403,ra/fsp/inc/instances/r_ioport.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1728953905,ra/fsp/inc/fsp_features.h|1939984091,ra/fsp/inc/api/r_ioport_api.h
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFB\#\#3.5.0/libraries=
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#3.5.0/libraries=
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com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
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com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1441545198,ra/arm/CMSIS_5/LICENSE.txt|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#3.5.0/all=1958999550,ra/fsp/src/r_gpt/r_gpt.c|232390045,ra/fsp/inc/api/r_timer_api.h|2886639616,ra/fsp/inc/instances/r_gpt.h
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com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1441545198,ra/arm/CMSIS_5/LICENSE.txt|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
|
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/all=
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=2208590403,ra/fsp/inc/instances/r_ioport.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c|1939984091,ra/fsp/inc/api/r_ioport_api.h
|
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_adc\#\#\#\#3.5.0/all=4250819551,ra/fsp/inc/instances/r_adc.h|1515334001,ra/fsp/inc/api/r_elc_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|1675086128,ra/fsp/inc/api/r_adc_api.h|377989633,ra/fsp/src/r_adc/r_adc.c
|
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=3254285722,ra/fsp/src/r_ioport/r_ioport.c|1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h
|
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3916852077,ra/fsp/inc/api/r_uart_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1610456547,ra/fsp/inc/api/r_transfer_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h
|
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|3916852077,ra/fsp/inc/api/r_uart_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c
|
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com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.606654632=false
|
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com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/libraries=
|
||||
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=
|
||||
|
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@ -9,6 +9,24 @@ menu "Hardware Drivers Config"
|
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|
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menu "Onboard Peripheral Drivers"
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|
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config BSP_USING_ARDUINO
|
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bool "Compatible with Arduino Ecosystem (RTduino)"
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select PKG_USING_RTDUINO
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select BSP_USING_UART4
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select BSP_USING_GPIO
|
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select BSP_USING_TIM
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select BSP_USING_TIM2
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select BSP_USING_ADC
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select BSP_USING_ADC0
|
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select BSP_USING_PWM
|
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select BSP_USING_PWM2
|
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select BSP_USING_PWM2_CH2
|
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select BSP_USING_I2C
|
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select BSP_USING_I2C2
|
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imply RTDUINO_USING_SERVO
|
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imply RTDUINO_USING_WIRE
|
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default n
|
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|
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endmenu
|
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|
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menu "On-chip Peripheral Drivers"
|
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@ -445,6 +463,65 @@ menu "Hardware Drivers Config"
|
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default n
|
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endif
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|
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menuconfig BSP_USING_I2C
|
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bool "Enable software I2C bus"
|
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select RT_USING_I2C
|
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select RT_USING_I2C_BITOPS
|
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select RT_USING_PIN
|
||||
default n
|
||||
|
||||
if BSP_USING_I2C
|
||||
config BSP_USING_I2C
|
||||
menuconfig BSP_USING_I2C0
|
||||
bool "Enable I2C0 Bus (software simulation)"
|
||||
default n
|
||||
if BSP_USING_I2C0
|
||||
comment "Please select your i2c analog pin, e.g. 'P512': BSP_IO_PORT_05_PIN_12"
|
||||
config BSP_I2C0_SCL_PIN
|
||||
string "i2c0 scl pin number (Pxxx)"
|
||||
default "pxxx"
|
||||
config BSP_I2C0_SDA_PIN
|
||||
string "i2c0 sda pin number (Pxxx)"
|
||||
default "pxxx"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C1
|
||||
bool "Enable I2C1 Bus (software simulation)"
|
||||
default n
|
||||
if BSP_USING_I2C1
|
||||
comment "Please select your i2c analog pin, e.g. 'P512': BSP_IO_PORT_05_PIN_12"
|
||||
config BSP_I2C1_SCL_PIN
|
||||
string "i2c1 scl pin number (Pxxx)"
|
||||
default "pxxx"
|
||||
config BSP_I2C1_SDA_PIN
|
||||
string "i2c1 sda pin number (Pxxx)"
|
||||
default "pxxx"
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C2
|
||||
bool "Enable I2C2 Bus (software simulation)"
|
||||
default n
|
||||
if BSP_USING_I2C2
|
||||
comment "Please select your i2c analog pin, e.g. 'P512': BSP_IO_PORT_05_PIN_12"
|
||||
config BSP_I2C2_SCL_PIN
|
||||
string "i2c2 scl pin number (P512)"
|
||||
default "BSP_IO_PORT_05_PIN_12"
|
||||
config BSP_I2C2_SDA_PIN
|
||||
string "i2c2 sda pin number (P511)"
|
||||
default "BSP_IO_PORT_05_PIN_11"
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
select RT_USING_ADC
|
||||
if BSP_USING_ADC
|
||||
config BSP_USING_ADC0
|
||||
bool "Enable ADC0"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_FS
|
||||
bool "Enable filesystem"
|
||||
default n
|
||||
@ -484,8 +561,19 @@ menu "Hardware Drivers Config"
|
||||
config BSP_USING_PWM12
|
||||
bool "Enable GPT12 (16-Bits) output PWM"
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_PWM2
|
||||
bool "Enable timer2 output PWM"
|
||||
default n
|
||||
if BSP_USING_PWM2
|
||||
config BSP_USING_PWM2_CH2
|
||||
bool "Enable PWM2 channel2"
|
||||
default n
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
|
||||
menuconfig BSP_USING_CAN
|
||||
bool "Enable CAN"
|
||||
default n
|
||||
|
||||
19
bsp/renesas/ra6m3-hmi-board/board/rtduino/SConscript
Normal file
19
bsp/renesas/ra6m3-hmi-board/board/rtduino/SConscript
Normal file
@ -0,0 +1,19 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = []
|
||||
group = []
|
||||
CPPPATH = [cwd]
|
||||
|
||||
|
||||
if GetDepend(['PKG_USING_RTDUINO']) and not GetDepend(['RTDUINO_NO_SETUP_LOOP']):
|
||||
src += Glob('arduino_main.cpp')
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
group = group + DefineGroup('rtduino-port', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = CPPPATH)
|
||||
Return('group')
|
||||
24
bsp/renesas/ra6m3-hmi-board/board/rtduino/arduino_main.cpp
Normal file
24
bsp/renesas/ra6m3-hmi-board/board/rtduino/arduino_main.cpp
Normal file
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-10-28 Wangyuqiang first version
|
||||
*/
|
||||
|
||||
#include <Arduino.h>
|
||||
|
||||
void setup(void)
|
||||
{
|
||||
/* put your setup code here, to run once: */
|
||||
Serial.begin();
|
||||
}
|
||||
|
||||
void loop(void)
|
||||
{
|
||||
/* put your main code here, to run repeatedly: */
|
||||
Serial.println("Hello Arduino!");
|
||||
delay(800);
|
||||
}
|
||||
@ -0,0 +1,50 @@
|
||||
# ra6m3-hmi-board Arduino Eco-compatibility Guide
|
||||
|
||||
**[中文](README_zh.md)** | **English**
|
||||
|
||||
## 1 RTduino - Arduino Eco-compatibility Layer for RT-Thread
|
||||
|
||||
The ra6m3-hmi-board development board has been fully adapted to the [RTduino software package](https://github.com/RTduino/RTduino), which is an Arduino eco-compatibility layer for RT-Thread. Users can program this BSP in accordance with Arduino coding conventions and can utilize a wide range of libraries from the Arduino community, significantly enhancing the RT-Thread ecosystem. For more information, please refer to the [RTduino software package documentation](https://github.com/RTduino/RTduino).
|
||||
|
||||
### 1.1 Enabling the Arduino Eco-compatibility Layer for this BSP
|
||||
|
||||
In the Env tool, enter the "menuconfig" command, or in the RT-Thread Studio IDE, select "RT-Thread Settings":
|
||||
|
||||
```Kconfig
|
||||
Hardware Drivers Config --->
|
||||
Onboard Peripheral Drivers --->
|
||||
[*] Compatible with Arduino Ecosystem (RTduino)
|
||||
```
|
||||
|
||||
## 2 Arduino Pin Layout
|
||||
|
||||
For more information about pin layout, please see [pins_arduino.c](pins_arduino.c) and [pins_arduino.h](pins_arduino.h).
|
||||
|
||||
|
||||
|
||||
| Arduino Pin Number | STM32 Pin Number | 5V Tolerance | Remarks |
|
||||
| ------------------- | --------- | ---- | ------------------------------------------------------------------------- |
|
||||
| 0 (D0) | P206 | Yes | Serial4-RX, managed by RT-Thread's UART device framework uart4 by default |
|
||||
| 1 (D1) | P205 | Yes | Serial4-TX, managed by RT-Thread's UART device framework uart4 by default |
|
||||
| 2 (D2) | P008 | Yes | |
|
||||
| 3 (D3) | P506 | Yes | |
|
||||
| 4 (D4) | P603 | Yes | |
|
||||
| 5 (D5) | P604 | Yes | |
|
||||
| 6 (D6) | P605 | Yes | |
|
||||
| 7 (D7) | P208 | Yes | |
|
||||
| 8 (D8) | P207 | Yes | |
|
||||
| 9 (D9) | P009 | Yes | |
|
||||
| 10 (D10) | P712 | Yes | PWM2-CH2, managed by RT-Thread's PWM device framework pwm2's channel2 by default |
|
||||
| 11 (D11) | P512 | Yes | I2C2-SCL, managed by RT-Thread's I2C device framework i2c2 by default |
|
||||
| 12 (D12) | P511 | Yes | I2C2-SDA, managed by RT-Thread's I2C device framework i2c2 by default |
|
||||
| 13 (D13) | P204 | Yes | |
|
||||
| 14 (D14) | P203 | Yes | |
|
||||
| 15 (D15) | P202 | Yes | |
|
||||
| 16 (A0) | P000 | Yes | ADC1-CH0-EXTVOL (external voltage), managed by RT-Thread's ADC device framework adc0's channel0 by default |
|
||||
| 17 (A1) | P001 | Yes | ADC1-CH1-EXTVOL (external voltage), managed by RT-Thread's ADC device framework adc0's channel1 by default |
|
||||
| 18 (A2) | P002 | Yes | ADC1-CH2-EXTVOL (external voltage), managed by RT-Thread's ADC device framework adc0's channel2 by default |
|
||||
| 19 (A3) | P003 | Yes | ADC1-CH7-EXTVOL (external voltage), managed by RT-Thread's ADC device framework adc0's channel7 by default |
|
||||
| 20 (A4) | P508 | Yes | ADC1-CH19-EXTVOL (external voltage), managed by RT-Thread's ADC device framework adc0's channel20 by default |
|
||||
| 21 (A5) | P014 | Yes | ADC1-CH5-EXTVOL (external voltage), managed by RT-Thread's ADC device framework adc0's channel5 by default |
|
||||
|
||||
> Note: RTduino does not currently support MDK. It is recommended to use the GNU GCC toolchain for compilation.
|
||||
@ -0,0 +1,50 @@
|
||||
# ra6m3-hmi-board 开发板的Arduino生态兼容说明
|
||||
|
||||
**[English](README.md)** | **中文**
|
||||
|
||||
## 1 RTduino - RT-Thread的Arduino生态兼容层
|
||||
|
||||
ra6m3-hmi-board 开发板已经完整适配了[RTduino软件包](https://github.com/RTduino/RTduino)，即RT-Thread的Arduino生态兼容层。用户可以按照Arduino的编程习惯来操作该BSP，并且可以使用大量Arduino社区丰富的库，是对RT-Thread生态的极大增强。更多信息，请参见[RTduino软件包说明文档](https://github.com/RTduino/RTduino)。
|
||||
|
||||
### 1.1 如何开启针对本BSP的Arduino生态兼容层
|
||||
|
||||
Env 工具下敲入 menuconfig 命令，或者 RT-Thread Studio IDE 下选择 RT-Thread Settings：
|
||||
|
||||
```Kconfig
|
||||
Hardware Drivers Config --->
|
||||
Onboard Peripheral Drivers --->
|
||||
[*] Compatible with Arduino Ecosystem (RTduino)
|
||||
```
|
||||
|
||||
## 2 Arduino引脚排布
|
||||
|
||||
更多引脚布局相关信息参见 [pins_arduino.c](pins_arduino.c) 和 [pins_arduino.h](pins_arduino.h)。
|
||||
|
||||
|
||||
|
||||
| Arduino引脚编号 | STM32引脚编号 | 5V容忍 | 备注 |
|
||||
| ------------------- | --------- | ---- | ------------------------------------------------------------------------- |
|
||||
| 0 (D0) | P206 | 是 | Serial4-RX,默认被RT-Thread的UART设备框架uart4接管 |
|
||||
| 1 (D1) | P205 | 是 | Serial4-TX,默认被RT-Thread的UART设备框架uart4接管 |
|
||||
| 2 (D2) | P008 | 是 | |
|
||||
| 3 (D3) | P506 | 是 | |
|
||||
| 4 (D4) | P603 | 是 | |
|
||||
| 5 (D5) | P604 | 是 | |
|
||||
| 6 (D6) | P605 | 是 | |
|
||||
| 7 (D7) | P208 | 是 | |
|
||||
| 8 (D8) | P207 | 是 | |
|
||||
| 9 (D9) | P009 | 是 | |
|
||||
| 10 (D10) | P712 | 是 | PWM2-CH2,默认被RT-Thread的PWM设备框架pwm2的channel2接管 |
|
||||
| 11 (D11) | P512 | 是 | I2C2-SCL,默认被RT-Thread的I2C设备框架i2c2接管 |
|
||||
| 12 (D12) | P511 | 是 | I2C2-SDA,默认被RT-Thread的I2C设备框架i2c2接管 |
|
||||
| 13 (D13) | P204 | 是 | |
|
||||
| 14 (D14) | P203 | 是 | |
|
||||
| 15 (D15) | P202 | 是 | |
|
||||
| 16 (A0) | P000 | 是 | ADC1-CH0-EXTVOL(外部电压),默认被RT-Thread的ADC设备框架adc0的channel0接管 |
|
||||
| 17 (A1) | P001 | 是 | ADC1-CH1-EXTVOL(外部电压),默认被RT-Thread的ADC设备框架adc0的channel1接管 |
|
||||
| 18 (A2) | P002 | 是 | ADC1-CH2-EXTVOL(外部电压),默认被RT-Thread的ADC设备框架adc0的channel2接管 |
|
||||
| 19 (A3) | P003 | 是 | ADC1-CH7-EXTVOL(外部电压),默认被RT-Thread的ADC设备框架adc0的channel7接管 |
|
||||
| 20 (A4) | P508 | 是 | ADC1-CH19-EXTVOL(外部电压),默认被RT-Thread的ADC设备框架adc0的channel20接管 |
|
||||
| 21 (A5) | P014 | 是 | ADC1-CH5-EXTVOL(外部电压),默认被RT-Thread的ADC设备框架adc0的channel5接管 |
|
||||
|
||||
> 注意：RTduino暂时不对MDK支持，建议使用GNU GCC工具链编译
|
||||
@ -0,0 +1,16 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp')
|
||||
group = []
|
||||
inc = [cwd]
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
group = group + DefineGroup('RTduino', src, depend = ['PKG_USING_RTDUINO'], CPPPATH = inc)
|
||||
|
||||
Return('group')
|
||||
@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-10-28 Wangyuqiang first version
|
||||
*/
|
||||
|
||||
#include <Arduino.h>
|
||||
#include "pins_arduino.h"
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "hal_data.h"
|
||||
#include <rtdevice.h>
|
||||
|
||||
/*
|
||||
* {Arduino Pin, RT-Thread Pin [, Device Name, Channel]}
|
||||
* [] means optional
|
||||
* Digital pins must NOT give the device name and channel.
|
||||
* Analog pins MUST give the device name and channel(ADC, PWM or DAC).
|
||||
* Arduino Pin must keep in sequence.
|
||||
*/
|
||||
const pin_map_t pin_map_table[]=
|
||||
{
|
||||
{D0, BSP_IO_PORT_02_PIN_06, "uart4"}, /* Serial4-RX */
|
||||
{D1, BSP_IO_PORT_02_PIN_05, "uart4"}, /* Serial4-TX */
|
||||
{D2, BSP_IO_PORT_00_PIN_08},
|
||||
{D3, BSP_IO_PORT_05_PIN_06},
|
||||
{D4, BSP_IO_PORT_06_PIN_03},
|
||||
{D5, BSP_IO_PORT_06_PIN_04},
|
||||
{D6, BSP_IO_PORT_06_PIN_05},
|
||||
{D7, BSP_IO_PORT_02_PIN_08},
|
||||
{D8, BSP_IO_PORT_02_PIN_07},
|
||||
{D9, BSP_IO_PORT_00_PIN_09}, /* SPI-SS */
|
||||
{D10, BSP_IO_PORT_07_PIN_12, "pwm2", 2}, /* PWM */
|
||||
{D11, BSP_IO_PORT_05_PIN_12, "i2c2"}, /* I2C-SCL (Wire) */
|
||||
{D12, BSP_IO_PORT_05_PIN_11, "i2c2"}, /* I2C-SDA (Wire) */
|
||||
{D13, BSP_IO_PORT_02_PIN_04},
|
||||
{D14, BSP_IO_PORT_02_PIN_03},
|
||||
{D15, BSP_IO_PORT_02_PIN_02},
|
||||
{A0, BSP_IO_PORT_00_PIN_00, "adc0", 0}, /* ADC */
|
||||
{A1, BSP_IO_PORT_00_PIN_01, "adc0", 1}, /* ADC */
|
||||
{A2, BSP_IO_PORT_00_PIN_02, "adc0", 2}, /* ADC */
|
||||
{A3, BSP_IO_PORT_00_PIN_03, "adc0", 7}, /* ADC */
|
||||
{A4, BSP_IO_PORT_05_PIN_08, "adc0", 20}, /* ADC */
|
||||
{A5, BSP_IO_PORT_00_PIN_14, "adc0", 5} /* ADC */
|
||||
};
|
||||
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-10-28 Wangyuqiang first version
|
||||
*/
|
||||
|
||||
#ifndef Pins_Arduino_h
|
||||
#define Pins_Arduino_h
|
||||
|
||||
/* pins alias. Must keep in sequence */
|
||||
#define D0 (0)
|
||||
#define D1 (1)
|
||||
#define D2 (2)
|
||||
#define D3 (3)
|
||||
#define D4 (4)
|
||||
#define D5 (5)
|
||||
#define D6 (6)
|
||||
#define D7 (7)
|
||||
#define D8 (8)
|
||||
#define D9 (9)
|
||||
#define D10 (10)
|
||||
#define D11 (11)
|
||||
#define D12 (12)
|
||||
#define D13 (13)
|
||||
#define D14 (14)
|
||||
#define D15 (15)
|
||||
#define A0 (16)
|
||||
#define A1 (17)
|
||||
#define A2 (18)
|
||||
#define A3 (19)
|
||||
#define A4 (20)
|
||||
#define A5 (21)
|
||||
|
||||
#define RTDUINO_PIN_MAX_LIMIT A5 /* pin number max limit check */
|
||||
|
||||
#define F_CPU 120000000L /* CPU:120MHz */
|
||||
|
||||
/* i2c2 : PD10-SDA PD10-SCL */
|
||||
#define RTDUINO_DEFAULT_IIC_BUS_NAME "i2c2"
|
||||
|
||||
/* Serial4(uart4) : P205-TX P206-RX */
|
||||
#define RTDUINO_SERIAL2_DEVICE_NAME "uart4"
|
||||
|
||||
#define RTDUINO_DEFAULT_HWTIMER_DEVICE_NAME "timer2"
|
||||
|
||||
#endif /* Pins_Arduino_h */
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 3.3 MiB |
@ -57,65 +57,57 @@
|
||||
<file category="source" name="ra/board/ra6m3/board_leds.c"/>
|
||||
<file category="header" name="ra/board/ra6m3/board_leds.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_adc_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_elc_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_timer_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/instances/r_adc.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/instances/r_glcdc.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/instances/r_gpt.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
|
||||
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
|
||||
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
|
||||
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
|
||||
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
|
||||
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h" path=""/>
|
||||
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h" path=""/>
|
||||
<file category="source" name="ra/fsp/src/r_adc/r_adc.c"/>
|
||||
<file category="source" name="ra/fsp/src/r_gpt/r_gpt.c"/>
|
||||
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
|
||||
<file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
|
||||
<file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
|
||||
<file category="other" name="ra/fsp/src/r_sci_uart/r_sci_uart.o"/>
|
||||
<file category="other" name="ra/SConscript"/>
|
||||
</files>
|
||||
</component>
|
||||
@ -129,6 +121,8 @@
|
||||
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/r_adc_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/r_gpt_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
|
||||
<file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
|
||||
<file category="other" name="ra_cfg/SConscript"/>
|
||||
|
||||
@ -165,6 +165,14 @@
|
||||
<description>SCI UART</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_adc" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>A/D Converter</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_gpt" variant="" vendor="Renesas" version="3.5.0">
|
||||
<description>General PWM Timer</description>
|
||||
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||
</component>
|
||||
</raComponentSelection>
|
||||
<raElcConfiguration/>
|
||||
<raIcuConfiguration/>
|
||||
@ -203,33 +211,185 @@
|
||||
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
|
||||
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
|
||||
</module>
|
||||
<module id="module.driver.adc_on_adc.1357067907">
|
||||
<property id="module.driver.adc.name" value="g_adc0"/>
|
||||
<property id="module.driver.adc.unit" value="0"/>
|
||||
<property id="module.driver.adc.resolution" value="module.driver.adc.resolution.resolution_12_bit"/>
|
||||
<property id="module.driver.adc.alignment" value="module.driver.adc.alignment.alignment_right"/>
|
||||
<property id="module.driver.adc.clearing" value="module.driver.adc.clearing.clear_after_read_on"/>
|
||||
<property id="module.driver.adc.mode" value="module.driver.adc.mode.mode_continuous_scan"/>
|
||||
<property id="module.driver.adc.mode.dt" value="module.driver.adc.mode.dt.disabled"/>
|
||||
<property id="module.driver.adc.scan_mask" value="module.driver.adc.scan_mask.channel_0,module.driver.adc.scan_mask.channel_1,module.driver.adc.scan_mask.channel_2,module.driver.adc.scan_mask.channel_3,module.driver.adc.scan_mask.channel_5,module.driver.adc.scan_mask.channel_7,module.driver.adc.scan_mask.channel_20"/>
|
||||
<property id="module.driver.adc.scan_mask_group_b" value=""/>
|
||||
<property id="module.driver.adc.trigger" value="enum.driver.adc.trigger.trigger_software"/>
|
||||
<property id="module.driver.adc.trigger_group_b" value="_disabled"/>
|
||||
<property id="module.driver.adc.priority_group_a" value="module.driver.adc.priority_group_a.group_a_priority_off"/>
|
||||
<property id="module.driver.adc.add_average_count" value="module.driver.adc.add_average_count.add_off"/>
|
||||
<property id="module.driver.adc.adc_vref_control" value="module.driver.adc.adc_vref_control.vrefh"/>
|
||||
<property id="module.driver.adc.add_mask" value=""/>
|
||||
<property id="module.driver.adc.sample_hold_mask" value=""/>
|
||||
<property id="module.driver.adc.sample_hold_states" value="24"/>
|
||||
<property id="module.driver.adc.compare.window_mode" value="module.driver.adc.compare.window_mode.disabled"/>
|
||||
<property id="module.driver.adc.compare.event_mode" value="module.driver.adc.compare.event_mode.or"/>
|
||||
<property id="module.driver.adc.compare.window_a.enable" value="module.driver.adc.compare.window_a.enable.disabled"/>
|
||||
<property id="module.driver.adc.compare.window_a.channels" value=""/>
|
||||
<property id="module.driver.adc.compare.window_a.channel_mode" value=""/>
|
||||
<property id="module.driver.adc.compare.window_a.ref_lower" value="0"/>
|
||||
<property id="module.driver.adc.compare.window_a.ref_upper" value="0"/>
|
||||
<property id="module.driver.adc.compare.window_b.enable" value="module.driver.adc.compare.window_b.enable.disabled"/>
|
||||
<property id="module.driver.adc.compare.window_b.channel" value="module.driver.adc.compare.window_b.channel.channel_0"/>
|
||||
<property id="module.driver.adc.compare.window_b.mode" value="module.driver.adc.compare.window_b.mode"/>
|
||||
<property id="module.driver.adc.compare.window_b.ref_lower" value="0"/>
|
||||
<property id="module.driver.adc.compare.window_b.ref_upper" value="0"/>
|
||||
<property id="module.driver.adc.p_callback" value="NULL"/>
|
||||
<property id="module.driver.adc.scan_end_ipl" value="_disabled"/>
|
||||
<property id="module.driver.adc.scan_end_b_ipl" value="_disabled"/>
|
||||
<property id="module.driver.adc.window_a_ipl" value="_disabled"/>
|
||||
<property id="module.driver.adc.window_b_ipl" value="_disabled"/>
|
||||
<property id="module.driver.adc.adbuf" value="module.driver.adc.adbuf.disabled"/>
|
||||
</module>
|
||||
<module id="module.driver.uart_on_sci_uart.606654632">
|
||||
<property id="module.driver.uart.name" value="g_uart4"/>
|
||||
<property id="module.driver.uart.channel" value="4"/>
|
||||
<property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
|
||||
<property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
|
||||
<property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
|
||||
<property id="module.driver.uart.baud" value="115200"/>
|
||||
<property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
|
||||
<property id="module.driver.uart.baudrate_max_err" value="5"/>
|
||||
<property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
|
||||
<property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
|
||||
<property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
|
||||
<property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
|
||||
<property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
|
||||
<property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
|
||||
<property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
|
||||
<property id="module.driver.uart.callback" value="user_uart4_callback"/>
|
||||
<property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority12"/>
|
||||
<property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority12"/>
|
||||
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
|
||||
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
|
||||
</module>
|
||||
<module id="module.driver.timer_on_gpt.1304889876">
|
||||
<property id="module.driver.timer.name" value="g_timer2"/>
|
||||
<property id="module.driver.timer.channel" value="2"/>
|
||||
<property id="module.driver.timer.mode" value="module.driver.timer.mode.mode_pwm"/>
|
||||
<property id="module.driver.timer.period" value="0x100000000"/>
|
||||
<property id="module.driver.timer.unit" value="module.driver.timer.unit.unit_period_raw_counts"/>
|
||||
<property id="module.driver.timer.gtior.gtioa.initial_output_level" value="module.driver.timer.gtior.gtioa.initial_output_level.low"/>
|
||||
<property id="module.driver.timer.gtior.gtioa.cycle_end_output_level" value="module.driver.timer.gtior.gtioa.cycle_end_output_level.retain"/>
|
||||
<property id="module.driver.timer.gtior.gtioa.compare_match_output_level" value="module.driver.timer.gtior.gtioa.compare_match_output_level.retain"/>
|
||||
<property id="module.driver.timer.gtior.gtioa.count_stop_retain" value="module.driver.timer.gtior.gtioa.count_stop_retain.disabled"/>
|
||||
<property id="module.driver.timer.gtior.gtiob.initial_output_level" value="module.driver.timer.gtior.gtiob.initial_output_level.low"/>
|
||||
<property id="module.driver.timer.gtior.gtiob.cycle_end_output_level" value="module.driver.timer.gtior.gtiob.cycle_end_output_level.retain"/>
|
||||
<property id="module.driver.timer.gtior.gtiob.compare_match_output_level" value="module.driver.timer.gtior.gtiob.compare_match_output_level.retain"/>
|
||||
<property id="module.driver.timer.gtior.gtiob.count_stop_retain" value="module.driver.timer.gtior.gtiob.count_stop_retain.disabled"/>
|
||||
<property id="module.driver.timer.gtior.custom_waveform_enable" value="module.driver.timer.gtior.custom_waveform_enable.disabled"/>
|
||||
<property id="module.driver.timer.duty_cycle" value="50"/>
|
||||
<property id="module.driver.timer.gtioca_output_enabled" value="module.driver.timer.gtioca_output_enabled.false"/>
|
||||
<property id="module.driver.timer.gtioca_stop_level" value="module.driver.timer.gtioca_stop_level.pin_level_low"/>
|
||||
<property id="module.driver.timer.gtiocb_output_enabled" value="module.driver.timer.gtiocb_output_enabled.true"/>
|
||||
<property id="module.driver.timer.gtiocb_stop_level" value="module.driver.timer.gtiocb_stop_level.pin_level_low"/>
|
||||
<property id="module.driver.timer.count_up_source" value=""/>
|
||||
<property id="module.driver.timer.count_down_source" value=""/>
|
||||
<property id="module.driver.timer.start_source" value=""/>
|
||||
<property id="module.driver.timer.stop_source" value=""/>
|
||||
<property id="module.driver.timer.clear_source" value=""/>
|
||||
<property id="module.driver.timer.capture_a_source" value=""/>
|
||||
<property id="module.driver.timer.capture_b_source" value=""/>
|
||||
<property id="module.driver.timer.gtioca_filter" value="module.driver.timer.gtioc_filter.gtioc_filter_none"/>
|
||||
<property id="module.driver.timer.gtiocb_filter" value="module.driver.timer.gtioc_filter.gtioc_filter_none"/>
|
||||
<property id="module.driver.timer.p_callback" value="NULL"/>
|
||||
<property id="module.driver.timer.ipl" value="_disabled"/>
|
||||
<property id="module.driver.timer.capture_a_ipl" value="_disabled"/>
|
||||
<property id="module.driver.timer.capture_b_ipl" value="_disabled"/>
|
||||
<property id="module.driver.timer.trough_ipl" value="_disabled"/>
|
||||
<property id="module.driver.timer.extra" value="module.driver.timer.extra.disabled"/>
|
||||
<property id="module.driver.timer.poeg_link" value="module.driver.timer.poeg_link.poeg_link_poeg0"/>
|
||||
<property id="module.driver.timer.output_disable" value=""/>
|
||||
<property id="module.driver.timer.adc_trigger" value=""/>
|
||||
<property id="module.driver.timer.dead_time_count_up" value="0"/>
|
||||
<property id="module.driver.timer.dead_time_count_down" value="0"/>
|
||||
<property id="module.driver.timer.adc_a_compare_match" value="0"/>
|
||||
<property id="module.driver.timer.adc_b_compare_match" value="0"/>
|
||||
<property id="module.driver.timer.interrupt_skip.source" value="module.driver.timer.interrupt_skip.source.none"/>
|
||||
<property id="module.driver.timer.interrupt_skip.count" value="module.driver.timer.interrupt_skip.count.count_0"/>
|
||||
<property id="module.driver.timer.interrupt_skip.adc" value="module.driver.timer.interrupt_skip.adc.none"/>
|
||||
<property id="module.driver.timer.gtioca_disable_setting" value="module.driver.timer.gtioca_disable_setting.gtioc_disable_prohibited"/>
|
||||
<property id="module.driver.timer.gtiocb_disable_setting" value="module.driver.timer.gtiocb_disable_setting.gtioc_disable_prohibited"/>
|
||||
</module>
|
||||
<context id="_hal.0">
|
||||
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||
<stack module="module.driver.uart_on_sci_uart.552817864"/>
|
||||
<stack module="module.driver.adc_on_adc.1357067907"/>
|
||||
<stack module="module.driver.uart_on_sci_uart.606654632"/>
|
||||
<stack module="module.driver.timer_on_gpt.1304889876"/>
|
||||
</context>
|
||||
<config id="config.driver.ioport">
|
||||
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||
</config>
|
||||
<config id="config.driver.adc">
|
||||
<property id="config.driver.adc.param_checking_enable" value="config.driver.adc.param_checking_enable.bsp"/>
|
||||
</config>
|
||||
<config id="config.driver.sci_uart">
|
||||
<property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
|
||||
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
|
||||
<property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
|
||||
<property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
|
||||
</config>
|
||||
<config id="config.driver.gpt">
|
||||
<property id="config.driver.gpt.param_checking_enable" value="config.driver.gpt.param_checking_enable.bsp"/>
|
||||
<property id="config.driver.gpt.output_support_enable" value="config.driver.gpt.output_support_enable.enabled"/>
|
||||
<property id="config.driver.gpt.write_protect_enable" value="config.driver.gpt.write_protect_enable.disabled"/>
|
||||
<property id="config.driver.gpt.gpt_core_clock" value="module.driver.timer.gpt_core_clock.pclk"/>
|
||||
</config>
|
||||
</raModuleConfiguration>
|
||||
<raPinConfiguration>
|
||||
<pincfg active="true" name="R7FA6M3AH3CFB.pincfg" selected="true" symbol="g_bsp_pin_cfg">
|
||||
<configSetting altId="adc0.an00.p000" configurationId="adc0.an00"/>
|
||||
<configSetting altId="adc0.an01.p001" configurationId="adc0.an01"/>
|
||||
<configSetting altId="adc0.an02.p002" configurationId="adc0.an02"/>
|
||||
<configSetting altId="adc0.an03.p008" configurationId="adc0.an03"/>
|
||||
<configSetting altId="adc0.an05.p014" configurationId="adc0.an05"/>
|
||||
<configSetting altId="adc0.an07.p003" configurationId="adc0.an07"/>
|
||||
<configSetting altId="adc0.an20.p508" configurationId="adc0.an20"/>
|
||||
<configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
|
||||
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||
<configSetting altId="gpt2.gtiocb.p712" configurationId="gpt2.gtiocb"/>
|
||||
<configSetting altId="gpt2.mode.gtiocaorgtiocb.free" configurationId="gpt2.mode"/>
|
||||
<configSetting altId="p000.adc0.an00" configurationId="p000"/>
|
||||
<configSetting altId="p000.gpio_mode.gpio_mode_an" configurationId="p000.gpio_mode"/>
|
||||
<configSetting altId="p001.adc0.an01" configurationId="p001"/>
|
||||
<configSetting altId="p001.gpio_mode.gpio_mode_an" configurationId="p001.gpio_mode"/>
|
||||
<configSetting altId="p002.adc0.an02" configurationId="p002"/>
|
||||
<configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/>
|
||||
<configSetting altId="p003.adc0.an07" configurationId="p003"/>
|
||||
<configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
|
||||
<configSetting altId="p008.adc0.an03" configurationId="p008"/>
|
||||
<configSetting altId="p008.gpio_mode.gpio_mode_an" configurationId="p008.gpio_mode"/>
|
||||
<configSetting altId="p014.adc0.an05" configurationId="p014"/>
|
||||
<configSetting altId="p014.gpio_mode.gpio_mode_an" configurationId="p014.gpio_mode"/>
|
||||
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||
<configSetting altId="p109.sci9.txd" configurationId="p109"/>
|
||||
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
|
||||
<configSetting altId="p110.sci9.rxd" configurationId="p110"/>
|
||||
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
|
||||
<configSetting altId="p205.sci4.txd" configurationId="p205"/>
|
||||
<configSetting altId="p205.gpio_mode.gpio_mode_peripheral" configurationId="p205.gpio_mode"/>
|
||||
<configSetting altId="p206.sci4.rxd" configurationId="p206"/>
|
||||
<configSetting altId="p206.gpio_mode.gpio_mode_peripheral" configurationId="p206.gpio_mode"/>
|
||||
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||
<configSetting altId="p508.adc0.an20" configurationId="p508"/>
|
||||
<configSetting altId="p508.gpio_mode.gpio_mode_an" configurationId="p508.gpio_mode"/>
|
||||
<configSetting altId="p712.gpt2.gtiocb" configurationId="p712"/>
|
||||
<configSetting altId="p712.gpio_mode.gpio_mode_peripheral" configurationId="p712.gpio_mode"/>
|
||||
<configSetting altId="sci4.mode.asynchronous.free" configurationId="sci4.mode"/>
|
||||
<configSetting altId="sci4.rxd.p206" configurationId="sci4.rxd"/>
|
||||
<configSetting altId="sci4.txd.p205" configurationId="sci4.txd"/>
|
||||
<configSetting altId="sci9.mode.asynchronous.free" configurationId="sci9.mode"/>
|
||||
<configSetting altId="sci9.rxd.p110" configurationId="sci9.rxd"/>
|
||||
<configSetting altId="sci9.txd.p109" configurationId="sci9.txd"/>
|
||||
|
||||
410
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_adc_api.h
Normal file
410
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_adc_api.h
Normal file
@ -0,0 +1,410 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_ADC_API_H
|
||||
#define R_ADC_API_H
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @defgroup ADC_API ADC Interface
|
||||
* @brief Interface for A/D Converters.
|
||||
*
|
||||
* @section ADC_API_SUMMARY Summary
|
||||
* The ADC interface provides standard ADC functionality including one-shot mode (single scan), continuous scan and
|
||||
* group scan. It also allows configuration of hardware and software triggers for starting scans. After each conversion
|
||||
* an interrupt can be triggered, and if a callback function is provided, the call back is invoked with the
|
||||
* appropriate event information.
|
||||
*
|
||||
* Implemented by:
|
||||
* @ref ADC
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Includes board and MCU related header files. */
|
||||
#include "bsp_api.h"
|
||||
#include "r_elc_api.h"
|
||||
#include "r_transfer_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Typedef definitions
|
||||
******************************************************************************/
|
||||
|
||||
/** ADC operation mode definitions */
|
||||
typedef enum e_adc_mode
|
||||
{
|
||||
ADC_MODE_SINGLE_SCAN = 0, ///< Single scan - one or more channels
|
||||
ADC_MODE_GROUP_SCAN = 1, ///< Two trigger sources to trigger scan for two groups which contain one or more channels
|
||||
ADC_MODE_CONTINUOUS_SCAN = 2, ///< Continuous scan - one or more channels
|
||||
} adc_mode_t;
|
||||
|
||||
/** ADC data resolution definitions */
|
||||
typedef enum e_adc_resolution
|
||||
{
|
||||
ADC_RESOLUTION_12_BIT = 0, ///< 12 bit resolution
|
||||
ADC_RESOLUTION_10_BIT = 1, ///< 10 bit resolution
|
||||
ADC_RESOLUTION_8_BIT = 2, ///< 8 bit resolution
|
||||
ADC_RESOLUTION_14_BIT = 3, ///< 14 bit resolution
|
||||
ADC_RESOLUTION_16_BIT = 4, ///< 16 bit resolution
|
||||
ADC_RESOLUTION_24_BIT = 5, ///< 24 bit resolution
|
||||
} adc_resolution_t;
|
||||
|
||||
/** ADC data alignment definitions */
|
||||
typedef enum e_adc_alignment
|
||||
{
|
||||
ADC_ALIGNMENT_RIGHT = 0, ///< Data alignment right
|
||||
ADC_ALIGNMENT_LEFT = 1 ///< Data alignment left
|
||||
} adc_alignment_t;
|
||||
|
||||
/** ADC trigger mode definitions */
|
||||
typedef enum e_adc_trigger
|
||||
{
|
||||
ADC_TRIGGER_SOFTWARE = 0, ///< Software trigger; not for group modes
|
||||
ADC_TRIGGER_SYNC_ELC = 2, ///< Synchronous trigger via ELC
|
||||
ADC_TRIGGER_ASYNC_EXTERNAL = 3, ///< External asynchronous trigger; not for group modes
|
||||
} adc_trigger_t;
|
||||
|
||||
/** ADC callback event definitions */
|
||||
typedef enum e_adc_event
|
||||
{
|
||||
ADC_EVENT_SCAN_COMPLETE, ///< Normal/Group A scan complete
|
||||
ADC_EVENT_SCAN_COMPLETE_GROUP_B, ///< Group B scan complete
|
||||
ADC_EVENT_CALIBRATION_COMPLETE, ///< Calibration complete
|
||||
ADC_EVENT_CONVERSION_COMPLETE, ///< Conversion complete
|
||||
ADC_EVENT_CALIBRATION_REQUEST, ///< Calibration requested
|
||||
ADC_EVENT_CONVERSION_ERROR, ///< Scan error
|
||||
ADC_EVENT_OVERFLOW, ///< Overflow occurred
|
||||
ADC_EVENT_LIMIT_CLIP, ///< Limiter clipping occurred
|
||||
ADC_EVENT_FIFO_READ_REQUEST, ///< FIFO read requested
|
||||
ADC_EVENT_FIFO_OVERFLOW, ///< FIFO overflow occurred
|
||||
ADC_EVENT_WINDOW_COMPARE_A, ///< Window A comparison condition met
|
||||
ADC_EVENT_WINDOW_COMPARE_B, ///< Window B comparison condition met
|
||||
} adc_event_t;
|
||||
|
||||
#ifndef BSP_OVERRIDE_ADC_CHANNEL_T
|
||||
|
||||
/** ADC channels */
|
||||
typedef enum e_adc_channel
|
||||
{
|
||||
ADC_CHANNEL_0 = 0, ///< ADC channel 0
|
||||
ADC_CHANNEL_1 = 1, ///< ADC channel 1
|
||||
ADC_CHANNEL_2 = 2, ///< ADC channel 2
|
||||
ADC_CHANNEL_3 = 3, ///< ADC channel 3
|
||||
ADC_CHANNEL_4 = 4, ///< ADC channel 4
|
||||
ADC_CHANNEL_5 = 5, ///< ADC channel 5
|
||||
ADC_CHANNEL_6 = 6, ///< ADC channel 6
|
||||
ADC_CHANNEL_7 = 7, ///< ADC channel 7
|
||||
ADC_CHANNEL_8 = 8, ///< ADC channel 8
|
||||
ADC_CHANNEL_9 = 9, ///< ADC channel 9
|
||||
ADC_CHANNEL_10 = 10, ///< ADC channel 10
|
||||
ADC_CHANNEL_11 = 11, ///< ADC channel 11
|
||||
ADC_CHANNEL_12 = 12, ///< ADC channel 12
|
||||
ADC_CHANNEL_13 = 13, ///< ADC channel 13
|
||||
ADC_CHANNEL_14 = 14, ///< ADC channel 14
|
||||
ADC_CHANNEL_15 = 15, ///< ADC channel 15
|
||||
ADC_CHANNEL_16 = 16, ///< ADC channel 16
|
||||
ADC_CHANNEL_17 = 17, ///< ADC channel 17
|
||||
ADC_CHANNEL_18 = 18, ///< ADC channel 18
|
||||
ADC_CHANNEL_19 = 19, ///< ADC channel 19
|
||||
ADC_CHANNEL_20 = 20, ///< ADC channel 20
|
||||
ADC_CHANNEL_21 = 21, ///< ADC channel 21
|
||||
ADC_CHANNEL_22 = 22, ///< ADC channel 22
|
||||
ADC_CHANNEL_23 = 23, ///< ADC channel 23
|
||||
ADC_CHANNEL_24 = 24, ///< ADC channel 24
|
||||
ADC_CHANNEL_25 = 25, ///< ADC channel 25
|
||||
ADC_CHANNEL_26 = 26, ///< ADC channel 26
|
||||
ADC_CHANNEL_27 = 27, ///< ADC channel 27
|
||||
ADC_CHANNEL_28 = 28, ///< ADC channel 28
|
||||
ADC_CHANNEL_DUPLEX_A = 50, ///< Data duplexing register A
|
||||
ADC_CHANNEL_DUPLEX_B = 51, ///< Data duplexing register B
|
||||
ADC_CHANNEL_DUPLEX = -4, ///< Data duplexing register
|
||||
ADC_CHANNEL_TEMPERATURE = -3, ///< Temperature sensor output
|
||||
ADC_CHANNEL_VOLT = -2, ///< Internal reference voltage
|
||||
} adc_channel_t;
|
||||
|
||||
#endif
|
||||
|
||||
typedef enum e_adc_group_id
|
||||
{
|
||||
ADC_GROUP_ID_0 = 0, ///< Group ID 0
|
||||
ADC_GROUP_ID_1 = 1, ///< Group ID 1
|
||||
ADC_GROUP_ID_2 = 2, ///< Group ID 2
|
||||
ADC_GROUP_ID_3 = 3, ///< Group ID 3
|
||||
ADC_GROUP_ID_4 = 4, ///< Group ID 4
|
||||
ADC_GROUP_ID_5 = 5, ///< Group ID 5
|
||||
ADC_GROUP_ID_6 = 6, ///< Group ID 6
|
||||
ADC_GROUP_ID_7 = 7, ///< Group ID 7
|
||||
ADC_GROUP_ID_8 = 8, ///< Group ID 8
|
||||
} adc_group_id_t;
|
||||
|
||||
typedef enum e_adc_group_mask
|
||||
{
|
||||
ADC_GROUP_MASK_NONE = 0x000, ///< Group Mask Unknown or None
|
||||
ADC_GROUP_MASK_0 = 0x001, ///< Group Mask 0
|
||||
ADC_GROUP_MASK_1 = 0x002, ///< Group Mask 1
|
||||
ADC_GROUP_MASK_2 = 0x004, ///< Group Mask 2
|
||||
ADC_GROUP_MASK_3 = 0x008, ///< Group Mask 3
|
||||
ADC_GROUP_MASK_4 = 0x010, ///< Group Mask 4
|
||||
ADC_GROUP_MASK_5 = 0x020, ///< Group Mask 5
|
||||
ADC_GROUP_MASK_6 = 0x040, ///< Group Mask 6
|
||||
ADC_GROUP_MASK_7 = 0x080, ///< Group Mask 7
|
||||
ADC_GROUP_MASK_8 = 0x100, ///< Group Mask 8
|
||||
ADC_GROUP_MASK_ALL = 0x1FF, ///< All Groups
|
||||
} adc_group_mask_t;
|
||||
|
||||
/** ADC states. */
|
||||
typedef enum e_adc_state
|
||||
{
|
||||
ADC_STATE_IDLE = 0, ///< ADC is idle
|
||||
ADC_STATE_SCAN_IN_PROGRESS = 1, ///< ADC scan in progress
|
||||
} adc_state_t;
|
||||
|
||||
/** ADC status. */
|
||||
typedef struct st_adc_status
|
||||
{
|
||||
adc_state_t state; ///< Current state
|
||||
} adc_status_t;
|
||||
|
||||
/** ADC callback arguments definitions */
|
||||
typedef struct st_adc_callback_args
|
||||
{
|
||||
uint16_t unit; ///< ADC device in use
|
||||
adc_event_t event; ///< ADC callback event
|
||||
void const * p_context; ///< Placeholder for user data
|
||||
adc_channel_t channel; ///< Channel of conversion result. Only valid for r_adc ADC_EVENT_CONVERSION_COMPLETE
|
||||
uint64_t channel_mask; ///< Channel mask for conversion result. Only valid for r_adc_b
|
||||
adc_group_mask_t group_mask; ///< Group Mask
|
||||
} adc_callback_args_t;
|
||||
|
||||
/** ADC Information Structure for Transfer Interface */
|
||||
typedef struct st_adc_info
|
||||
{
|
||||
__I void * p_address; ///< The address to start reading the data from
|
||||
uint32_t length; ///< The total number of transfers to read
|
||||
|
||||
transfer_size_t transfer_size; ///< The size of each transfer
|
||||
elc_peripheral_t elc_peripheral; ///< Name of the peripheral in the ELC list
|
||||
elc_event_t elc_event; ///< Name of the ELC event for the peripheral
|
||||
uint32_t calibration_data; ///< Temperature sensor calibration data (0xFFFFFFFF if unsupported) for reference voltage
|
||||
int16_t slope_microvolts; ///< Temperature sensor slope in microvolts/degrees C
|
||||
bool calibration_ongoing; ///< Calibration is in progress.
|
||||
} adc_info_t;
|
||||
|
||||
/** ADC general configuration */
|
||||
typedef struct st_adc_cfg
|
||||
{
|
||||
uint16_t unit; ///< ADC unit to be used
|
||||
adc_mode_t mode; ///< ADC operation mode
|
||||
adc_resolution_t resolution; ///< ADC resolution
|
||||
adc_alignment_t alignment; ///< Specify left or right alignment; ignored if addition used
|
||||
adc_trigger_t trigger; ///< Default and Group A trigger source
|
||||
IRQn_Type scan_end_irq; ///< Scan end IRQ number
|
||||
IRQn_Type scan_end_b_irq; ///< Scan end group B IRQ number
|
||||
uint8_t scan_end_ipl; ///< Scan end interrupt priority
|
||||
uint8_t scan_end_b_ipl; ///< Scan end group B interrupt priority
|
||||
void (* p_callback)(adc_callback_args_t * p_args); ///< Callback function; set to NULL for none
|
||||
void const * p_context; ///< Placeholder for user data. Passed to the user callback in @ref adc_callback_args_t.
|
||||
void const * p_extend; ///< Extension parameter for hardware specific settings
|
||||
} adc_cfg_t;
|
||||
|
||||
/** ADC control block. Allocate using driver instance control structure from driver instance header file. */
|
||||
typedef void adc_ctrl_t;
|
||||
|
||||
/** ADC functions implemented at the HAL layer will follow this API. */
|
||||
typedef struct st_adc_api
|
||||
{
|
||||
/** Initialize ADC Unit; apply power, set the operational mode, trigger sources, interrupt priority,
|
||||
* and configurations common to all channels and sensors.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_Open()
|
||||
* - @ref R_ADC_B_Open()
|
||||
* - @ref R_SDADC_Open()
|
||||
*
|
||||
* @pre Configure peripheral clocks, ADC pins and IRQs prior to calling this function.
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
* @param[in] p_cfg Pointer to configuration structure
|
||||
*/
|
||||
fsp_err_t (* open)(adc_ctrl_t * const p_ctrl, adc_cfg_t const * const p_cfg);
|
||||
|
||||
/** Configure the scan including the channels, groups, and scan triggers to be used for the unit that
|
||||
* was initialized in the open call. Some configurations are not supported for all implementations.
|
||||
* See implementation for details.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_ScanCfg()
|
||||
* - @ref R_ADC_B_ScanCfg()
|
||||
* - @ref R_SDADC_ScanCfg()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
* @param[in] p_extend See implementation for details
|
||||
*/
|
||||
fsp_err_t (* scanCfg)(adc_ctrl_t * const p_ctrl, void const * const p_extend);
|
||||
|
||||
/** Start the scan (in case of a software trigger), or enable the hardware trigger.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_ScanStart()
|
||||
* - @ref R_SDADC_ScanStart()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
*/
|
||||
fsp_err_t (* scanStart)(adc_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Start the scan group (in case of a software trigger), or enable the hardware trigger.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_B_ScanGroupStart()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
* @param[in] group_mask Mask of groups to start
|
||||
*/
|
||||
fsp_err_t (* scanGroupStart)(adc_ctrl_t * p_ctrl, adc_group_mask_t group_mask);
|
||||
|
||||
/** Stop the ADC scan (in case of a software trigger), or disable the hardware trigger.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_ScanStop()
|
||||
* - @ref R_SDADC_ScanStop()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
*/
|
||||
fsp_err_t (* scanStop)(adc_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Check scan status.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_StatusGet()
|
||||
* - @ref R_ADC_B_StatusGet()
|
||||
* - @ref R_SDADC_StatusGet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
* @param[out] p_status Pointer to store current status in
|
||||
*/
|
||||
fsp_err_t (* scanStatusGet)(adc_ctrl_t * const p_ctrl, adc_status_t * p_status);
|
||||
|
||||
/** Read ADC conversion result.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_Read()
|
||||
* - @ref R_ADC_B_Read()
|
||||
* - @ref R_SDADC_Read()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
* @param[in] reg_id ADC channel to read (see enumeration adc_channel_t)
|
||||
* @param[in] p_data Pointer to variable to load value into.
|
||||
*/
|
||||
fsp_err_t (* read)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data);
|
||||
|
||||
/** Read ADC conversion result into a 32-bit word.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_Read32()
|
||||
* - @ref R_ADC_B_Read32()
|
||||
* - @ref R_SDADC_Read32()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
* @param[in] reg_id ADC channel to read (see enumeration adc_channel_t)
|
||||
* @param[in] p_data Pointer to variable to load value into.
|
||||
*/
|
||||
fsp_err_t (* read32)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data);
|
||||
|
||||
/** Calibrate ADC or associated PGA (programmable gain amplifier). The driver may require implementation specific
|
||||
* arguments to the p_extend input. Not supported for all implementations. See implementation for details.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_Calibrate()
|
||||
* - @ref R_ADC_B_Calibrate()
|
||||
* - @ref R_SDADC_Calibrate()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
* @param[in] p_extend Pointer to implementation specific arguments
|
||||
*/
|
||||
fsp_err_t (* calibrate)(adc_ctrl_t * const p_ctrl, void const * p_extend);
|
||||
|
||||
/** Set offset for input PGA configured for differential input. Not supported for all implementations.
|
||||
* See implementation for details.
|
||||
* @par Implemented as
|
||||
* - @ref R_SDADC_OffsetSet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
* @param[in] reg_id ADC channel to read (see enumeration adc_channel_t)
|
||||
* @param[in] offset See implementation for details.
|
||||
*/
|
||||
fsp_err_t (* offsetSet)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t const offset);
|
||||
|
||||
/**
|
||||
* Specify callback function and optional context pointer and working memory pointer.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_CallbackSet()
|
||||
* - @ref R_ADC_B_CallbackSet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to the ADC control block.
|
||||
* @param[in] p_callback Callback function
|
||||
* @param[in] p_context Pointer to send to callback function
|
||||
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
|
||||
* Callback arguments allocated here are only valid during the callback.
|
||||
*/
|
||||
fsp_err_t (* callbackSet)(adc_ctrl_t * const p_api_ctrl, void (* p_callback)(adc_callback_args_t *),
|
||||
void const * const p_context, adc_callback_args_t * const p_callback_memory);
|
||||
|
||||
/** Close the specified ADC unit by ending any scan in progress, disabling interrupts, and removing power to the
|
||||
* specified A/D unit.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_Close()
|
||||
* - @ref R_ADC_B_Close()
|
||||
* - @ref R_SDADC_Close()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
*/
|
||||
fsp_err_t (* close)(adc_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Return the ADC data register address of the first (lowest number) channel and the total number of bytes
|
||||
* to be read in order for the DTC/DMAC to read the conversion results of all configured channels.
|
||||
* Return the temperature sensor calibration and slope data.
|
||||
* @par Implemented as
|
||||
* - @ref R_ADC_InfoGet()
|
||||
* - @ref R_ADC_B_InfoGet()
|
||||
* - @ref R_SDADC_InfoGet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control handle structure
|
||||
* @param[out] p_adc_info Pointer to ADC information structure
|
||||
*/
|
||||
fsp_err_t (* infoGet)(adc_ctrl_t * const p_ctrl, adc_info_t * const p_adc_info);
|
||||
} adc_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_adc_instance
|
||||
{
|
||||
adc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
adc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
void const * p_channel_cfg; ///< Pointer to the channel configuration structure for this instance
|
||||
adc_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} adc_instance_t;
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup ADC_API)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
#endif
|
||||
185
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_elc_api.h
Normal file
185
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_elc_api.h
Normal file
@ -0,0 +1,185 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @defgroup ELC_API ELC Interface
|
||||
* @brief Interface for the Event Link Controller.
|
||||
*
|
||||
*
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_ELC_API_H
|
||||
#define R_ELC_API_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Register definitions, common services and error codes. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
#ifndef ELC_PERIPHERAL_NUM
|
||||
#define ELC_PERIPHERAL_NUM (23U)
|
||||
#endif
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef BSP_OVERRIDE_ELC_PERIPHERAL_T
|
||||
|
||||
/** Possible peripherals to be linked to event signals (not all available on all MCUs) */
|
||||
typedef enum e_elc_peripheral
|
||||
{
|
||||
ELC_PERIPHERAL_GPT_A = (0),
|
||||
ELC_PERIPHERAL_GPT_B = (1),
|
||||
ELC_PERIPHERAL_GPT_C = (2),
|
||||
ELC_PERIPHERAL_GPT_D = (3),
|
||||
ELC_PERIPHERAL_GPT_E = (4),
|
||||
ELC_PERIPHERAL_GPT_F = (5),
|
||||
ELC_PERIPHERAL_GPT_G = (6),
|
||||
ELC_PERIPHERAL_GPT_H = (7),
|
||||
ELC_PERIPHERAL_ADC0 = (8),
|
||||
ELC_PERIPHERAL_ADC0_B = (9),
|
||||
ELC_PERIPHERAL_ADC1 = (10),
|
||||
ELC_PERIPHERAL_ADC1_B = (11),
|
||||
ELC_PERIPHERAL_DAC0 = (12),
|
||||
ELC_PERIPHERAL_DAC1 = (13),
|
||||
ELC_PERIPHERAL_IOPORT1 = (14),
|
||||
ELC_PERIPHERAL_IOPORT2 = (15),
|
||||
ELC_PERIPHERAL_IOPORT3 = (16),
|
||||
ELC_PERIPHERAL_IOPORT4 = (17),
|
||||
ELC_PERIPHERAL_CTSU = (18),
|
||||
ELC_PERIPHERAL_DA8_0 = (19),
|
||||
ELC_PERIPHERAL_DA8_1 = (20),
|
||||
ELC_PERIPHERAL_SDADC0 = (22),
|
||||
} elc_peripheral_t;
|
||||
|
||||
#endif
|
||||
|
||||
/** ELC control block. Allocate an instance specific control block to pass into the ELC API calls.
|
||||
* @par Implemented as
|
||||
* - elc_instance_ctrl_t
|
||||
*/
|
||||
typedef void elc_ctrl_t;
|
||||
|
||||
/** Main configuration structure for the Event Link Controller */
|
||||
typedef struct st_elc_cfg
|
||||
{
|
||||
elc_event_t const link[ELC_PERIPHERAL_NUM]; ///< Event link register (ELSR) settings
|
||||
} elc_cfg_t;
|
||||
|
||||
/** Software event number */
|
||||
typedef enum e_elc_software_event
|
||||
{
|
||||
ELC_SOFTWARE_EVENT_0, ///< Software event 0
|
||||
ELC_SOFTWARE_EVENT_1, ///< Software event 1
|
||||
} elc_software_event_t;
|
||||
|
||||
/** ELC driver structure. General ELC functions implemented at the HAL layer follow this API. */
|
||||
typedef struct st_elc_api
|
||||
{
|
||||
/** Initialize all links in the Event Link Controller.
|
||||
* @par Implemented as
|
||||
* - @ref R_ELC_Open()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control structure.
|
||||
* @param[in] p_cfg Pointer to configuration structure.
|
||||
**/
|
||||
fsp_err_t (* open)(elc_ctrl_t * const p_ctrl, elc_cfg_t const * const p_cfg);
|
||||
|
||||
/** Disable all links in the Event Link Controller and close the API.
|
||||
* @par Implemented as
|
||||
* - @ref R_ELC_Close()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control structure.
|
||||
**/
|
||||
fsp_err_t (* close)(elc_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Generate a software event in the Event Link Controller.
|
||||
* @par Implemented as
|
||||
* - @ref R_ELC_SoftwareEventGenerate()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control structure.
|
||||
* @param[in] eventNum Software event number to be generated.
|
||||
**/
|
||||
fsp_err_t (* softwareEventGenerate)(elc_ctrl_t * const p_ctrl, elc_software_event_t event_num);
|
||||
|
||||
/** Create a single event link.
|
||||
* @par Implemented as
|
||||
* - @ref R_ELC_LinkSet()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control structure.
|
||||
* @param[in] peripheral The peripheral block that will receive the event signal.
|
||||
* @param[in] signal The event signal.
|
||||
**/
|
||||
fsp_err_t (* linkSet)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal);
|
||||
|
||||
/** Break an event link.
|
||||
* @par Implemented as
|
||||
* - @ref R_ELC_LinkBreak()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control structure.
|
||||
* @param[in] peripheral The peripheral that should no longer be linked.
|
||||
**/
|
||||
fsp_err_t (* linkBreak)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral);
|
||||
|
||||
/** Enable the operation of the Event Link Controller.
|
||||
* @par Implemented as
|
||||
* - @ref R_ELC_Enable()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control structure.
|
||||
**/
|
||||
fsp_err_t (* enable)(elc_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Disable the operation of the Event Link Controller.
|
||||
* @par Implemented as
|
||||
* - @ref R_ELC_Disable()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control structure.
|
||||
**/
|
||||
fsp_err_t (* disable)(elc_ctrl_t * const p_ctrl);
|
||||
} elc_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_elc_instance
|
||||
{
|
||||
elc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
elc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
elc_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} elc_instance_t;
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end addtogroup ELC_API)
|
||||
**********************************************************************************************************************/
|
||||
332
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_timer_api.h
Normal file
332
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_timer_api.h
Normal file
@ -0,0 +1,332 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_TIMER_API_H
|
||||
#define R_TIMER_API_H
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @defgroup TIMER_API Timer Interface
|
||||
* @ingroup RENESAS_INTERFACES
|
||||
* @brief Interface for timer functions.
|
||||
*
|
||||
* @section TIMER_API_SUMMARY Summary
|
||||
* The general timer interface provides standard timer functionality including periodic mode, one-shot mode, PWM output,
|
||||
* and free-running timer mode. After each timer cycle (overflow or underflow), an interrupt can be triggered.
|
||||
*
|
||||
* If an instance supports output compare mode, it is provided in the extension configuration
|
||||
* timer_on_<instance>_cfg_t defined in r_<instance>.h.
|
||||
*
|
||||
* Implemented by:
|
||||
* - @ref GPT
|
||||
* - @ref AGT
|
||||
*
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Includes board and MCU related header files. */
|
||||
#include "bsp_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Leading zeroes removed to avoid coding standard violation. */
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Events that can trigger a callback function */
|
||||
typedef enum e_timer_event
|
||||
{
|
||||
TIMER_EVENT_CYCLE_END, ///< Requested timer delay has expired or timer has wrapped around
|
||||
TIMER_EVENT_CREST = TIMER_EVENT_CYCLE_END, ///< Timer crest event (counter is at a maximum, triangle-wave PWM only)
|
||||
TIMER_EVENT_CAPTURE_A, ///< A capture has occurred on signal A
|
||||
TIMER_EVENT_CAPTURE_B, ///< A capture has occurred on signal B
|
||||
TIMER_EVENT_TROUGH, ///< Timer trough event (counter is 0, triangle-wave PWM only
|
||||
} timer_event_t;
|
||||
|
||||
/** Timer variant types. */
|
||||
typedef enum e_timer_variant
|
||||
{
|
||||
TIMER_VARIANT_32_BIT, ///< 32-bit timer
|
||||
TIMER_VARIANT_16_BIT ///< 16-bit timer
|
||||
} timer_variant_t;
|
||||
|
||||
/** Callback function parameter data */
|
||||
typedef struct st_timer_callback_args
|
||||
{
|
||||
/** Placeholder for user data. Set in @ref timer_api_t::open function in @ref timer_cfg_t. */
|
||||
void const * p_context;
|
||||
timer_event_t event; ///< The event can be used to identify what caused the callback.
|
||||
|
||||
/** Most recent capture, only valid if event is TIMER_EVENT_CAPTURE_A or TIMER_EVENT_CAPTURE_B. */
|
||||
uint32_t capture;
|
||||
} timer_callback_args_t;
|
||||
|
||||
/** Timer control block. Allocate an instance specific control block to pass into the timer API calls.
|
||||
* @par Implemented as
|
||||
* - gpt_instance_ctrl_t
|
||||
* - agt_instance_ctrl_t
|
||||
*/
|
||||
typedef void timer_ctrl_t;
|
||||
|
||||
/** Possible status values returned by @ref timer_api_t::statusGet. */
|
||||
typedef enum e_timer_state
|
||||
{
|
||||
TIMER_STATE_STOPPED = 0, ///< Timer is stopped
|
||||
TIMER_STATE_COUNTING = 1, ///< Timer is running
|
||||
} timer_state_t;
|
||||
|
||||
/** Timer operational modes */
|
||||
typedef enum e_timer_mode
|
||||
{
|
||||
TIMER_MODE_PERIODIC, ///< Timer restarts after period elapses.
|
||||
TIMER_MODE_ONE_SHOT, ///< Timer stops after period elapses.
|
||||
TIMER_MODE_PWM, ///< Timer generates saw-wave PWM output.
|
||||
TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM = 4U, ///< Timer generates symmetric triangle-wave PWM output.
|
||||
TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM = 5U, ///< Timer generates asymmetric triangle-wave PWM output.
|
||||
|
||||
/**
|
||||
* Timer generates Asymmetric Triangle-wave PWM output. In PWM mode 3, the duty cycle does
|
||||
* not need to be updated at each tough/crest interrupt. Instead, the trough and crest duty cycle values can be
|
||||
* set once and only need to be updated when the application needs to change the duty cycle.
|
||||
*/
|
||||
TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 = 6U,
|
||||
} timer_mode_t;
|
||||
|
||||
/** Direction of timer count */
|
||||
typedef enum e_timer_direction
|
||||
{
|
||||
TIMER_DIRECTION_DOWN = 0, ///< Timer count goes up
|
||||
TIMER_DIRECTION_UP = 1 ///< Timer count goes down
|
||||
} timer_direction_t;
|
||||
|
||||
/** PCLK divisors */
|
||||
typedef enum e_timer_source_div
|
||||
{
|
||||
TIMER_SOURCE_DIV_1 = 0, ///< Timer clock source divided by 1
|
||||
TIMER_SOURCE_DIV_2 = 1, ///< Timer clock source divided by 2
|
||||
TIMER_SOURCE_DIV_4 = 2, ///< Timer clock source divided by 4
|
||||
TIMER_SOURCE_DIV_8 = 3, ///< Timer clock source divided by 8
|
||||
TIMER_SOURCE_DIV_16 = 4, ///< Timer clock source divided by 16
|
||||
TIMER_SOURCE_DIV_32 = 5, ///< Timer clock source divided by 32
|
||||
TIMER_SOURCE_DIV_64 = 6, ///< Timer clock source divided by 64
|
||||
TIMER_SOURCE_DIV_128 = 7, ///< Timer clock source divided by 128
|
||||
TIMER_SOURCE_DIV_256 = 8, ///< Timer clock source divided by 256
|
||||
TIMER_SOURCE_DIV_512 = 9, ///< Timer clock source divided by 512
|
||||
TIMER_SOURCE_DIV_1024 = 10, ///< Timer clock source divided by 1024
|
||||
} timer_source_div_t;
|
||||
|
||||
/** Timer information structure to store various information for a timer resource */
|
||||
typedef struct st_timer_info
|
||||
{
|
||||
timer_direction_t count_direction; ///< Clock counting direction of the timer.
|
||||
uint32_t clock_frequency; ///< Clock frequency of the timer counter.
|
||||
|
||||
/** Period in raw timer counts.
|
||||
* @note For triangle wave PWM modes, the full period is double this value.
|
||||
*/
|
||||
uint32_t period_counts;
|
||||
} timer_info_t;
|
||||
|
||||
/** Current timer status. */
|
||||
typedef struct st_timer_status
|
||||
{
|
||||
uint32_t counter; ///< Current counter value
|
||||
timer_state_t state; ///< Current timer state (running or stopped)
|
||||
} timer_status_t;
|
||||
|
||||
/** User configuration structure, used in open function */
|
||||
typedef struct st_timer_cfg
|
||||
{
|
||||
timer_mode_t mode; ///< Select enumerated value from @ref timer_mode_t
|
||||
|
||||
/* Period in raw timer counts.
|
||||
* @note For triangle wave PWM modes, enter the period of half the triangle wave, or half the desired period.
|
||||
*/
|
||||
uint32_t period_counts; ///< Period in raw timer counts
|
||||
timer_source_div_t source_div; ///< Source clock divider
|
||||
uint32_t duty_cycle_counts; ///< Duty cycle in counts
|
||||
|
||||
/** Select a channel corresponding to the channel number of the hardware. */
|
||||
uint8_t channel;
|
||||
uint8_t cycle_end_ipl; ///< Cycle end interrupt priority
|
||||
IRQn_Type cycle_end_irq; ///< Cycle end interrupt
|
||||
|
||||
/** Callback provided when a timer ISR occurs. Set to NULL for no CPU interrupt. */
|
||||
void (* p_callback)(timer_callback_args_t * p_args);
|
||||
|
||||
/** Placeholder for user data. Passed to the user callback in @ref timer_callback_args_t. */
|
||||
void const * p_context;
|
||||
void const * p_extend; ///< Extension parameter for hardware specific settings.
|
||||
} timer_cfg_t;
|
||||
|
||||
/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */
|
||||
typedef struct st_timer_api
|
||||
{
|
||||
/** Initial configuration.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Open()
|
||||
* - @ref R_AGT_Open()
|
||||
*
|
||||
* @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
|
||||
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user.
|
||||
*/
|
||||
fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
|
||||
|
||||
/** Start the counter.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Start()
|
||||
* - @ref R_AGT_Start()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* start)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Stop the counter.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Stop()
|
||||
* - @ref R_AGT_Stop()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Reset the counter to the initial value.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Reset()
|
||||
* - @ref R_AGT_Reset()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Enables input capture.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Enable()
|
||||
* - @ref R_AGT_Enable()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Disables input capture.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Disable()
|
||||
* - @ref R_AGT_Disable()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* disable)(timer_ctrl_t * const p_ctrl);
|
||||
|
||||
/** Set the time until the timer expires. See implementation for details of period update timing.
|
||||
*
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_PeriodSet()
|
||||
* - @ref R_AGT_PeriodSet()
|
||||
*
|
||||
* @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in
|
||||
* @ref timer_api_t::open.
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[in] p_period Time until timer should expire.
|
||||
*/
|
||||
fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period);
|
||||
|
||||
/** Sets the number of counts for the pin level to be high. If the timer is counting, the updated duty cycle is
|
||||
* reflected after the next timer expiration.
|
||||
*
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_DutyCycleSet()
|
||||
* - @ref R_AGT_DutyCycleSet()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[in] duty_cycle_counts Time until duty cycle should expire.
|
||||
* @param[in] pin Which output pin to update. See implementation for details.
|
||||
*/
|
||||
fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
|
||||
|
||||
/** Stores timer information in p_info.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_InfoGet()
|
||||
* - @ref R_AGT_InfoGet()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[out] p_info Collection of information for this timer.
|
||||
*/
|
||||
fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
|
||||
|
||||
/** Get the current counter value and timer state and store it in p_status.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_StatusGet()
|
||||
* - @ref R_AGT_StatusGet()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[out] p_status Current status of this timer.
|
||||
*/
|
||||
fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
|
||||
|
||||
/** Specify callback function and optional context pointer and working memory pointer.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_CallbackSet()
|
||||
* - @ref R_AGT_CallbackSet()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
* @param[in] p_callback Callback function to register
|
||||
* @param[in] p_context Pointer to send to callback function
|
||||
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
|
||||
* Callback arguments allocated here are only valid during the callback.
|
||||
*/
|
||||
fsp_err_t (* callbackSet)(timer_ctrl_t * const p_api_ctrl, void (* p_callback)(timer_callback_args_t *),
|
||||
void const * const p_context, timer_callback_args_t * const p_callback_memory);
|
||||
|
||||
/** Allows driver to be reconfigured and may reduce power consumption.
|
||||
* @par Implemented as
|
||||
* - @ref R_GPT_Close()
|
||||
* - @ref R_AGT_Close()
|
||||
*
|
||||
* @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
|
||||
*/
|
||||
fsp_err_t (* close)(timer_ctrl_t * const p_ctrl);
|
||||
} timer_api_t;
|
||||
|
||||
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||
typedef struct st_timer_instance
|
||||
{
|
||||
timer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||
timer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||
timer_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||
} timer_instance_t;
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup TIMER_API)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
359
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_adc.h
Normal file
359
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_adc.h
Normal file
@ -0,0 +1,359 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_ADC_H
|
||||
#define R_ADC_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include <stdlib.h>
|
||||
|
||||
/* Fixed width integer support. */
|
||||
#include <stdint.h>
|
||||
|
||||
/* bool support */
|
||||
#include <stdbool.h>
|
||||
#include "bsp_api.h"
|
||||
#include "r_adc_cfg.h"
|
||||
#include "r_adc_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup ADC
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Typical values that can be used to modify the sample states.
|
||||
* The minimum sample state count value is either 6 or 7 depending on the clock ratios.
|
||||
* It is fixed to 7 based on the fact that at the lowest ADC conversion clock supported (1 MHz)
|
||||
* this extra state will lead to at worst a "1 microsecond" increase in conversion time.
|
||||
* At 60 MHz the extra sample state will add 16.7 ns to the conversion time.
|
||||
*/
|
||||
#define ADC_SAMPLE_STATE_COUNT_MIN (7U)
|
||||
#define ADC_SAMPLE_STATE_COUNT_MAX (255U)
|
||||
|
||||
/* Typical values that can be used for the sample and hold counts for the channels 0-2*/
|
||||
/* Minimum sample and hold states */
|
||||
#define ADC_SAMPLE_STATE_HOLD_COUNT_MIN (4U)
|
||||
|
||||
/* Default sample and hold states */
|
||||
#define ADC_SAMPLE_STATE_HOLD_COUNT_DEFAULT (24U)
|
||||
|
||||
/** For ADC Scan configuration adc_channel_cfg_t::scan_mask, adc_channel_cfg_t::scan_mask_group_b,
|
||||
* adc_channel_cfg_t::add_mask and adc_channel_cfg_t::sample_hold_mask.
|
||||
* Use bitwise OR to combine these masks for desired channels and sensors. */
|
||||
typedef enum e_adc_mask
|
||||
{
|
||||
ADC_MASK_OFF = (0U), ///< No channels selected
|
||||
ADC_MASK_CHANNEL_0 = (1U << 0U), ///< Channel 0 mask
|
||||
ADC_MASK_CHANNEL_1 = (1U << 1U), ///< Channel 1 mask
|
||||
ADC_MASK_CHANNEL_2 = (1U << 2U), ///< Channel 2 mask
|
||||
ADC_MASK_CHANNEL_3 = (1U << 3U), ///< Channel 3 mask
|
||||
ADC_MASK_CHANNEL_4 = (1U << 4U), ///< Channel 4 mask
|
||||
ADC_MASK_CHANNEL_5 = (1U << 5U), ///< Channel 5 mask
|
||||
ADC_MASK_CHANNEL_6 = (1U << 6U), ///< Channel 6 mask
|
||||
ADC_MASK_CHANNEL_7 = (1U << 7U), ///< Channel 7 mask
|
||||
ADC_MASK_CHANNEL_8 = (1U << 8U), ///< Channel 8 mask
|
||||
ADC_MASK_CHANNEL_9 = (1U << 9U), ///< Channel 9 mask
|
||||
ADC_MASK_CHANNEL_10 = (1U << 10U), ///< Channel 10 mask
|
||||
ADC_MASK_CHANNEL_11 = (1U << 11U), ///< Channel 11 mask
|
||||
ADC_MASK_CHANNEL_12 = (1U << 12U), ///< Channel 12 mask
|
||||
ADC_MASK_CHANNEL_13 = (1U << 13U), ///< Channel 13 mask
|
||||
ADC_MASK_CHANNEL_14 = (1U << 14U), ///< Channel 14 mask
|
||||
ADC_MASK_CHANNEL_15 = (1U << 15U), ///< Channel 15 mask
|
||||
ADC_MASK_CHANNEL_16 = (1U << 16U), ///< Channel 16 mask
|
||||
ADC_MASK_CHANNEL_17 = (1U << 17U), ///< Channel 17 mask
|
||||
ADC_MASK_CHANNEL_18 = (1U << 18U), ///< Channel 18 mask
|
||||
ADC_MASK_CHANNEL_19 = (1U << 19U), ///< Channel 19 mask
|
||||
ADC_MASK_CHANNEL_20 = (1U << 20U), ///< Channel 20 mask
|
||||
ADC_MASK_CHANNEL_21 = (1U << 21U), ///< Channel 21 mask
|
||||
ADC_MASK_CHANNEL_22 = (1U << 22U), ///< Channel 22 mask
|
||||
ADC_MASK_CHANNEL_23 = (1U << 23U), ///< Channel 23 mask
|
||||
ADC_MASK_CHANNEL_24 = (1U << 24U), ///< Channel 24 mask
|
||||
ADC_MASK_CHANNEL_25 = (1U << 25U), ///< Channel 25 mask
|
||||
ADC_MASK_CHANNEL_26 = (1U << 26U), ///< Channel 26 mask
|
||||
ADC_MASK_CHANNEL_27 = (1U << 27U), ///< Channel 27 mask
|
||||
ADC_MASK_TEMPERATURE = (1U << 28UL), ///< Temperature sensor channel mask
|
||||
ADC_MASK_VOLT = (1U << 29UL), ///< Voltage reference channel mask
|
||||
ADC_MASK_SENSORS = (ADC_MASK_TEMPERATURE | ADC_MASK_VOLT), ///< All sensor channel mask
|
||||
} adc_mask_t;
|
||||
|
||||
/** ADC data sample addition and averaging options */
|
||||
typedef enum e_adc_add
|
||||
{
|
||||
ADC_ADD_OFF = 0, ///< Addition turned off for channels/sensors
|
||||
ADC_ADD_TWO = 1, ///< Add two samples
|
||||
ADC_ADD_THREE = 2, ///< Add three samples
|
||||
ADC_ADD_FOUR = 3, ///< Add four samples
|
||||
ADC_ADD_SIXTEEN = 5, ///< Add sixteen samples
|
||||
ADC_ADD_AVERAGE_TWO = 0x81, ///< Average two samples
|
||||
ADC_ADD_AVERAGE_FOUR = 0x83, ///< Average four samples
|
||||
ADC_ADD_AVERAGE_EIGHT = 0x84, ///< Average eight samples
|
||||
ADC_ADD_AVERAGE_SIXTEEN = 0x85, ///< Add sixteen samples
|
||||
} adc_add_t;
|
||||
|
||||
/** ADC clear after read definitions */
|
||||
typedef enum e_adc_clear
|
||||
{
|
||||
ADC_CLEAR_AFTER_READ_OFF = 0, ///< Clear after read off
|
||||
ADC_CLEAR_AFTER_READ_ON = 1 ///< Clear after read on
|
||||
} adc_clear_t;
|
||||
|
||||
/* VREF configuration options, not all options are available on all MCUs. If the MCU does not have VREFAMPCNT or
|
||||
* ADHVREFCNT. */
|
||||
typedef enum e_adc_vref_control
|
||||
{
|
||||
/* Available selections on MCUs with VREFAMPCNT.
|
||||
* Reference Table 32.12 "VREFADC output voltage control list" in the RA2A1 manual R01UH0888EJ0100.*/
|
||||
|
||||
ADC_VREF_CONTROL_VREFH = 0, ///< VREFAMPCNT reset value. VREFADC Output voltage is Hi-Z
|
||||
ADC_VREF_CONTROL_1_5V_OUTPUT = 25, ///< BGR turn ON. VREFADC Output voltage is 1.5 V
|
||||
ADC_VREF_CONTROL_2_0V_OUTPUT = 29, ///< BGR turn ON. VREFADC Output voltage is 2.0 V
|
||||
ADC_VREF_CONTROL_2_5V_OUTPUT = 31, ///< BGR turn ON. VREFADC Output voltage is 2.5 V
|
||||
|
||||
/* Available selections on MCUs with ADHVREFCNT.
|
||||
* Reference Section 35.2.31 "A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT)"
|
||||
* in the RA4M1 manual R01UH0887EJ0100.*/
|
||||
|
||||
ADC_VREF_CONTROL_AVCC0_AVSS0 = 0x0, ///< High potential is AVCC0, low potential is AVSS0
|
||||
ADC_VREF_CONTROL_VREFH0_AVSS0 = 0x1, ///< High potential is VREFH0, low potential is AVSS0
|
||||
|
||||
/** High potential is internal reference voltage, low potential is AVSS0. When the high potential is set to the
|
||||
* internal reference voltage, wait 5 us after R_ADC_Open() to start an ADC measurement. */
|
||||
ADC_VREF_CONTROL_IVREF_AVSS0 = 0x2,
|
||||
ADC_VREF_CONTROL_AVCC0_VREFL0 = 0x10, ///< High potential is AVCC0, low potential is VREFL0
|
||||
ADC_VREF_CONTROL_VREFH0_VREFL0 = 0x11, ///< High potential is VREFH0, low potential is VREFL0
|
||||
|
||||
/** High potential is internal reference voltage, low potential is VREFL0. When the high potential is set to the
|
||||
* internal reference voltage, wait 5 us after R_ADC_Open() to start an ADC measurement. */
|
||||
ADC_VREF_CONTROL_IVREF_VREFL0 = 0x12,
|
||||
} adc_vref_control_t;
|
||||
|
||||
/** ADC sample state registers */
|
||||
typedef enum e_adc_sample_state_reg
|
||||
{
|
||||
ADC_SAMPLE_STATE_CHANNEL_0 = 0, ///< Sample state register channel 0
|
||||
ADC_SAMPLE_STATE_CHANNEL_1, ///< Sample state register channel 1
|
||||
ADC_SAMPLE_STATE_CHANNEL_2, ///< Sample state register channel 2
|
||||
ADC_SAMPLE_STATE_CHANNEL_3, ///< Sample state register channel 3
|
||||
ADC_SAMPLE_STATE_CHANNEL_4, ///< Sample state register channel 4
|
||||
ADC_SAMPLE_STATE_CHANNEL_5, ///< Sample state register channel 5
|
||||
ADC_SAMPLE_STATE_CHANNEL_6, ///< Sample state register channel 6
|
||||
ADC_SAMPLE_STATE_CHANNEL_7, ///< Sample state register channel 7
|
||||
ADC_SAMPLE_STATE_CHANNEL_8, ///< Sample state register channel 8
|
||||
ADC_SAMPLE_STATE_CHANNEL_9, ///< Sample state register channel 9
|
||||
ADC_SAMPLE_STATE_CHANNEL_10, ///< Sample state register channel 10
|
||||
ADC_SAMPLE_STATE_CHANNEL_11, ///< Sample state register channel 11
|
||||
ADC_SAMPLE_STATE_CHANNEL_12, ///< Sample state register channel 12
|
||||
ADC_SAMPLE_STATE_CHANNEL_13, ///< Sample state register channel 13
|
||||
ADC_SAMPLE_STATE_CHANNEL_14, ///< Sample state register channel 14
|
||||
ADC_SAMPLE_STATE_CHANNEL_15, ///< Sample state register channel 15
|
||||
ADC_SAMPLE_STATE_CHANNEL_16_TO_31 = -3, ///< Sample state register channel 16 to 31
|
||||
} adc_sample_state_reg_t;
|
||||
|
||||
/** ADC comparison settings */
|
||||
typedef enum e_adc_compare_cfg
|
||||
{
|
||||
ADC_COMPARE_CFG_EVENT_OUTPUT_OR = 0,
|
||||
ADC_COMPARE_CFG_EVENT_OUTPUT_XOR = 1,
|
||||
ADC_COMPARE_CFG_EVENT_OUTPUT_AND = 2,
|
||||
ADC_COMPARE_CFG_A_ENABLE = R_ADC0_ADCMPCR_CMPAE_Msk | R_ADC0_ADCMPCR_CMPAIE_Msk,
|
||||
ADC_COMPARE_CFG_B_ENABLE = R_ADC0_ADCMPCR_CMPBE_Msk | R_ADC0_ADCMPCR_CMPBIE_Msk,
|
||||
ADC_COMPARE_CFG_WINDOW_ENABLE = R_ADC0_ADCMPCR_WCMPE_Msk,
|
||||
} adc_compare_cfg_t;
|
||||
|
||||
/** ADC Window B channel */
|
||||
typedef enum e_adc_window_b_channel
|
||||
{
|
||||
ADC_WINDOW_B_CHANNEL_0 = 0,
|
||||
ADC_WINDOW_B_CHANNEL_1,
|
||||
ADC_WINDOW_B_CHANNEL_2,
|
||||
ADC_WINDOW_B_CHANNEL_3,
|
||||
ADC_WINDOW_B_CHANNEL_4,
|
||||
ADC_WINDOW_B_CHANNEL_5,
|
||||
ADC_WINDOW_B_CHANNEL_6,
|
||||
ADC_WINDOW_B_CHANNEL_7,
|
||||
ADC_WINDOW_B_CHANNEL_8,
|
||||
ADC_WINDOW_B_CHANNEL_9,
|
||||
ADC_WINDOW_B_CHANNEL_10,
|
||||
ADC_WINDOW_B_CHANNEL_11,
|
||||
ADC_WINDOW_B_CHANNEL_12,
|
||||
ADC_WINDOW_B_CHANNEL_13,
|
||||
ADC_WINDOW_B_CHANNEL_14,
|
||||
ADC_WINDOW_B_CHANNEL_15,
|
||||
ADC_WINDOW_B_CHANNEL_16,
|
||||
ADC_WINDOW_B_CHANNEL_17,
|
||||
ADC_WINDOW_B_CHANNEL_18,
|
||||
ADC_WINDOW_B_CHANNEL_19,
|
||||
ADC_WINDOW_B_CHANNEL_20,
|
||||
ADC_WINDOW_B_CHANNEL_21,
|
||||
ADC_WINDOW_B_CHANNEL_22,
|
||||
ADC_WINDOW_B_CHANNEL_23,
|
||||
ADC_WINDOW_B_CHANNEL_24,
|
||||
ADC_WINDOW_B_CHANNEL_25,
|
||||
ADC_WINDOW_B_CHANNEL_26,
|
||||
ADC_WINDOW_B_CHANNEL_27,
|
||||
ADC_WINDOW_B_CHANNEL_TEMPERATURE = 32,
|
||||
ADC_WINDOW_B_CHANNEL_VOLT = 33,
|
||||
} adc_window_b_channel_t;
|
||||
|
||||
/** ADC Window B comparison mode */
|
||||
typedef enum e_adc_window_b_mode
|
||||
{
|
||||
ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE = 0,
|
||||
ADC_WINDOW_B_MODE_GREATER_THAN_OR_INSIDE = R_ADC0_ADCMPBNSR_CMPLB_Msk,
|
||||
} adc_window_b_mode_t;
|
||||
|
||||
/** ADC action for group A interrupts group B scan.
|
||||
* This enumeration is used to specify the priority between Group A and B in group mode. */
|
||||
typedef enum e_adc_group_a
|
||||
{
|
||||
ADC_GROUP_A_PRIORITY_OFF = 0, ///< Group A ignored and does not interrupt ongoing group B scan
|
||||
ADC_GROUP_A_GROUP_B_WAIT_FOR_TRIGGER = 1, ///< Group A interrupts Group B(single scan) which restarts at next Group B trigger
|
||||
ADC_GROUP_A_GROUP_B_RESTART_SCAN = 3, ///< Group A interrupts Group B(single scan) which restarts immediately after Group A scan is complete
|
||||
ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN = 0x8001, ///< Group A interrupts Group B(continuous scan) which continues scanning without a new Group B trigger
|
||||
} adc_group_a_t;
|
||||
|
||||
/** ADC double-trigger mode definitions */
|
||||
typedef enum e_adc_double_trigger
|
||||
{
|
||||
ADC_DOUBLE_TRIGGER_DISABLED = 0, ///< Double-triggering disabled
|
||||
ADC_DOUBLE_TRIGGER_ENABLED = 1, ///< Double-triggering enabled
|
||||
ADC_DOUBLE_TRIGGER_ENABLED_EXTENDED = 2, ///< Double-triggering enabled on both ADC ELC events
|
||||
} adc_double_trigger_t;
|
||||
|
||||
/** ADC sample state configuration */
|
||||
typedef struct st_adc_sample_state
|
||||
{
|
||||
adc_sample_state_reg_t reg_id; ///< Sample state register ID
|
||||
uint8_t num_states; ///< Number of sampling states for conversion. Ch16-20/21 use the same value.
|
||||
} adc_sample_state_t;
|
||||
|
||||
/** ADC Window Compare configuration */
|
||||
typedef struct st_adc_window_cfg
|
||||
{
|
||||
uint32_t compare_mask; ///< Channel mask to compare with Window A
|
||||
uint32_t compare_mode_mask; ///< Per-channel condition mask for Window A
|
||||
adc_compare_cfg_t compare_cfg; ///< Window Compare configuration
|
||||
uint16_t compare_ref_low; ///< Window A lower reference value
|
||||
uint16_t compare_ref_high; ///< Window A upper reference value
|
||||
uint16_t compare_b_ref_low; ///< Window B lower reference value
|
||||
uint16_t compare_b_ref_high; ///< Window A upper reference value
|
||||
adc_window_b_channel_t compare_b_channel; ///< Window B channel
|
||||
adc_window_b_mode_t compare_b_mode; ///< Window B condition setting
|
||||
} adc_window_cfg_t;
|
||||
|
||||
/** Extended configuration structure for ADC. */
|
||||
typedef struct st_adc_extended_cfg
|
||||
{
|
||||
adc_add_t add_average_count; ///< Add or average samples
|
||||
adc_clear_t clearing; ///< Clear after read
|
||||
adc_trigger_t trigger_group_b; ///< Group B trigger source; valid only for group mode
|
||||
adc_double_trigger_t double_trigger_mode; ///< Double-trigger mode setting
|
||||
adc_vref_control_t adc_vref_control; ///< VREFADC output voltage control
|
||||
uint8_t enable_adbuf; ///< Enable ADC Ring Buffer, Valid only to use along with DMAC transfer
|
||||
IRQn_Type window_a_irq; ///< IRQ number for Window Compare A interrupts
|
||||
IRQn_Type window_b_irq; ///< IRQ number for Window Compare B interrupts
|
||||
uint8_t window_a_ipl; ///< Priority for Window Compare A interrupts
|
||||
uint8_t window_b_ipl; ///< Priority for Window Compare B interrupts
|
||||
} adc_extended_cfg_t;
|
||||
|
||||
/** ADC channel(s) configuration */
|
||||
typedef struct st_adc_channel_cfg
|
||||
{
|
||||
uint32_t scan_mask; ///< Channels/bits: bit 0 is ch0; bit 15 is ch15.
|
||||
uint32_t scan_mask_group_b; ///< Valid for group modes.
|
||||
uint32_t add_mask; ///< Valid if add enabled in Open().
|
||||
adc_window_cfg_t * p_window_cfg; ///< Pointer to Window Compare configuration
|
||||
adc_group_a_t priority_group_a; ///< Valid for group modes.
|
||||
uint8_t sample_hold_mask; ///< Channels/bits 0-2.
|
||||
uint8_t sample_hold_states; ///< Number of states to be used for sample and hold. Affects channels 0-2.
|
||||
} adc_channel_cfg_t;
|
||||
|
||||
/* Sample and hold Channel mask. Sample and hold is only available for channel 0,1,2*/
|
||||
#define ADC_SAMPLE_HOLD_CHANNELS (0x07U)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** ADC instance control block. DO NOT INITIALIZE. Initialized in @ref adc_api_t::open(). */
|
||||
typedef struct
|
||||
{
|
||||
R_ADC0_Type * p_reg; // Base register for this unit
|
||||
adc_cfg_t const * p_cfg;
|
||||
uint32_t opened; // Boolean to verify that the Unit has been initialized
|
||||
uint32_t initialized; // Initialized status of ADC
|
||||
uint32_t scan_mask; // Scan mask used for Normal scan
|
||||
uint16_t scan_start_adcsr;
|
||||
|
||||
void (* p_callback)(adc_callback_args_t *); // Pointer to callback that is called when an adc_event_t occurs.
|
||||
adc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
|
||||
|
||||
/* Pointer to context to be passed into callback function */
|
||||
void const * p_context;
|
||||
} adc_instance_ctrl_t;
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** @cond INC_HEADER_DEFS_SEC */
|
||||
/** Interface Structure for user access */
|
||||
extern const adc_api_t g_adc_on_adc;
|
||||
|
||||
/** @endcond */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Public APIs
|
||||
**********************************************************************************************************************/
|
||||
fsp_err_t R_ADC_Open(adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg);
|
||||
fsp_err_t R_ADC_ScanCfg(adc_ctrl_t * p_ctrl, void const * const p_channel_cfg);
|
||||
fsp_err_t R_ADC_InfoGet(adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info);
|
||||
fsp_err_t R_ADC_ScanStart(adc_ctrl_t * p_ctrl);
|
||||
fsp_err_t R_ADC_ScanGroupStart(adc_ctrl_t * p_ctrl, adc_group_mask_t group_id);
|
||||
fsp_err_t R_ADC_ScanStop(adc_ctrl_t * p_ctrl);
|
||||
fsp_err_t R_ADC_StatusGet(adc_ctrl_t * p_ctrl, adc_status_t * p_status);
|
||||
fsp_err_t R_ADC_Read(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data);
|
||||
fsp_err_t R_ADC_Read32(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data);
|
||||
fsp_err_t R_ADC_SampleStateCountSet(adc_ctrl_t * p_ctrl, adc_sample_state_t * p_sample);
|
||||
fsp_err_t R_ADC_Close(adc_ctrl_t * p_ctrl);
|
||||
fsp_err_t R_ADC_OffsetSet(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset);
|
||||
fsp_err_t R_ADC_Calibrate(adc_ctrl_t * const p_ctrl, void const * p_extend);
|
||||
fsp_err_t R_ADC_CallbackSet(adc_ctrl_t * const p_api_ctrl,
|
||||
void ( * p_callback)(adc_callback_args_t *),
|
||||
void const * const p_context,
|
||||
adc_callback_args_t * const p_callback_memory);
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup ADC)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
438
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_gpt.h
Normal file
438
bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_gpt.h
Normal file
@ -0,0 +1,438 @@
|
||||
/***********************************************************************************************************************
|
||||
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef R_GPT_H
|
||||
#define R_GPT_H
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @addtogroup GPT
|
||||
* @{
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Includes
|
||||
**********************************************************************************************************************/
|
||||
#include "bsp_api.h"
|
||||
#include "r_timer_api.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Macro definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Typedef definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */
|
||||
typedef enum e_gpt_io_pin
|
||||
{
|
||||
GPT_IO_PIN_GTIOCA = 0, ///< GTIOCA
|
||||
GPT_IO_PIN_GTIOCB = 1, ///< GTIOCB
|
||||
GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2, ///< GTIOCA and GTIOCB
|
||||
GPT_IO_PIN_TROUGH = 4, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected.
|
||||
GPT_IO_PIN_CREST = 8, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected.
|
||||
} gpt_io_pin_t;
|
||||
|
||||
/** Level of GPT pin */
|
||||
typedef enum e_gpt_pin_level
|
||||
{
|
||||
GPT_PIN_LEVEL_LOW = 0, ///< Pin level low
|
||||
GPT_PIN_LEVEL_HIGH = 1, ///< Pin level high
|
||||
} gpt_pin_level_t;
|
||||
|
||||
/** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent
|
||||
* a bitmask. Multiple sources can be ORed together. */
|
||||
typedef enum e_gpt_source
|
||||
{
|
||||
/** No active event sources. */
|
||||
GPT_SOURCE_NONE = 0U,
|
||||
|
||||
/** Action performed on GTETRGA rising edge. **/
|
||||
GPT_SOURCE_GTETRGA_RISING = (1U << 0),
|
||||
|
||||
/** Action performed on GTETRGA falling edge. **/
|
||||
GPT_SOURCE_GTETRGA_FALLING = (1U << 1),
|
||||
|
||||
/** Action performed on GTETRGB rising edge. **/
|
||||
GPT_SOURCE_GTETRGB_RISING = (1U << 2),
|
||||
|
||||
/** Action performed on GTETRGB falling edge. **/
|
||||
GPT_SOURCE_GTETRGB_FALLING = (1U << 3),
|
||||
|
||||
/** Action performed on GTETRGC rising edge. **/
|
||||
GPT_SOURCE_GTETRGC_RISING = (1U << 4),
|
||||
|
||||
/** Action performed on GTETRGC falling edge. **/
|
||||
GPT_SOURCE_GTETRGC_FALLING = (1U << 5),
|
||||
|
||||
/** Action performed on GTETRGB rising edge. **/
|
||||
GPT_SOURCE_GTETRGD_RISING = (1U << 6),
|
||||
|
||||
/** Action performed on GTETRGB falling edge. **/
|
||||
GPT_SOURCE_GTETRGD_FALLING = (1U << 7),
|
||||
|
||||
/** Action performed when GTIOCA input rises while GTIOCB is low. **/
|
||||
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8),
|
||||
|
||||
/** Action performed when GTIOCA input rises while GTIOCB is high. **/
|
||||
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9),
|
||||
|
||||
/** Action performed when GTIOCA input falls while GTIOCB is low. **/
|
||||
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10),
|
||||
|
||||
/** Action performed when GTIOCA input falls while GTIOCB is high. **/
|
||||
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11),
|
||||
|
||||
/** Action performed when GTIOCB input rises while GTIOCA is low. **/
|
||||
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12),
|
||||
|
||||
/** Action performed when GTIOCB input rises while GTIOCA is high. **/
|
||||
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13),
|
||||
|
||||
/** Action performed when GTIOCB input falls while GTIOCA is low. **/
|
||||
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14),
|
||||
|
||||
/** Action performed when GTIOCB input falls while GTIOCA is high. **/
|
||||
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15),
|
||||
|
||||
/** Action performed on ELC GPTA event. **/
|
||||
GPT_SOURCE_GPT_A = (1U << 16),
|
||||
|
||||
/** Action performed on ELC GPTB event. **/
|
||||
GPT_SOURCE_GPT_B = (1U << 17),
|
||||
|
||||
/** Action performed on ELC GPTC event. **/
|
||||
GPT_SOURCE_GPT_C = (1U << 18),
|
||||
|
||||
/** Action performed on ELC GPTD event. **/
|
||||
GPT_SOURCE_GPT_D = (1U << 19),
|
||||
|
||||
/** Action performed on ELC GPTE event. **/
|
||||
GPT_SOURCE_GPT_E = (1U << 20),
|
||||
|
||||
/** Action performed on ELC GPTF event. **/
|
||||
GPT_SOURCE_GPT_F = (1U << 21),
|
||||
|
||||
/** Action performed on ELC GPTG event. **/
|
||||
GPT_SOURCE_GPT_G = (1U << 22),
|
||||
|
||||
/** Action performed on ELC GPTH event. **/
|
||||
GPT_SOURCE_GPT_H = (1U << 23),
|
||||
} gpt_source_t;
|
||||
|
||||
/** Configurations for output pins. */
|
||||
typedef struct s_gpt_output_pin
|
||||
{
|
||||
bool output_enabled; ///< Set to true to enable output, false to disable output
|
||||
gpt_pin_level_t stop_level; ///< Select a stop level from ::gpt_pin_level_t
|
||||
} gpt_output_pin_t;
|
||||
|
||||
/** Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. */
|
||||
typedef struct s_gpt_gtior_setting
|
||||
{
|
||||
union
|
||||
{
|
||||
uint32_t gtior;
|
||||
struct
|
||||
{
|
||||
/* Settings for GTIOCxA pin. */
|
||||
uint32_t gtioa : 5; ///< GTIOCA Pin Function Select.
|
||||
uint32_t : 1; // Reserved
|
||||
uint32_t oadflt : 1; ///< GTIOCA Pin Output Value Setting at the Count Stop.
|
||||
uint32_t oahld : 1; ///< GTIOCA Pin Output Setting at the Start/Stop Count.
|
||||
uint32_t oae : 1; ///< GTIOCA Pin Output Enable
|
||||
uint32_t oadf : 2; ///< GTIOCA Pin Disable Value Setting.
|
||||
uint32_t : 2; /// Reserved
|
||||
uint32_t nfaen : 1; /// Noise Filter A Enable.
|
||||
uint32_t nfcsa : 2; /// Noise Filter A Sampling Clock Select.
|
||||
|
||||
/* Settings for GTIOCxB pin. */
|
||||
uint32_t gtiob : 5; ///< GTIOCB Pin Function Select.
|
||||
uint32_t : 1; // Reserved
|
||||
uint32_t obdflt : 1; ///< GTIOCB Pin Output Value Setting at the Count Stop.
|
||||
uint32_t obhld : 1; ///< GTIOCB Pin Output Setting at the Start/Stop Count.
|
||||
uint32_t obe : 1; ///< GTIOCB Pin Output Enable
|
||||
uint32_t obdf : 2; ///< GTIOCB Pin Disable Value Setting.
|
||||
uint32_t : 2; /// Reserved
|
||||
uint32_t nfben : 1; /// Noise Filter B Enable.
|
||||
uint32_t nfcsb : 2; /// Noise Filter B Sampling Clock Select.
|
||||
} gtior_b;
|
||||
};
|
||||
} gpt_gtior_setting_t;
|
||||
|
||||
/** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB.
|
||||
* The noise filter samples the external signal at intervals of the PCLK divided by one of the values.
|
||||
* When 3 consecutive samples are at the same level (high or low), then that level is passed on as
|
||||
* the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section.
|
||||
*/
|
||||
typedef enum e_gpt_capture_filter
|
||||
{
|
||||
GPT_CAPTURE_FILTER_NONE = 0U, ///< None - no filtering
|
||||
GPT_CAPTURE_FILTER_PCLKD_DIV_1 = 1U, ///< PCLK/1 - fast sampling
|
||||
GPT_CAPTURE_FILTER_PCLKD_DIV_4 = 3U, ///< PCLK/4
|
||||
GPT_CAPTURE_FILTER_PCLKD_DIV_16 = 5U, ///< PCLK/16
|
||||
GPT_CAPTURE_FILTER_PCLKD_DIV_64 = 7U, ///< PCLK/64 - slow sampling
|
||||
} gpt_capture_filter_t;
|
||||
|
||||
/** Trigger options to start A/D conversion. */
|
||||
typedef enum e_gpt_adc_trigger
|
||||
{
|
||||
GPT_ADC_TRIGGER_NONE = 0U, ///< None - no output disable request
|
||||
GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match
|
||||
GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match
|
||||
GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match
|
||||
GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match
|
||||
} gpt_adc_trigger_t;
|
||||
|
||||
/** POEG channel to link to this channel. */
|
||||
typedef enum e_gpt_poeg_link
|
||||
{
|
||||
GPT_POEG_LINK_POEG0 = 0U, ///< Link this GPT channel to POEG channel 0 (GTETRGA)
|
||||
GPT_POEG_LINK_POEG1 = 1U, ///< Link this GPT channel to POEG channel 1 (GTETRGB)
|
||||
GPT_POEG_LINK_POEG2 = 2U, ///< Link this GPT channel to POEG channel 2 (GTETRGC)
|
||||
GPT_POEG_LINK_POEG3 = 3U, ///< Link this GPT channel to POEG channel 3 (GTETRGD)
|
||||
} gpt_poeg_link_t;
|
||||
|
||||
/** Select trigger to send output disable request to POEG. */
|
||||
typedef enum e_gpt_output_disable
|
||||
{
|
||||
GPT_OUTPUT_DISABLE_NONE = 0U, ///< None - no output disable request
|
||||
GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR = 1U << 0, ///< Request output disable if a dead time error occurs
|
||||
GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time
|
||||
GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time
|
||||
} gpt_output_disable_t;
|
||||
|
||||
/** Disable level options for GTIOC pins. */
|
||||
typedef enum e_gpt_gtioc_disable
|
||||
{
|
||||
GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable
|
||||
GPT_GTIOC_DISABLE_SET_HI_Z = 1U, ///< Set GTIOC to high impedance when output is disabled
|
||||
GPT_GTIOC_DISABLE_LEVEL_LOW = 2U, ///< Set GTIOC level low when output is disabled
|
||||
GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled
|
||||
} gpt_gtioc_disable_t;
|
||||
|
||||
/** Trigger options to start A/D conversion. */
|
||||
typedef enum e_gpt_adc_compare_match
|
||||
{
|
||||
GPT_ADC_COMPARE_MATCH_ADC_A = 0U, ///< Set A/D conversion start request value for GPT A/D converter start request A
|
||||
GPT_ADC_COMPARE_MATCH_ADC_B = 3U, ///< Set A/D conversion start request value for GPT A/D converter start request B
|
||||
} gpt_adc_compare_match_t;
|
||||
|
||||
/** Interrupt skipping modes */
|
||||
typedef enum e_gpt_interrupt_skip_source
|
||||
{
|
||||
GPT_INTERRUPT_SKIP_SOURCE_NONE = 0U, ///< Do not skip interrupts
|
||||
GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts
|
||||
|
||||
/** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in
|
||||
* @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest
|
||||
* interrupt. */
|
||||
GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U,
|
||||
|
||||
/** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in
|
||||
* @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough
|
||||
* interrupt. */
|
||||
GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U,
|
||||
} gpt_interrupt_skip_source_t;
|
||||
|
||||
/** Number of interrupts to skip between events */
|
||||
typedef enum e_gpt_interrupt_skip_count
|
||||
{
|
||||
GPT_INTERRUPT_SKIP_COUNT_0 = 0U, ///< Do not skip interrupts
|
||||
GPT_INTERRUPT_SKIP_COUNT_1, ///< Skip one interrupt
|
||||
GPT_INTERRUPT_SKIP_COUNT_2, ///< Skip two interrupts
|
||||
GPT_INTERRUPT_SKIP_COUNT_3, ///< Skip three interrupts
|
||||
GPT_INTERRUPT_SKIP_COUNT_4, ///< Skip four interrupts
|
||||
GPT_INTERRUPT_SKIP_COUNT_5, ///< Skip five interrupts
|
||||
GPT_INTERRUPT_SKIP_COUNT_6, ///< Skip six interrupts
|
||||
GPT_INTERRUPT_SKIP_COUNT_7, ///< Skip seven interrupts
|
||||
} gpt_interrupt_skip_count_t;
|
||||
|
||||
/** ADC events to skip during interrupt skipping */
|
||||
typedef enum e_gpt_interrupt_skip_adc
|
||||
{
|
||||
GPT_INTERRUPT_SKIP_ADC_NONE = 0U, ///< Do not skip ADC events
|
||||
GPT_INTERRUPT_SKIP_ADC_A = 1U, ///< Skip ADC A events
|
||||
GPT_INTERRUPT_SKIP_ADC_B = 4U, ///< Skip ADC B events
|
||||
GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events
|
||||
} gpt_interrupt_skip_adc_t;
|
||||
|
||||
/** Delay setting for the PWM Delay Generation Circuit (PDG). */
|
||||
typedef enum e_gpt_pwm_output_delay_setting
|
||||
{
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_0_32, ///< Delay is not applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_1_32, ///< Delay of 1 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_2_32, ///< Delay of 2 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_3_32, ///< Delay of 3 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_4_32, ///< Delay of 4 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_5_32, ///< Delay of 5 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_6_32, ///< Delay of 6 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_7_32, ///< Delay of 7 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_8_32, ///< Delay of 8 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_9_32, ///< Delay of 9 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_10_32, ///< Delay of 10 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_11_32, ///< Delay of 11 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_12_32, ///< Delay of 12 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_13_32, ///< Delay of 13 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_14_32, ///< Delay of 14 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_15_32, ///< Delay of 15 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_16_32, ///< Delay of 16 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_17_32, ///< Delay of 17 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_18_32, ///< Delay of 18 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_19_32, ///< Delay of 19 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_20_32, ///< Delay of 20 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_21_32, ///< Delay of 21 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_22_32, ///< Delay of 22 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_23_32, ///< Delay of 23 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_24_32, ///< Delay of 24 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_25_32, ///< Delay of 25 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_26_32, ///< Delay of 26 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_27_32, ///< Delay of 27 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_28_32, ///< Delay of 28 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_29_32, ///< Delay of 29 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_30_32, ///< Delay of 30 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_31_32, ///< Delay of 31 / 32 GTCLK period applied.
|
||||
GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS, ///< Bypass the PWM Output Delay Circuit.
|
||||
} gpt_pwm_output_delay_setting_t;
|
||||
|
||||
/** Select which PWM Output Delay setting to apply. */
|
||||
typedef enum e_gpt_pwm_output_delay_edge
|
||||
{
|
||||
GPT_PWM_OUTPUT_DELAY_EDGE_RISING, ///< Configure the PWM Output Delay setting for rising edge.
|
||||
GPT_PWM_OUTPUT_DELAY_EDGE_FALLING, ///< Configure the PWM Output Delay setting for falling edge.
|
||||
} gpt_pwm_output_delay_edge_t;
|
||||
|
||||
/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */
|
||||
typedef struct st_gpt_instance_ctrl
|
||||
{
|
||||
uint32_t open; // Whether or not channel is open
|
||||
const timer_cfg_t * p_cfg; // Pointer to initial configurations
|
||||
R_GPT0_Type * p_reg; // Base register for this channel
|
||||
uint32_t channel_mask; // Channel bitmask
|
||||
timer_variant_t variant; // Timer variant
|
||||
|
||||
void (* p_callback)(timer_callback_args_t *); // Pointer to callback
|
||||
timer_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory
|
||||
void const * p_context; // Pointer to context to be passed into callback function
|
||||
} gpt_instance_ctrl_t;
|
||||
|
||||
/** GPT extension for advanced PWM features. */
|
||||
typedef struct st_gpt_extended_pwm_cfg
|
||||
{
|
||||
uint8_t trough_ipl; ///< Trough interrupt priority
|
||||
IRQn_Type trough_irq; ///< Trough interrupt
|
||||
gpt_poeg_link_t poeg_link; ///< Select which POEG channel controls output disable for this GPT channel
|
||||
gpt_output_disable_t output_disable; ///< Select which trigger sources request output disable from POEG
|
||||
gpt_adc_trigger_t adc_trigger; ///< Select trigger sources to start A/D conversion
|
||||
uint32_t dead_time_count_up; ///< Set a dead time value for counting up
|
||||
uint32_t dead_time_count_down; ///< Set a dead time value for counting down (available on GPT32E and GPT32EH only)
|
||||
uint32_t adc_a_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_A
|
||||
uint32_t adc_b_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_B
|
||||
gpt_interrupt_skip_source_t interrupt_skip_source; ///< Interrupt source to count for interrupt skipping
|
||||
gpt_interrupt_skip_count_t interrupt_skip_count; ///< Number of interrupts to skip between events
|
||||
gpt_interrupt_skip_adc_t interrupt_skip_adc; ///< ADC events to skip when interrupt skipping is enabled
|
||||
gpt_gtioc_disable_t gtioca_disable_setting; ///< DEPRECATED - Select how to configure GTIOCA when output is disabled
|
||||
gpt_gtioc_disable_t gtiocb_disable_setting; ///< DEPRECATED - Select how to configure GTIOCB when output is disabled
|
||||
} gpt_extended_pwm_cfg_t;
|
||||
|
||||
/** GPT extension configures the output pins for GPT. */
|
||||
typedef struct st_gpt_extended_cfg
|
||||
{
|
||||
gpt_output_pin_t gtioca; ///< DEPRECATED - Configuration for GPT I/O pin A
|
||||
gpt_output_pin_t gtiocb; ///< DEPRECATED - Configuration for GPT I/O pin B
|
||||
gpt_source_t start_source; ///< Event sources that trigger the timer to start
|
||||
gpt_source_t stop_source; ///< Event sources that trigger the timer to stop
|
||||
gpt_source_t clear_source; ///< Event sources that trigger the timer to clear
|
||||
gpt_source_t capture_a_source; ///< Event sources that trigger capture of GTIOCA
|
||||
gpt_source_t capture_b_source; ///< Event sources that trigger capture of GTIOCB
|
||||
|
||||
/** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source
|
||||
* and count_down_source, then the timer count source is PCLK. */
|
||||
gpt_source_t count_up_source;
|
||||
|
||||
/** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source
|
||||
* and count_down_source, then the timer count source is PCLK. */
|
||||
gpt_source_t count_down_source;
|
||||
|
||||
/* Debounce filter for GTIOCxA input signal pin (DEPRECATED). */
|
||||
gpt_capture_filter_t capture_filter_gtioca;
|
||||
|
||||
/* Debounce filter for GTIOCxB input signal pin (DEPRECATED). */
|
||||
gpt_capture_filter_t capture_filter_gtiocb;
|
||||
|
||||
uint8_t capture_a_ipl; ///< Capture A interrupt priority
|
||||
uint8_t capture_b_ipl; ///< Capture B interrupt priority
|
||||
IRQn_Type capture_a_irq; ///< Capture A interrupt
|
||||
IRQn_Type capture_b_irq; ///< Capture B interrupt
|
||||
gpt_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional
|
||||
gpt_gtior_setting_t gtior_setting; ///< Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins.
|
||||
} gpt_extended_cfg_t;
|
||||
|
||||
/**********************************************************************************************************************
|
||||
* Exported global variables
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/** @cond INC_HEADER_DEFS_SEC */
|
||||
/** Filled in Interface API structure for this Instance. */
|
||||
extern const timer_api_t g_timer_on_gpt;
|
||||
|
||||
/** @endcond */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Public APIs
|
||||
**********************************************************************************************************************/
|
||||
fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
|
||||
fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts);
|
||||
fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
|
||||
fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
|
||||
fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
|
||||
fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter);
|
||||
fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin);
|
||||
fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin);
|
||||
fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const p_ctrl,
|
||||
gpt_adc_compare_match_t which_compare_match,
|
||||
uint32_t compare_match_value);
|
||||
fsp_err_t R_GPT_PwmOutputDelaySet(timer_ctrl_t * const p_ctrl,
|
||||
gpt_pwm_output_delay_edge_t edge,
|
||||
gpt_pwm_output_delay_setting_t delay_setting,
|
||||
uint32_t const pin);
|
||||
fsp_err_t R_GPT_CallbackSet(timer_ctrl_t * const p_api_ctrl,
|
||||
void ( * p_callback)(timer_callback_args_t *),
|
||||
void const * const p_context,
|
||||
timer_callback_args_t * const p_callback_memory);
|
||||
fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl);
|
||||
fsp_err_t R_GPT_PwmOutputDelayInitialize();
|
||||
|
||||
/*******************************************************************************************************************//**
|
||||
* @} (end defgroup GPT)
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif
|
||||
1802
bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_adc/r_adc.c
Normal file
1802
bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_adc/r_adc.c
Normal file
File diff suppressed because it is too large
Load Diff
1830
bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_gpt/r_gpt.c
Normal file
1830
bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_gpt/r_gpt.c
Normal file
File diff suppressed because it is too large
Load Diff
5
bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_adc_cfg.h
Normal file
5
bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_adc_cfg.h
Normal file
@ -0,0 +1,5 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef R_ADC_CFG_H_
|
||||
#define R_ADC_CFG_H_
|
||||
#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
|
||||
#endif /* R_ADC_CFG_H_ */
|
||||
8
bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_gpt_cfg.h
Normal file
8
bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_gpt_cfg.h
Normal file
@ -0,0 +1,8 @@
|
||||
/* generated configuration header file - do not edit */
|
||||
#ifndef R_GPT_CFG_H_
|
||||
#define R_GPT_CFG_H_
|
||||
#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
|
||||
#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (1)
|
||||
#define GPT_CFG_WRITE_PROTECT_ENABLE (0)
|
||||
#define GPT_CFG_GPTCLK_BYPASS 1
|
||||
#endif /* R_GPT_CFG_H_ */
|
||||
@ -1,5 +1,279 @@
|
||||
/* generated HAL source file - do not edit */
|
||||
#include "hal_data.h"
|
||||
|
||||
/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
|
||||
#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
|
||||
#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
|
||||
#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
|
||||
#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
|
||||
gpt_instance_ctrl_t g_timer2_ctrl;
|
||||
#if 0
|
||||
const gpt_extended_pwm_cfg_t g_timer2_pwm_extend =
|
||||
{
|
||||
.trough_ipl = (BSP_IRQ_DISABLED),
|
||||
#if defined(VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW)
|
||||
.trough_irq = VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW,
|
||||
#else
|
||||
.trough_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.poeg_link = GPT_POEG_LINK_POEG0,
|
||||
.output_disable = GPT_OUTPUT_DISABLE_NONE,
|
||||
.adc_trigger = GPT_ADC_TRIGGER_NONE,
|
||||
.dead_time_count_up = 0,
|
||||
.dead_time_count_down = 0,
|
||||
.adc_a_compare_match = 0,
|
||||
.adc_b_compare_match = 0,
|
||||
.interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE,
|
||||
.interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0,
|
||||
.interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE,
|
||||
.gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
|
||||
.gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
|
||||
};
|
||||
#endif
|
||||
const gpt_extended_cfg_t g_timer2_extend =
|
||||
{
|
||||
.gtioca = { .output_enabled = false,
|
||||
.stop_level = GPT_PIN_LEVEL_LOW
|
||||
},
|
||||
.gtiocb = { .output_enabled = true,
|
||||
.stop_level = GPT_PIN_LEVEL_LOW
|
||||
},
|
||||
.start_source = (gpt_source_t) ( GPT_SOURCE_NONE),
|
||||
.stop_source = (gpt_source_t) ( GPT_SOURCE_NONE),
|
||||
.clear_source = (gpt_source_t) ( GPT_SOURCE_NONE),
|
||||
.count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE),
|
||||
.count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE),
|
||||
.capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE),
|
||||
.capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE),
|
||||
.capture_a_ipl = (BSP_IRQ_DISABLED),
|
||||
.capture_b_ipl = (BSP_IRQ_DISABLED),
|
||||
#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A)
|
||||
.capture_a_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A,
|
||||
#else
|
||||
.capture_a_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B)
|
||||
.capture_b_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B,
|
||||
#else
|
||||
.capture_b_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE,
|
||||
.capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE,
|
||||
#if 0
|
||||
.p_pwm_cfg = &g_timer2_pwm_extend,
|
||||
#else
|
||||
.p_pwm_cfg = NULL,
|
||||
#endif
|
||||
#if 0
|
||||
.gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U),
|
||||
.gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW,
|
||||
.gtior_setting.gtior_b.oahld = 0U,
|
||||
.gtior_setting.gtior_b.oae = (uint32_t) false,
|
||||
.gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
|
||||
.gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
|
||||
.gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
|
||||
.gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U),
|
||||
.gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW,
|
||||
.gtior_setting.gtior_b.obhld = 0U,
|
||||
.gtior_setting.gtior_b.obe = (uint32_t) true,
|
||||
.gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
|
||||
.gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
|
||||
.gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
|
||||
#else
|
||||
.gtior_setting.gtior = 0U,
|
||||
#endif
|
||||
};
|
||||
const timer_cfg_t g_timer2_cfg =
|
||||
{
|
||||
.mode = TIMER_MODE_PWM,
|
||||
/* Actual period: 35.791394133333334 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = (timer_source_div_t)0,
|
||||
.channel = 2,
|
||||
.p_callback = NULL,
|
||||
/** If NULL then do not add & */
|
||||
#if defined(NULL)
|
||||
.p_context = NULL,
|
||||
#else
|
||||
.p_context = &NULL,
|
||||
#endif
|
||||
.p_extend = &g_timer2_extend,
|
||||
.cycle_end_ipl = (BSP_IRQ_DISABLED),
|
||||
#if defined(VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW)
|
||||
.cycle_end_irq = VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW,
|
||||
#else
|
||||
.cycle_end_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const timer_instance_t g_timer2 =
|
||||
{
|
||||
.p_ctrl = &g_timer2_ctrl,
|
||||
.p_cfg = &g_timer2_cfg,
|
||||
.p_api = &g_timer_on_gpt
|
||||
};
|
||||
sci_uart_instance_ctrl_t g_uart4_ctrl;
|
||||
|
||||
baud_setting_t g_uart4_baud_setting =
|
||||
{
|
||||
/* Baud rate calculated with 0.160% error. */ .abcse = 0, .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t) 256, .brme = false
|
||||
};
|
||||
|
||||
/** UART extended configuration for UARTonSCI HAL driver */
|
||||
const sci_uart_extended_cfg_t g_uart4_cfg_extend =
|
||||
{
|
||||
.clock = SCI_UART_CLOCK_INT,
|
||||
.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
|
||||
.noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
|
||||
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
|
||||
.p_baud_setting = &g_uart4_baud_setting,
|
||||
.flow_control = SCI_UART_FLOW_CONTROL_RTS,
|
||||
#if 0xFF != 0xFF
|
||||
.flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
|
||||
#else
|
||||
.flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
|
||||
#endif
|
||||
};
|
||||
|
||||
/** UART interface configuration */
|
||||
const uart_cfg_t g_uart4_cfg =
|
||||
{
|
||||
.channel = 4,
|
||||
.data_bits = UART_DATA_BITS_8,
|
||||
.parity = UART_PARITY_OFF,
|
||||
.stop_bits = UART_STOP_BITS_1,
|
||||
.p_callback = user_uart4_callback,
|
||||
.p_context = NULL,
|
||||
.p_extend = &g_uart4_cfg_extend,
|
||||
#define RA_NOT_DEFINED (1)
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_tx = NULL,
|
||||
#else
|
||||
.p_transfer_tx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
|
||||
.p_transfer_rx = NULL,
|
||||
#else
|
||||
.p_transfer_rx = &RA_NOT_DEFINED,
|
||||
#endif
|
||||
#undef RA_NOT_DEFINED
|
||||
.rxi_ipl = (12),
|
||||
.txi_ipl = (12),
|
||||
.tei_ipl = (12),
|
||||
.eri_ipl = (12),
|
||||
#if defined(VECTOR_NUMBER_SCI4_RXI)
|
||||
.rxi_irq = VECTOR_NUMBER_SCI4_RXI,
|
||||
#else
|
||||
.rxi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI4_TXI)
|
||||
.txi_irq = VECTOR_NUMBER_SCI4_TXI,
|
||||
#else
|
||||
.txi_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI4_TEI)
|
||||
.tei_irq = VECTOR_NUMBER_SCI4_TEI,
|
||||
#else
|
||||
.tei_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
#if defined(VECTOR_NUMBER_SCI4_ERI)
|
||||
.eri_irq = VECTOR_NUMBER_SCI4_ERI,
|
||||
#else
|
||||
.eri_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Instance structure to use this module. */
|
||||
const uart_instance_t g_uart4 =
|
||||
{
|
||||
.p_ctrl = &g_uart4_ctrl,
|
||||
.p_cfg = &g_uart4_cfg,
|
||||
.p_api = &g_uart_on_sci
|
||||
};
|
||||
adc_instance_ctrl_t g_adc0_ctrl;
|
||||
const adc_extended_cfg_t g_adc0_cfg_extend =
|
||||
{
|
||||
.add_average_count = ADC_ADD_OFF,
|
||||
.clearing = ADC_CLEAR_AFTER_READ_ON,
|
||||
.trigger_group_b = ADC_TRIGGER_SYNC_ELC,
|
||||
.double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
|
||||
.adc_vref_control = ADC_VREF_CONTROL_VREFH,
|
||||
.enable_adbuf = 0,
|
||||
#if defined(VECTOR_NUMBER_ADC0_WINDOW_A)
|
||||
.window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A,
|
||||
#else
|
||||
.window_a_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.window_a_ipl = (BSP_IRQ_DISABLED),
|
||||
#if defined(VECTOR_NUMBER_ADC0_WINDOW_B)
|
||||
.window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B,
|
||||
#else
|
||||
.window_b_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.window_b_ipl = (BSP_IRQ_DISABLED),
|
||||
};
|
||||
const adc_cfg_t g_adc0_cfg =
|
||||
{
|
||||
.unit = 0,
|
||||
.mode = ADC_MODE_CONTINUOUS_SCAN,
|
||||
.resolution = ADC_RESOLUTION_12_BIT,
|
||||
.alignment = (adc_alignment_t) ADC_ALIGNMENT_RIGHT,
|
||||
.trigger = ADC_TRIGGER_SOFTWARE,
|
||||
.p_callback = NULL,
|
||||
/** If NULL then do not add & */
|
||||
#if defined(NULL)
|
||||
.p_context = NULL,
|
||||
#else
|
||||
.p_context = &NULL,
|
||||
#endif
|
||||
.p_extend = &g_adc0_cfg_extend,
|
||||
#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
|
||||
.scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
|
||||
#else
|
||||
.scan_end_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.scan_end_ipl = (BSP_IRQ_DISABLED),
|
||||
#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
|
||||
.scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
|
||||
#else
|
||||
.scan_end_b_irq = FSP_INVALID_VECTOR,
|
||||
#endif
|
||||
.scan_end_b_ipl = (BSP_IRQ_DISABLED),
|
||||
};
|
||||
#if ((0) | (0))
|
||||
const adc_window_cfg_t g_adc0_window_cfg =
|
||||
{
|
||||
.compare_mask = 0,
|
||||
.compare_mode_mask = 0,
|
||||
.compare_cfg = (0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR),
|
||||
.compare_ref_low = 0,
|
||||
.compare_ref_high = 0,
|
||||
.compare_b_channel = (ADC_WINDOW_B_CHANNEL_0),
|
||||
.compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE),
|
||||
.compare_b_ref_low = 0,
|
||||
.compare_b_ref_high = 0,
|
||||
};
|
||||
#endif
|
||||
const adc_channel_cfg_t g_adc0_channel_cfg =
|
||||
{
|
||||
.scan_mask = ADC_MASK_CHANNEL_0 | ADC_MASK_CHANNEL_1 | ADC_MASK_CHANNEL_2 | ADC_MASK_CHANNEL_3 | ADC_MASK_CHANNEL_5 | ADC_MASK_CHANNEL_7 | ADC_MASK_CHANNEL_20 | 0,
|
||||
.scan_mask_group_b = 0,
|
||||
.priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
|
||||
.add_mask = 0,
|
||||
.sample_hold_mask = 0,
|
||||
.sample_hold_states = 24,
|
||||
#if ((0) | (0))
|
||||
.p_window_cfg = (adc_window_cfg_t *) &g_adc0_window_cfg,
|
||||
#else
|
||||
.p_window_cfg = NULL,
|
||||
#endif
|
||||
};
|
||||
/* Instance structure to use this module. */
|
||||
const adc_instance_t g_adc0 =
|
||||
{
|
||||
.p_ctrl = &g_adc0_ctrl,
|
||||
.p_cfg = &g_adc0_cfg,
|
||||
.p_channel_cfg = &g_adc0_channel_cfg,
|
||||
.p_api = &g_adc_on_adc
|
||||
};
|
||||
sci_uart_instance_ctrl_t g_uart9_ctrl;
|
||||
|
||||
baud_setting_t g_uart9_baud_setting =
|
||||
|
||||
@ -4,9 +4,49 @@
|
||||
#include <stdint.h>
|
||||
#include "bsp_api.h"
|
||||
#include "common_data.h"
|
||||
#include "r_gpt.h"
|
||||
#include "r_timer_api.h"
|
||||
#include "r_sci_uart.h"
|
||||
#include "r_uart_api.h"
|
||||
#include "r_adc.h"
|
||||
#include "r_adc_api.h"
|
||||
FSP_HEADER
|
||||
/** Timer on GPT Instance. */
|
||||
extern const timer_instance_t g_timer2;
|
||||
|
||||
/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern gpt_instance_ctrl_t g_timer2_ctrl;
|
||||
extern const timer_cfg_t g_timer2_cfg;
|
||||
|
||||
#ifndef NULL
|
||||
void NULL(timer_callback_args_t * p_args);
|
||||
#endif
|
||||
/** UART on SCI Instance. */
|
||||
extern const uart_instance_t g_uart4;
|
||||
|
||||
/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern sci_uart_instance_ctrl_t g_uart4_ctrl;
|
||||
extern const uart_cfg_t g_uart4_cfg;
|
||||
extern const sci_uart_extended_cfg_t g_uart4_cfg_extend;
|
||||
|
||||
#ifndef user_uart4_callback
|
||||
void user_uart4_callback(uart_callback_args_t * p_args);
|
||||
#endif
|
||||
/** ADC on ADC Instance. */
|
||||
extern const adc_instance_t g_adc0;
|
||||
|
||||
/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
|
||||
extern adc_instance_ctrl_t g_adc0_ctrl;
|
||||
extern const adc_cfg_t g_adc0_cfg;
|
||||
extern const adc_channel_cfg_t g_adc0_channel_cfg;
|
||||
|
||||
#ifndef NULL
|
||||
void NULL(adc_callback_args_t * p_args);
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 7
|
||||
#endif
|
||||
/** UART on SCI Instance. */
|
||||
extern const uart_instance_t g_uart9;
|
||||
|
||||
|
||||
@ -4,6 +4,30 @@
|
||||
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_02,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_03,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_00_PIN_14,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_01_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
@ -16,10 +40,26 @@ const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
.pin = BSP_IO_PORT_01_PIN_10,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_05,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_02_PIN_06,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_03_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_05_PIN_08,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
|
||||
},
|
||||
{
|
||||
.pin = BSP_IO_PORT_07_PIN_12,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1)
|
||||
},
|
||||
};
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
|
||||
@ -8,6 +8,10 @@
|
||||
[1] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */
|
||||
[2] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
|
||||
[3] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
|
||||
[4] = sci_uart_rxi_isr, /* SCI4 RXI (Received data full) */
|
||||
[5] = sci_uart_txi_isr, /* SCI4 TXI (Transmit data empty) */
|
||||
[6] = sci_uart_tei_isr, /* SCI4 TEI (Transmit end) */
|
||||
[7] = sci_uart_eri_isr, /* SCI4 ERI (Receive error) */
|
||||
};
|
||||
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
|
||||
{
|
||||
@ -15,5 +19,9 @@
|
||||
[1] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */
|
||||
[2] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */
|
||||
[3] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */
|
||||
[4] = BSP_PRV_IELS_ENUM(EVENT_SCI4_RXI), /* SCI4 RXI (Received data full) */
|
||||
[5] = BSP_PRV_IELS_ENUM(EVENT_SCI4_TXI), /* SCI4 TXI (Transmit data empty) */
|
||||
[6] = BSP_PRV_IELS_ENUM(EVENT_SCI4_TEI), /* SCI4 TEI (Transmit end) */
|
||||
[7] = BSP_PRV_IELS_ENUM(EVENT_SCI4_ERI), /* SCI4 ERI (Receive error) */
|
||||
};
|
||||
#endif
|
||||
@ -3,7 +3,7 @@
|
||||
#define VECTOR_DATA_H
|
||||
/* Number of interrupts allocated */
|
||||
#ifndef VECTOR_DATA_IRQ_COUNT
|
||||
#define VECTOR_DATA_IRQ_COUNT (4)
|
||||
#define VECTOR_DATA_IRQ_COUNT (8)
|
||||
#endif
|
||||
/* ISR prototypes */
|
||||
void sci_uart_rxi_isr(void);
|
||||
@ -20,4 +20,12 @@
|
||||
#define SCI9_TEI_IRQn ((IRQn_Type) 2) /* SCI9 TEI (Transmit end) */
|
||||
#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type) 3) /* SCI9 ERI (Receive error) */
|
||||
#define SCI9_ERI_IRQn ((IRQn_Type) 3) /* SCI9 ERI (Receive error) */
|
||||
#define VECTOR_NUMBER_SCI4_RXI ((IRQn_Type) 4) /* SCI4 RXI (Received data full) */
|
||||
#define SCI4_RXI_IRQn ((IRQn_Type) 4) /* SCI4 RXI (Received data full) */
|
||||
#define VECTOR_NUMBER_SCI4_TXI ((IRQn_Type) 5) /* SCI4 TXI (Transmit data empty) */
|
||||
#define SCI4_TXI_IRQn ((IRQn_Type) 5) /* SCI4 TXI (Transmit data empty) */
|
||||
#define VECTOR_NUMBER_SCI4_TEI ((IRQn_Type) 6) /* SCI4 TEI (Transmit end) */
|
||||
#define SCI4_TEI_IRQn ((IRQn_Type) 6) /* SCI4 TEI (Transmit end) */
|
||||
#define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type) 7) /* SCI4 ERI (Receive error) */
|
||||
#define SCI4_ERI_IRQn ((IRQn_Type) 7) /* SCI4 ERI (Receive error) */
|
||||
#endif /* VECTOR_DATA_H */
|
||||
@ -47,6 +47,7 @@
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart9"
|
||||
#define RT_VER_NUM 0x50100
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
#define RT_USING_HW_ATOMIC
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM
|
||||
@ -84,7 +85,11 @@
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V2
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_ADC
|
||||
#define RT_USING_PWM
|
||||
|
||||
/* Using USB */
|
||||
|
||||
@ -108,6 +113,7 @@
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
#define RT_USING_CPLUSPLUS
|
||||
|
||||
/* Network */
|
||||
|
||||
@ -175,6 +181,8 @@
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
#define PKG_USING_PERF_COUNTER
|
||||
#define PKG_USING_PERF_COUNTER_LATEST_VERSION
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
@ -205,6 +213,14 @@
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
#define PKG_USING_RTDUINO
|
||||
#define RTDUINO_THREAD_SIZE 2048
|
||||
#define RTDUINO_THREAD_PRIO 30
|
||||
#define RTDUINO_SUPPORT_HIGH_PRECISION_MICROS
|
||||
#define RTDUINO_USING_WIRE
|
||||
#define RTDUINO_WIRE_BUFFER_LENGTH 32
|
||||
#define RTDUINO_USING_SERVO
|
||||
#define PKG_USING_RTDUINO_LATEST_VERSION
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
@ -246,13 +262,24 @@
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_ARDUINO
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART4
|
||||
#define BSP_UART4_RX_BUFSIZE 256
|
||||
#define BSP_UART4_TX_BUFSIZE 0
|
||||
#define BSP_USING_UART9
|
||||
#define BSP_UART9_RX_BUFSIZE 256
|
||||
#define BSP_UART9_TX_BUFSIZE 0
|
||||
#define BSP_USING_I2C
|
||||
#define BSP_USING_ADC
|
||||
#define BSP_USING_ADC0
|
||||
#define BSP_USING_PWM
|
||||
#define BSP_USING_PWM2
|
||||
#define BSP_USING_PWM2_CH2
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
|
||||
@ -223,6 +223,14 @@ SECTIONS
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
/* new GCC version uses .init_array */
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
__ROM_End = .;
|
||||
} > FLASH = 0xFF
|
||||
|
||||
@ -327,6 +335,14 @@ SECTIONS
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user