libs/rt-thread-official
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rt-thread-official
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Merge branch 'master' of https://github.com/RT-Thread/rt-thread

This commit is contained in:
bernard 2024-11-10 19:31:50 +08:00
parent 33ab629b84 56c9bbe405
commit eb79397557
907 changed files with 266140 additions and 5839 deletions
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3
.github/PULL_REQUEST_TEMPLATE.md vendored
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@ -61,4 +61,5 @@ The following content must not be changed in the submitted PR message. Otherwise
- [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
- [ ] 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
- [ ] 代码是高质量的 Code in this PR is of high quality
- [ ] 已经使用[formatting](https://github.com/mysterywolf/formatting) 等源码格式化工具确保格式符合[RT-Thread代码规范](https://github.com/RT-Thread/rt-thread/blob/master/documentation/contribution_guide/coding_style_cn.md) This PR complies with [RT-Thread code specification](https://github.com/RT-Thread/rt-thread/blob/master/documentation/contribution_guide/coding_style_en.md)
- [ ] 已经使用[formatting](https://github.com/mysterywolf/formatting) 等源码格式化工具确保格式符合[RT-Thread代码规范](https://github.com/RT-Thread/rt-thread/blob/master/documentation/contribution_guide/coding_style_cn.md) This PR complies with [RT-Thread code specification](https://github.com/RT-Thread/rt-thread/blob/master/documentation/contribution_guide/coding_style_en.md)
- [ ] 如果是新增bsp, 已经添加ci检查到[.github/workflows/bsp_buildings.yml](workflows/bsp_buildings.yml) 详细请参考链接[BSP自查](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/bsp-selfcheck/bsp_selfcheck)

4
.github/workflows/action_tools.yml vendored
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@ -34,7 +34,7 @@ jobs:
test:
runs-on: ubuntu-latest
name: Tools
if: github.repository_owner == 'RT-Thread' && false
if: github.repository_owner == 'RT-Thread'
strategy:
fail-fast: false
env:
@ -77,7 +77,7 @@ jobs:
if: ${{ success() }}
run: |
echo "Test to dist project"
scons --dist -C $TEST_BSP_ROOT
scons --dist --project-name=project -C $TEST_BSP_ROOT
scons --dist-ide -C $TEST_BSP_ROOT
ls $TEST_BSP_ROOT
ls $TEST_BSP_ROOT/dist

45
.github/workflows/bsp_buildings.yml vendored
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@ -93,6 +93,7 @@ jobs:
- "hc32l196"
- "mm32/mm32f3270-100ask-pitaya"
- "mm32f327x"
- "mm32l07x"
- "sam7x"
- "hk32/hk32f030c8-mini"
- "acm32/acm32f0x0-nucleo"
@ -100,6 +101,12 @@ jobs:
- "rm48x50"
- "ht32/ht32f52352"
- "ht32/ht32f12366"
- "w60x"
- "essemi/es32f0654"
- "essemi/es32f365x"
- "hc32l136"
- "yichip/yc3121-pos"
- "fm33lc026"
- RTT_BSP: "stm32l4_f0_f1"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:
@ -208,8 +215,8 @@ jobs:
- "nxp/lpc/lpc1114"
- "nxp/lpc/lpc2148"
- "nxp/lpc/lpc2478"
# - "nxp/lpc/lpc5410x"
# - "nxp/lpc/lpc54114-lite"
- "nxp/lpc/lpc5410x"
- "nxp/lpc/lpc54114-lite"
- "nxp/lpc/lpc176x"
#- "nxp/lpc/lpc43xx/M4"
- "nxp/imx/imx6sx/cortex-a9"
@ -228,6 +235,7 @@ jobs:
- "renesas/ra6m4-iot"
- "renesas/ra6m3-ek"
- "renesas/ra6m3-hmi-board"
- "renesas/ra6e2-fpb"
- "renesas/ra4m2-eco"
- "renesas/ra2l1-cpk"
- "renesas/ra8m1-ek"
@ -237,6 +245,21 @@ jobs:
- "renesas/rzn2l_rsk"
- "frdm-k64f"
- "xplorer4330/M4"
- RTT_BSP: "nuvoton"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:
- "nuvoton/numaker-pfm-m487"
- "nuvoton/numaker-hmi-ma35d1"
- "nuvoton/numaker-iot-m487"
- "nuvoton/numaker-m032ki"
- "nuvoton/numaker-iot-m467"
- "nuvoton/numaker-m467hj"
- "nuvoton/nk-n9h30"
- "nuvoton/nk-rtu980"
- "nuvoton/ma35-rtp"
- "nuvoton/nk-980iot"
- "nuvoton/numaker-iot-ma35d1"
- "nuvoton/numaker-m2354"
- RTT_BSP: "gd32_n32_apm32"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:
@ -255,6 +278,7 @@ jobs:
- "gd32/arm/gd32450z-eval"
- "gd32/arm/gd32470z-lckfb"
- "gd32/arm/gd32h759i-start"
- "gd32/arm/gd32e503v-eval"
- "n32/n32g43xcl-stb"
- "n32/n32g45xcl-stb"
- "n32/n32g45xml-stb"
@ -279,14 +303,9 @@ jobs:
- "apm32/apm32e103ze-evalboard"
- "apm32/apm32e103ze-tinyboard"
- "apm32/apm32s103vb-miniboard"
- RTT_BSP: "nordic_Infineon_TI_microchip"
- RTT_BSP: "Infineon_TI_microchip"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:
- "nrf5x/nrf51822"
- "nrf5x/nrf52832"
- "nrf5x/nrf52833"
- "nrf5x/nrf52840"
- "nrf5x/nrf5340"
- "Infineon/psoc6-cy8ckit-062S2-43012"
- "Infineon/psoc6-cy8ckit-062-BLE"
- "Infineon/psoc6-cy8ckit-062s4"
@ -363,10 +382,18 @@ jobs:
RTT_TOOL_CHAIN: "sourcery-i386-unknown-elf"
SUB_RTT_BSP:
- "x86"
- RTT_BSP: "nordic(yml)"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:
- "nrf5x/nrf51822"
- "nrf5x/nrf52832"
- "nrf5x/nrf52833"
- "nrf5x/nrf52840"
- "nrf5x/nrf5340"
steps:
- uses: actions/checkout@v4
- name: Set up Python
uses: actions/setup-python@v3
uses: actions/setup-python@main
with:
python-version: 3.8

11
.github/workflows/manual_dist.yml vendored
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@ -44,11 +44,6 @@ on:
required: true
type: boolean
default: false
debug_flag:
description: 'True to debug action, False not debug'
required: true
type: boolean
default: false
permissions:
contents: read # to fetch code (actions/checkout)
@ -167,12 +162,6 @@ jobs:
cppcheck --project=bsp/$RTT_BSP/compile_commands.json
pwd
- name: Setup Debug Session
if: ${{ github.event.inputs.debug_flag }}
uses: csexton/debugger-action@master
- uses: actions/upload-artifact@v3
if: ${{ github.event.inputs.dist_flag }}
with:

43
.github/workflows/manual_trigger_scons_except_STM32_all.yml vendored
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@ -43,7 +43,6 @@ jobs:
legs:
- {RTT_BSP_NAME: "acm32_acm32f0x0-nucleo", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "acm32/acm32f0x0-nucleo"}
- {RTT_BSP_NAME: "acm32_acm32f4xx-nucleo", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "acm32/acm32f4xx-nucleo"}
#- {RTT_BSP_NAME: "airm2m_air105", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "airm2m/air105"} #scons fail in last step
- {RTT_BSP_NAME: "airm2m_air32f103", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "airm2m/air32f103"}
#- {RTT_BSP_NAME: "allwinner_d1", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "allwinner/d1"} # rt-smart fail toolchain
#- {RTT_BSP_NAME: "allwinner_d1s", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "allwinner/d1s"} #toochain
@ -91,11 +90,11 @@ jobs:
- {RTT_BSP_NAME: "dm365", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "dm365"}
- {RTT_BSP_NAME: "efm32", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "efm32"}
- {RTT_BSP_NAME: "ESP32_C3", RTT_TOOL_CHAIN: "sourcery-riscv32-esp32", RTT_BSP: "ESP32_C3"}
#- {RTT_BSP_NAME: "essemi_es32f0654", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32f0654"} #GCC link文件没支持好
#- {RTT_BSP_NAME: "essemi_es32f365x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32f365x"} #GCC link文件没支持好
- {RTT_BSP_NAME: "essemi_es32f0654", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32f0654"}
- {RTT_BSP_NAME: "essemi_es32f365x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32f365x"}
- {RTT_BSP_NAME: "essemi_es32f369x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32f369x"}
- {RTT_BSP_NAME: "essemi_es32vf2264", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32vf2264"}
#- {RTT_BSP_NAME: "fm33lc026", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "fm33lc026"} #GCC
- {RTT_BSP_NAME: "fm33lc026", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "fm33lc026"}
- {RTT_BSP_NAME: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "frdm-k64f"}
#- {RTT_BSP_NAME: "ft2004", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ft2004"} #编译错误
- {RTT_BSP_NAME: "ft32_ft32f072xb-starter", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ft32/ft32f072xb-starter"}
@ -120,7 +119,7 @@ jobs:
- {RTT_BSP_NAME: "gd32_risc-v_gd32vf103v-eval", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed", RTT_BSP: "gd32/risc-v/gd32vf103v-eval"}
- {RTT_BSP_NAME: "hc32_ev_hc32f460_lqfp100_v2", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32/ev_hc32f460_lqfp100_v2"}
- {RTT_BSP_NAME: "hc32_ev_hc32f4a0_lqfp176", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32/ev_hc32f4a0_lqfp176"}
#- {RTT_BSP_NAME: "hc32l136", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32l136"} #编译错误
- {RTT_BSP_NAME: "hc32l136", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32l136"}
- {RTT_BSP_NAME: "hc32l196", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32l196"}
- {RTT_BSP_NAME: "hifive1", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed", RTT_BSP: "hifive1"}
#- {RTT_BSP_NAME: "hk32_hk32f030c8-mini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hk32/hk32f030c8-mini"} #scons dist有问题
@ -139,7 +138,7 @@ jobs:
- {RTT_BSP_NAME: "imxrt_imxrt1060-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imxrt/imxrt1060-nxp-evk"}
- {RTT_BSP_NAME: "imxrt_imxrt1061-forlinx-OK1061-S", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imxrt/imxrt1061-forlinx-OK1061-S"}
- {RTT_BSP_NAME: "imxrt_imxrt1064-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imxrt/imxrt1064-nxp-evk"}
#- {RTT_BSP_NAME: "imxrt_imxrt1170-nxp-evk_m7", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imxrt/imxrt1170-nxp-evk/m7"} #GCC 编译有问题
- {RTT_BSP_NAME: "imxrt_imxrt1170-nxp-evk_m7", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imxrt/imxrt1170-nxp-evk/m7"}
- {RTT_BSP_NAME: "Infineon_psoc6-cy8ckit-062-BLE", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "Infineon/psoc6-cy8ckit-062-BLE"}
- {RTT_BSP_NAME: "Infineon_psoc6-cy8ckit-062-WIFI-BT", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "Infineon/psoc6-cy8ckit-062-WIFI-BT"}
- {RTT_BSP_NAME: "Infineon_psoc6-cy8ckit-062S2-43012", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "Infineon/psoc6-cy8ckit-062S2-43012"}
@ -155,7 +154,7 @@ jobs:
- {RTT_BSP_NAME: "loongson_ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips", RTT_BSP: "loongson/ls1bdev"}
- {RTT_BSP_NAME: "loongson_ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips", RTT_BSP: "loongson/ls1cdev"}
- {RTT_BSP_NAME: "loongson_ls2kdev", RTT_TOOL_CHAIN: "sourcery-mips", RTT_BSP: "loongson/ls2kdev"}
- {RTT_BSP_NAME: "lpc1114", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc1114"}
- {RTT_BSP_NAME: "lpc1114", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc1114"} # 默认使用nano版本
- {RTT_BSP_NAME: "lpc176x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc176x"}
- {RTT_BSP_NAME: "lpc178x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc178x"}
- {RTT_BSP_NAME: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc2148"}
@ -165,13 +164,17 @@ jobs:
#- {RTT_BSP_NAME: "lpc43xx_M4", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc43xx/M4"} #编译问题
- {RTT_BSP_NAME: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc5410x"}
- {RTT_BSP_NAME: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc54114-lite"}
#- {RTT_BSP_NAME: "lpc54608-LPCXpresso", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc54608-LPCXpresso"} #编译问题
- {RTT_BSP_NAME: "lpc54608-LPCXpresso", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc54608-LPCXpresso"}
- {RTT_BSP_NAME: "lpc55sxx_lpc55s06_nxp_evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc55sxx/lpc55s06_nxp_evk"}
- {RTT_BSP_NAME: "lpc55sxx_lpc55s16_nxp_evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc55sxx/lpc55s16_nxp_evk"}
- {RTT_BSP_NAME: "lpc55sxx_lpc55s28_nxp_evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc55sxx/lpc55s28_nxp_evk"}
- {RTT_BSP_NAME: "lpc55sxx_lpc55s36_nxp_evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc55sxx/lpc55s36_nxp_evk"}
- {RTT_BSP_NAME: "lpc55sxx_lpc55s69_nxp_evk", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc55sxx/lpc55s69_nxp_evk"}
#- {RTT_BSP_NAME: "lpc824", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc824"} #编译问题
- {RTT_BSP_NAME: "lpc824", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "lpc824"} # 默认使用nano版本
- {RTT_BSP_NAME: "frdm-mcxa153", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mcx/mcxa/frdm-mcxa153"}
- {RTT_BSP_NAME: "frdm-mcxc444", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mcx/mcxc/frdm-mcxc444"}
- {RTT_BSP_NAME: "frdm-mcxn236", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mcx/mcxn/frdm-mcxn236"}
- {RTT_BSP_NAME: "frdm-mcxn947", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mcx/mcxa/frdm-mcxn947"}
#- {RTT_BSP_NAME: "m16c62p", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "m16c62p"} #编译问题
- {RTT_BSP_NAME: "maxim_max32660-evsys", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "maxim/max32660-evsys"}
#- {RTT_BSP_NAME: "microblaze", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "microblaze"} #编译问题
@ -185,7 +188,7 @@ jobs:
- {RTT_BSP_NAME: "mm32_mm32f3270-100ask-pitaya", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32/mm32f3270-100ask-pitaya"}
- {RTT_BSP_NAME: "mm32f103x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32f103x"}
#- {RTT_BSP_NAME: "mm32f327x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32f327x"} #编译问题
#- {RTT_BSP_NAME: "mm32l07x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32l07x"} #编译问题
- {RTT_BSP_NAME: "mm32l07x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32l07x"}
- {RTT_BSP_NAME: "mm32l3xx", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "mm32l3xx"}
- {RTT_BSP_NAME: "n32_n32g43xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g43xcl-stb"}
- {RTT_BSP_NAME: "n32_n32g457qel-stb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "n32/n32g457qel-stb"}
@ -255,7 +258,7 @@ jobs:
#- {RTT_BSP_NAME: "upd70f3454", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "upd70f3454"} #GCC还没支持
- {RTT_BSP_NAME: "Vango_v85xx", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "Vango/v85xx"}
- {RTT_BSP_NAME: "Vango_v85xxp", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "Vango/v85xxp"}
#- {RTT_BSP_NAME: "w60x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "w60x"} #menuconfig有问题
- {RTT_BSP_NAME: "w60x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "w60x"}
- {RTT_BSP_NAME: "wch_arm_ch32f103c8-core", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "wch/arm/ch32f103c8-core"}
- {RTT_BSP_NAME: "wch_arm_ch32f203r-evt", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "wch/arm/ch32f203r-evt"}
#- {RTT_BSP_NAME: "wch_arm_ch579m", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "wch/arm/ch579m"} #编译错误
@ -267,10 +270,22 @@ jobs:
#- {RTT_BSP_NAME: "x86", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "x86"} #menuconfig有问题，toolchain也不支持
#- {RTT_BSP_NAME: "xplorer4330_M0", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "xplorer4330/M0"} #编译问题
- {RTT_BSP_NAME: "xplorer4330_M4", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "xplorer4330/M4"}
# - {RTT_BSP_NAME: "yichip_yc3121-pos", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "yichip/yc3121-pos"} #编译问题
# - {RTT_BSP_NAME: "yichip_yc3122-pos", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "yichip/yc3122-pos"} #编译问题
- {RTT_BSP_NAME: "yichip_yc3121-pos", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "yichip/yc3121-pos"}
- {RTT_BSP_NAME: "yichip_yc3122-pos", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "yichip/yc3122-pos"}
- {RTT_BSP_NAME: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "zynqmp-r5-axu4ev"}
- {RTT_BSP_NAME: "nuvoton_numaker-pfm-m487", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/numaker-pfm-m487"}
- {RTT_BSP_NAME: "nuvoton_numaker-hmi-ma35d1", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/numaker-hmi-ma35d1"}
- {RTT_BSP_NAME: "nuvoton_numaker-iot-m487", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/numaker-iot-m487"}
- {RTT_BSP_NAME: "nuvoton_numaker-m032ki", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/numaker-m032ki"}
- {RTT_BSP_NAME: "nuvoton_numaker-iot-m467", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/numaker-iot-m467"}
- {RTT_BSP_NAME: "nuvoton_numaker-m467hj", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/numaker-m467hj"}
- {RTT_BSP_NAME: "nuvoton_nk-n9h30", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/nk-n9h30"}
- {RTT_BSP_NAME: "nuvoton_nk-rtu980", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/nk-rtu980"}
- {RTT_BSP_NAME: "nuvoton_ma35-rtp", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/ma35-rtp"}
- {RTT_BSP_NAME: "nuvoton_nk-980iot", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/nk-980iot"}
- {RTT_BSP_NAME: "nuvoton_numaker-iot-ma35d1", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/numaker-iot-ma35d1"}
- {RTT_BSP_NAME: "nuvoton_numaker-m2354 ", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuvoton/numaker-m2354"}
steps:
- uses: actions/checkout@v4
- name: Set up Python

2
README.md
View File

@ -12,7 +12,7 @@
[![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls)
[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls)
[![RT-Thread BSP Static Build Check](https://github.com/RT-Thread/rt-thread/actions/workflows/bsp_buildings.yml/badge.svg)](https://github.com/RT-Thread/rt-thread/actions/workflows/bsp_buildings.yml)
<a href="https://hellogithub.com/repository/5816fc3c1e714d109631ceb377538ca9" target="_blank"><img src="https://api.hellogithub.com/v1/widgets/recommend.svg?rid=5816fc3c1e714d109631ceb377538ca9&claim_uid=kVCe5FXIMGAjJfy" alt="Featured｜HelloGitHub" style="width: 100px; height: 20px;" width="250" height="54" /></a>
# RT-Thread
RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS).

21
bsp/ESP32_C3/drivers/Kconfig
View File

@ -47,6 +47,11 @@ menu "Onboard Peripheral Drivers"
default 20 if BSP_BOARD_LUATOS_ESP32C3
depends on BSP_USING_UART
config RT_BSP_SPI_CS_PIN
int "SPI GPIO PIN SET"
default 10 if BSP_BOARD_LUATOS_ESP32C3
depends on BSP_USING_SPI2
endmenu
@ -70,7 +75,17 @@ menu "On-chip Peripheral Drivers"
config BSP_USING_I2C0
bool "Enable I2C0"
default n
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI2
bool "Enable SPI2"
default n
endif
config BSP_USING_WIFI
bool "Enable WIFI"
@ -137,6 +152,4 @@ config BSP_ENABLE_GDBSTUB
bool "Enable ESP_GDBSTUB compontent"
default n
endmenu
endmenu

3
bsp/ESP32_C3/drivers/SConscript
View File

@ -27,6 +27,9 @@ if GetDepend('BSP_USING_HWTIMER'):
if GetDepend('BSP_USING_WIFI'):
src += ['drv_wifi.c']
if GetDepend('BSP_USING_SPI'):
src += ['drv_spi.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

177
bsp/ESP32_C3/drivers/drv_spi.c Normal file
View File

@ -0,0 +1,177 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-10-08 wumingzi first implementation
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "rtdef.h"
#include "rttypes.h"
#include "sdkconfig.h"
#include "hal/spi_hal.h" /*bsp/ESP32_C3/packages/ESP-IDF-latest/components/hal/include/hal/spi_types.h*/
#include "driver/gpio.h" /*bsp/ESP32_C3/packages/ESP-IDF-latest/components/driver/include/driver/gpio.h*/
#include "driver/spi_master.h"
#include "drv_spi.h"
#ifdef RT_USING_SPI
#ifdef BSP_USING_SPI2
#define LOG_TAG "drv.spi"
#include <rtdbg.h>
static struct rt_spi_bus spi_bus2;
static spi_device_handle_t spi;
static spi_bus_config_t buscfg;
static struct esp32_spi spi_bus_obj[] = {
#ifdef BSP_USING_SPI2
{
.bus_name = "spi2",
.spi_bus = &spi_bus2,
.esp32_spi_bus_cfg = &buscfg,
},
#endif /* BSP_USING_SPI2 */
};
/* private rt-thread spi ops function */
static rt_err_t spi_configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
static rt_ssize_t spixfer(struct rt_spi_device* device, struct rt_spi_message* message);
static struct rt_spi_ops esp32_spi_ops =
{
.configure = spi_configure,
.xfer = spixfer,
};
/**
* @brief SPI Initialization
* @param esp32_spi: SPI BUS
* @retval None
*/
static void esp32_spi_init(struct esp32_spi *esp32_spi)
{
spi_configure(NULL,NULL);
}
static void spi_pin_mode(rt_base_t pin)
{
gpio_config_t io_conf;
io_conf.intr_type = GPIO_INTR_DISABLE;
io_conf.mode = GPIO_MODE_OUTPUT;
io_conf.pin_bit_mask = (1ULL << pin);
io_conf.pull_down_en = 0;
io_conf.pull_up_en = 1;
}
static rt_err_t spi_configure(struct rt_spi_device* device,
struct rt_spi_configuration* configuration)
{
/* spi_pin_mode(RT_BSP_SPI_CS_PIN);*/
static spi_bus_config_t buscfg =
{
.miso_io_num=SPI2_IOMUX_PIN_NUM_MISO, /*MISO*/
.mosi_io_num=SPI2_IOMUX_PIN_NUM_MOSI, /*MOSI*/
.sclk_io_num=SPI2_IOMUX_PIN_NUM_CLK, /*CLK*/
.quadwp_io_num=-1, /*不使用*/
.quadhd_io_num=-1, /*不使用*/
.max_transfer_sz=4092 /*最大传送数据长度*/
};
esp_err_t err = spi_bus_initialize(SPI2_HOST, &buscfg, SPI_DMA_CH_AUTO);
ESP_ERROR_CHECK(err);
static spi_device_interface_config_t devcfg={
.clock_speed_hz = SPI_MASTER_FREQ_8M,
.mode = 0,
.spics_io_num = RT_BSP_SPI_CS_PIN,
.queue_size = 7,
};
err = spi_bus_add_device(SPI2_HOST, &devcfg, &spi);
ESP_ERROR_CHECK(err);
spi_bus_obj[0].bus_name = "spi2";
spi_bus_obj[0].spi_bus = &spi_bus2;
spi_bus_obj[0].esp32_spi_bus_cfg = &buscfg;
return RT_EOK;
};
static rt_ssize_t spixfer(struct rt_spi_device* device, struct rt_spi_message* message)
{
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
static spi_transaction_t trans;
trans.tx_buffer = message->send_buf;
trans.rx_buffer = message->recv_buf;
trans.length = message->length;
trans.rxlength = message->length;
spi_device_acquire_bus(spi, portMAX_DELAY);
esp_err_t err = spi_device_polling_transmit(spi, &trans);
spi_device_release_bus(spi);
ESP_ERROR_CHECK(err);
return RT_EOK;
};
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
rt_err_t result;rt_device_t busp = RT_NULL;
struct rt_spi_device *spi_device;
/* attach the device to spi bus*/
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
if (result != RT_EOK)
{
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
RT_ASSERT(result == RT_EOK);
LOG_D("%s attach to %s done", device_name, bus_name);
return result;
}
int rt_hw_spi_init(void)
{
int result = 0;
spi_bus_obj[0].spi_bus->parent.user_data = (void *)&spi_bus_obj[0];
result = rt_spi_bus_register(spi_bus_obj[0].spi_bus, spi_bus_obj[0].bus_name, &esp32_spi_ops);
RT_ASSERT(result == RT_EOK);
LOG_D("%s bus init done", spi_bus_obj[i].bus_name);
return result;
}
INIT_BOARD_EXPORT(rt_hw_spi_init);
#endif /* BSP_USING_SPI0 || BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4*/
#endif /* RT_USING_SPI */

36
bsp/ESP32_C3/drivers/drv_spi.h Normal file
View File

@ -0,0 +1,36 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-10-08 wumingzi first implementation
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#include "driver/spi_common.h" /*bsp/ESP32_C3/packages/ESP-IDF-latest/components/driver/include/driver/spi_common.h*/
#ifdef __cplusplus
extern "C" {
#endif
/* esp32 spi dirver class */
struct esp32_spi
{
char *bus_name;
struct rt_spi_bus *spi_bus;
spi_bus_config_t* esp32_spi_bus_cfg;
};
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_SPI_H__ */

3
bsp/Infineon/libraries/HAL_Drivers/SConscript
View File

@ -59,6 +59,9 @@ if GetDepend(['RT_USING_DAC']):
if GetDepend(['BSP_USING_TIM']):
src += ['drv_hwtimer.c']
if GetDepend(['BSP_USING_ETH']):
src += ['drv_eth.c']
path = [cwd]
path += [cwd + '/config']

10
bsp/Infineon/libraries/HAL_Drivers/drv_adc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,7 +15,7 @@
#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)
//#define DRV_DEBUG
/*#define DRV_DEBUG*/
#define LOG_TAG "drv.adc"
#include <drv_log.h>
@ -45,9 +45,9 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
const cyhal_adc_channel_config_t channel_config =
{
.enable_averaging = false, // Disable averaging for channel
.min_acquisition_ns = 1000, // Minimum acquisition time set to 1us
.enabled = enabled // Sample this channel when ADC performs a scan
.enable_averaging = false, /* Disable averaging for channel*/
.min_acquisition_ns = 1000, /* Minimum acquisition time set to 1us*/
.enabled = enabled /* Sample this channel when ADC performs a scan*/
};
if (enabled)

16
bsp/Infineon/libraries/HAL_Drivers/drv_adc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -28,13 +28,13 @@ cyhal_adc_channel_t adc_chan_obj;
const cyhal_adc_config_t adc_config =
{
.continuous_scanning = false, // Continuous Scanning is disabled
.average_count = 1, // Average count disabled
.vref = CYHAL_ADC_REF_VDDA, // VREF for Single ended channel set to VDDA
.vneg = CYHAL_ADC_VNEG_VSSA, // VNEG for Single ended channel set to VSSA
.resolution = 12u, // 12-bit resolution
.ext_vref = NC, // No connection
.bypass_pin = NC // No connection
.continuous_scanning = false, /* Continuous Scanning is disabled*/
.average_count = 1, /* Average count disabled*/
.vref = CYHAL_ADC_REF_VDDA, /* VREF for Single ended channel set to VDDA*/
.vneg = CYHAL_ADC_VNEG_VSSA, /* VNEG for Single ended channel set to VSSA*/
.resolution = 12u, /* 12-bit resolution*/
.ext_vref = NC, /* No connection*/
.bypass_pin = NC /* No connection*/
};
#ifndef ADC1_CONFIG

2
bsp/Infineon/libraries/HAL_Drivers/drv_common.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/Infineon/libraries/HAL_Drivers/drv_common.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/Infineon/libraries/HAL_Drivers/drv_dac.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/Infineon/libraries/HAL_Drivers/drv_dac.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

867
bsp/Infineon/libraries/HAL_Drivers/drv_eth.c Normal file
View File

@ -0,0 +1,867 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-09-23 LZerro first version
*/
#include <netif/ethernetif.h>
#include <lwipopts.h>
#include "drv_eth.h"
#include "eth_config.h"
#include <rtdbg.h>
#define DBG_TAG "drv"
#define DBG_LVL DBG_INFO
#define cy_ecm_log_msg(a,b,c,...) rt_kprintf(c, __VA_ARGS__)
#define cy_rtos_delay_milliseconds rt_thread_mdelay
#define SLEEP_ETHERNET_PHY_STATUS (500) /* Sleep time in milliseconds. */
#define Eth_Mempool_Num 40
#define MAX_ADDR_LEN 6
/********************************************************/
/******************EMAC configuration********************/
/********************************************************/
#define EMAC_MII 0
#define EMAC_RMII 1
#define EMAC_GMII 2
#define EMAC_RGMII 3
/********************************************************/
/** PHY Mode Selection */
#define EMAC_INTERFACE EMAC_RGMII
/********************************************************/
/* INTERRUPT */
#define ETH_INTR_SRC (CY_GIG_ETH_IRQN0)
#define ETH_INTR_SRC_Q1 (CY_GIG_ETH_IRQN1)
#define ETH_INTR_SRC_Q2 (CY_GIG_ETH_IRQN2)
/* TX_DATA_PIN */
#define ETHx_TD0_PORT CY_GIG_ETH_TD0_PORT
#define ETHx_TD0_PIN CY_GIG_ETH_TD0_PIN
#define ETHx_TD0_PIN_MUX CY_GIG_ETH_TD0_PIN_MUX
#define ETHx_TD1_PORT CY_GIG_ETH_TD1_PORT
#define ETHx_TD1_PIN CY_GIG_ETH_TD1_PIN
#define ETHx_TD1_PIN_MUX CY_GIG_ETH_TD1_PIN_MUX
#define ETHx_TD2_PORT CY_GIG_ETH_TD2_PORT
#define ETHx_TD2_PIN CY_GIG_ETH_TD2_PIN
#define ETHx_TD2_PIN_MUX CY_GIG_ETH_TD2_PIN_MUX
#define ETHx_TD3_PORT CY_GIG_ETH_TD3_PORT
#define ETHx_TD3_PIN CY_GIG_ETH_TD3_PIN
#define ETHx_TD3_PIN_MUX CY_GIG_ETH_TD3_PIN_MUX
/* TX_CTRL_PIN */
#define ETHx_TX_CTL_PORT CY_GIG_ETH_TX_CLK_PORT
#define ETHx_TX_CTL_PIN CY_GIG_ETH_TX_CTL_PIN
#define ETHx_TX_CTL_PIN_MUX CY_GIG_ETH_TX_CTL_PIN_MUX
/* RX_DATA_PIN */
#define ETHx_RD0_PORT CY_GIG_ETH_RD0_PORT
#define ETHx_RD0_PIN CY_GIG_ETH_RD0_PIN
#define ETHx_RD0_PIN_MUX CY_GIG_ETH_RD0_PIN_MUX
#define ETHx_RD1_PORT CY_GIG_ETH_RD1_PORT
#define ETHx_RD1_PIN CY_GIG_ETH_RD1_PIN
#define ETHx_RD1_PIN_MUX CY_GIG_ETH_RD1_PIN_MUX
#define ETHx_RD2_PORT CY_GIG_ETH_RD2_PORT
#define ETHx_RD2_PIN CY_GIG_ETH_RD2_PIN
#define ETHx_RD2_PIN_MUX CY_GIG_ETH_RD2_PIN_MUX
#define ETHx_RD3_PORT CY_GIG_ETH_RD3_PORT
#define ETHx_RD3_PIN CY_GIG_ETH_RD3_PIN
#define ETHx_RD3_PIN_MUX CY_GIG_ETH_RD3_PIN_MUX
/* RX_CTRL_PIN */
#define ETHx_RX_CTL_PORT CY_GIG_ETH_RX_CTL_PORT
#define ETHx_RX_CTL_PIN CY_GIG_ETH_RX_CTL_PIN
#define ETHx_RX_CTL_PIN_MUX CY_GIG_ETH_RX_CTL_PIN_MUX
/* CLK_PORT_PIN */
#define ETHx_TX_CLK_PORT CY_GIG_ETH_TX_CLK_PORT
#define ETHx_TX_CLK_PIN CY_GIG_ETH_TX_CLK_PIN
#define ETHx_TX_CLK_PIN_MUX CY_GIG_ETH_TX_CLK_PIN_MUX
#define ETHx_RX_CLK_PORT CY_GIG_ETH_RX_CLK_PORT
#define ETHx_RX_CLK_PIN CY_GIG_ETH_RX_CLK_PIN
#define ETHx_RX_CLK_PIN_MUX CY_GIG_ETH_RX_CLK_PIN_MUX
/* REF_CLK */
#define ETHx_REF_CLK_PORT CY_GIG_ETH_REF_CLK_PORT
#define ETHx_REF_CLK_PIN CY_GIG_ETH_REF_CLK_PIN
#define ETHx_REF_CLK_PIN_MUX CY_GIG_ETH_REF_CLK_PIN_MUX
/* Management Data Clock */
#define ETHx_MDC_PORT CY_GIG_ETH_MDC_PORT
#define ETHx_MDC_PIN CY_GIG_ETH_MDC_PIN
#define ETHx_MDC_PIN_MUX CY_GIG_ETH_MDC_PIN_MUX
/* Management Data Input/Output */
#define ETHx_MDIO_PORT CY_GIG_ETH_MDIO_PORT
#define ETHx_MDIO_PIN CY_GIG_ETH_MDIO_PIN
#define ETHx_MDIO_PIN_MUX CY_GIG_ETH_MDIO_PIN_MUX
/* Bits masks to verify auto negotiation configured speed */
#define ANLPAR_10_Msk (0x00000020UL) /**< 10BASE-Te Support */
#define ANLPAR_10_Pos (5UL) /**< 10BASE-Te bit position */
#define ANLPAR_10FD_Msk (0x00000040UL) /**< 10BASE-Te Full Duplex Support */
#define ANLPAR_10FD_Pos (6UL) /**< 10BASE-Te Full Duplex bit position */
#define ANLPAR_TX_Msk (0x00000080UL) /**< 100BASE-TX Support */
#define ANLPAR_TX_Pos (7UL) /**< 100BASE-TX bit position */
#define ANLPAR_TXFD_Msk (0x00000100UL) /**< 100BASE-TX Full Duplex Support */
#define ANLPAR_TXFD_Pos (8UL) /**< 100BASE-TX Full Duplex bit position */
#define ANLPAR_T4_Msk (0x00000200UL) /**< 100BASE-T4 Support */
#define ANLPAR_T4_Pos (9UL) /**< 100BASE-T4 bit position */
#define STS1_1000BASE_T_HALFDUPLEX_Msk (0x00000400UL) /**< 1000BASE-T Half-Duplex Capable */
#define STS1_1000BASE_T_HALFDUPLEX_Pos (10UL) /**< 1000BASE-T Half-Duplex bit position */
#define STS1_1000BASE_T_FULLDUPLEX_Msk (0x00000800UL) /**< 1000BASE-T Full-Duplex Capable */
#define STS1_1000BASE_T_FULLDUPLEX_Pos (11UL) /**< 1000BASE-T Full-Duplex bit position */
/********************************************************/
/** PHY related constants */
#define PHY_ADDR (0) /* Value depends on PHY and its hardware configurations */
#define PHY_ID_DP83867IR (0x2000A231) /* PHYIDR1=0x2000 PHYIDR2=0xA231 */
/************************START********************************/
struct rt_ifx_eth
{
/* inherit from ethernet device */
struct eth_device parent;
#ifndef PHY_USING_INTERRUPT_MODE
rt_timer_t poll_link_timer;
#endif
/* interface address info, hw address */
rt_uint8_t dev_addr[MAX_ADDR_LEN];
/* ETH_Speed */
rt_uint32_t ETH_Speed;
/* ETH_Duplex_Mode */
rt_uint32_t ETH_Mode;
cy_stc_ephy_t phy_obj;
ETH_Type *eth_base_type;
};
typedef struct rt_ifx_eth* rt_ifx_eth_t;
static cy_stc_ethif_wrapper_config_t stcWrapperConfig;
uint8_t *pRx_Q_buff_pool[CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE];
static struct rt_ifx_eth ifx_eth_device;
static bool is_driver_configured = false;
static rt_uint8_t eth_mempool[Eth_Mempool_Num][CY_ETH_SIZE_MAX_FRAME];
static rt_uint8_t mempool_index = 0;
static rt_mailbox_t recv_frame_buffer_addr_mb = RT_NULL;
/************************END********************************/
/************************START********************************/
static void Cy_Ethx_InterruptHandler (void);
void cy_process_ethernet_data_cb( ETH_Type *eth_type, uint8_t *rx_buffer, uint32_t length );
void cy_notify_ethernet_rx_data_cb(ETH_Type *base, uint8_t **u8RxBuffer, uint32_t *u32Length);
struct pbuf *rt_ifx_eth_rx(rt_device_t dev);
rt_err_t rt_ifx_eth_tx(rt_device_t dev, struct pbuf *p);
static rt_err_t rt_ifx_eth_open(rt_device_t dev, rt_uint16_t oflag);
static rt_err_t rt_ifx_eth_close(rt_device_t dev);
static rt_ssize_t rt_ifx_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size);
static rt_ssize_t rt_ifx_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
static rt_err_t rt_ifx_eth_control(rt_device_t dev, int cmd, void *args);
static void phy_monitor_thread_entry(void *parameter);
static cy_en_ethif_speed_sel_t ecm_config_to_speed_sel( cy_ecm_phy_config_t *config);
static void eth_clock_config(cy_en_ethif_speed_sel_t speed_sel, cy_ecm_phy_speed_t phy_speed);
void phyRead(uint32_t phyId, uint32_t regAddress, uint32_t *value);
void phyWrite(uint32_t phyId, uint32_t regAddress, uint32_t value);
static void ethernet_portpins_init (cy_ecm_speed_type_t interface_speed_type);
static void init_phy_DP83867IR (ETH_Type *reg_base, cy_ecm_phy_config_t *ecm_phy_config, cy_stc_ephy_t *phy_obj);
cy_rslt_t cy_eth_driver_initialization(ETH_Type *reg_base, cy_ecm_phy_config_t *ecm_phy_config, cy_stc_ephy_t *phy_obj);
static void enable_phy_DP83867IR_extended_reg(ETH_Type *reg_base, cy_ecm_phy_config_t *ecm_phy_config);
static rt_err_t rt_ifx_eth_init(rt_device_t dev);
/************************END********************************/
/************************START********************************/
/** General Ethernet configuration */
static cy_stc_ethif_mac_config_t stcENETConfig = {
.bintrEnable = 1, /** Interrupt enable */
.dmaDataBurstLen = CY_ETHIF_DMA_DBUR_LEN_4,
.u8dmaCfgFlags = CY_ETHIF_CFG_DMA_FRCE_TX_BRST,
.mdcPclkDiv = CY_ETHIF_MDC_DIV_BY_48, /** source clock is 80 MHz and MDC must be less than 2.5MHz */
.u8rxLenErrDisc = 0, /** Length error frame not discarded */
.u8disCopyPause = 0,
.u8chkSumOffEn = 0, /** Checksum for both Tx and Rx disabled */
.u8rx1536ByteEn = 1, /** Enable receive frame up to 1536 */
.u8rxJumboFrEn = 0,
.u8enRxBadPreamble = 1,
.u8ignoreIpgRxEr = 0,
.u8storeUdpTcpOffset = 0,
.u8aw2wMaxPipeline = 2, /** Value must be > 0 */
.u8ar2rMaxPipeline = 2, /** Value must be > 0 */
.u8pfcMultiQuantum = 0,
.pstcWrapperConfig = &stcWrapperConfig,
.pstcTSUConfig = NULL, //&stcTSUConfig, /** TSU settings */
.btxq0enable = 1, /** Tx Q0 Enabled */
.btxq1enable = 0, /** Tx Q1 Disabled */
.btxq2enable = 0, /** Tx Q2 Disabled */
.brxq0enable = 1, /** Rx Q0 Enabled */
.brxq1enable = 0, /** Rx Q1 Disabled */
.brxq2enable = 0, /** Rx Q2 Disabled */
};
/** Interrupt configurations */
static cy_stc_ethif_intr_config_t stcInterruptConfig = {
.btsu_time_match = 0, /** Timestamp unit time match event */
.bwol_rx = 0, /** Wake-on-LAN event received */
.blpi_ch_rx = 0, /** LPI indication status bit change received */
.btsu_sec_inc = 0, /** TSU seconds register increment */
.bptp_tx_pdly_rsp = 0, /** PTP pdelay_resp frame transmitted */
.bptp_tx_pdly_req = 0, /** PTP pdelay_req frame transmitted */
.bptp_rx_pdly_rsp = 0, /** PTP pdelay_resp frame received */
.bptp_rx_pdly_req = 0, /** PTP pdelay_req frame received */
.bptp_tx_sync = 0, /** PTP sync frame transmitted */
.bptp_tx_dly_req = 0, /** PTP delay_req frame transmitted */
.bptp_rx_sync = 0, /** PTP sync frame received */
.bptp_rx_dly_req = 0, /** PTP delay_req frame received */
.bext_intr = 0, /** External input interrupt detected */
.bpause_frame_tx = 0, /** Pause frame transmitted */
.bpause_time_zero = 0, /** Pause time reaches zero or zero pause frame received */
.bpause_nz_qu_rx = 0, /** Pause frame with non-zero quantum received */
.bhresp_not_ok = 0, /** DMA HRESP not OK */
.brx_overrun = 1, /** Rx overrun error */
.bpcs_link_change_det = 0, /** Link status change detected by PCS */
.btx_complete = 1, /** Frame has been transmitted successfully */
.btx_fr_corrupt = 1, /** Tx frame corrupted */
.btx_retry_ex_late_coll = 1, /** Retry limit exceeded or late collision */
.btx_underrun = 1, /** Tx underrun */
.btx_used_read = 1, /** Used bit set has been read in Tx descriptor list */
.brx_used_read = 1, /** Used bit set has been read in Rx descriptor list */
.brx_complete = 1, /** Frame received successfully and stored */
.bman_frame = 0, /** Management frame sent */
};
//回调函数注册
static cy_stc_ethif_cb_t stcInterruptCB = {
/** Callback functions */
.rxframecb = cy_process_ethernet_data_cb, //接收处理回调函数
.txerrorcb = NULL, //发送错误回调函数
.txcompletecb = NULL, //发送完成回调函数
.tsuSecondInccb = NULL, //TSU 计时器每秒递增时触发的回调
.rxgetbuff = cy_notify_ethernet_rx_data_cb //获取空闲缓冲区
};
/************************END********************************/
/************************START********************************/
/** PortPinName.outVal|| driveMode hsiom ||intEdge||intMask||vtrip||slewRate||driveSel||vregEn||ibufMode||vtripSel||vrefSel||vohSel*/
static cy_stc_gpio_pin_config_t ethx_tx0 = {0x00, CY_GPIO_DM_STRONG_IN_OFF, ETHx_TD0_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_tx1 = {0x00, CY_GPIO_DM_STRONG_IN_OFF, ETHx_TD1_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_tx2 = {0x00, CY_GPIO_DM_STRONG_IN_OFF, ETHx_TD2_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_tx3 = {0x00, CY_GPIO_DM_STRONG_IN_OFF, ETHx_TD3_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_txctl = {0x00, CY_GPIO_DM_STRONG_IN_OFF, ETHx_TX_CTL_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_rx0 = {0x00, CY_GPIO_DM_HIGHZ, ETHx_RD0_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_rx1 = {0x00, CY_GPIO_DM_HIGHZ, ETHx_RD1_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_rx2 = {0x00, CY_GPIO_DM_HIGHZ, ETHx_RD2_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_rx3 = {0x00, CY_GPIO_DM_HIGHZ, ETHx_RD3_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_rxctl = {0x00, CY_GPIO_DM_HIGHZ, ETHx_RX_CTL_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_txclk = {0x00, CY_GPIO_DM_STRONG_IN_OFF, ETHx_TX_CLK_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_rxclk = {0x00, CY_GPIO_DM_HIGHZ, ETHx_RX_CLK_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_refclk = {0x00, CY_GPIO_DM_HIGHZ, ETHx_REF_CLK_PIN_MUX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_mdc = {0x00, CY_GPIO_DM_STRONG_IN_OFF, ETHx_MDC_PIN_MUX, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0};
static cy_stc_gpio_pin_config_t ethx_mdio = {0x00, CY_GPIO_DM_STRONG, ETHx_MDIO_PIN_MUX, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0};
/** Enable Ethernet interrupts */
static const cy_stc_sysint_t irq_cfg_ethx_q0 = {.intrSrc = ((NvicMux3_IRQn << 16) | ETH_INTR_SRC), .intrPriority=3UL};
static const cy_stc_sysint_t irq_cfg_ethx_q1 = {.intrSrc = ((NvicMux3_IRQn << 16) | ETH_INTR_SRC_Q1), .intrPriority=3UL};
static const cy_stc_sysint_t irq_cfg_ethx_q2 = {.intrSrc = ((NvicMux3_IRQn << 16) | ETH_INTR_SRC_Q2), .intrPriority=3UL};
/************************END********************************/
/** Interrupt handlers for Ethernet 1 */
static void Cy_Ethx_InterruptHandler (void)
{
/* enter interrupt */
rt_interrupt_enter();
Cy_ETHIF_DecodeEvent(ETH_REG_BASE);
/* leave interrupt */
rt_interrupt_leave();
}
void cy_process_ethernet_data_cb( ETH_Type *eth_type, uint8_t *rx_buffer, uint32_t length )
{
rt_err_t result;
result = rt_mb_send(recv_frame_buffer_addr_mb, (rt_ubase_t)rx_buffer);
if (result != RT_EOK)
{
LOG_I("Send_Recv_Buffer_Adder_MB err = %d", result);
}
result = eth_device_ready(&(ifx_eth_device.parent));
if (result != RT_EOK)
{
LOG_I("RxCpltCallback err = %d", result);
}
}
void cy_notify_ethernet_rx_data_cb(ETH_Type *base, uint8_t **u8RxBuffer, uint32_t *u32Length)
{
*u8RxBuffer = eth_mempool[mempool_index++];
if(mempool_index >= Eth_Mempool_Num)
{
mempool_index = 0;
}
*u32Length = CY_ETH_SIZE_MAX_FRAME;
}
struct pbuf *rt_ifx_eth_rx(rt_device_t dev)
{
rt_err_t result;
rt_uint32_t *rx_buffer;
rt_uint32_t length = CY_ETH_SIZE_MAX_FRAME;
struct pbuf *recv_frame = RT_NULL;
struct pbuf *temp = RT_NULL;
rt_uint32_t bufferoffset = 0;
rt_uint32_t payloadlength = 0;
result = rt_mb_recv(recv_frame_buffer_addr_mb, (rt_ubase_t *)&rx_buffer, 1000);
if(result != RT_EOK)
{
LOG_I("Recv_Recv_Buffer_Adder_MB err = %d", result);
}
recv_frame = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
if(recv_frame != RT_NULL)
{
if(rx_buffer != RT_NULL)
{
for(temp = recv_frame; temp != RT_NULL; temp = temp->next)
{
payloadlength = temp->len;
rt_memcpy((uint8_t *)((uint8_t *)temp->payload), (uint8_t *)((uint8_t *)rx_buffer + bufferoffset), (payloadlength < length ? payloadlength : length));
bufferoffset = bufferoffset + payloadlength;
length = length - payloadlength;
}
}
}
return recv_frame;
}
rt_err_t rt_ifx_eth_tx(rt_device_t dev, struct pbuf *p)
{
struct pbuf *q;
cy_en_ethif_status_t eth_status;
rt_uint32_t framelen = 0;
rt_uint8_t data_buffer[CY_ETH_SIZE_MAX_FRAME];
rt_ifx_eth_t ifx_device = (rt_ifx_eth_t)dev;
if (p->tot_len > (u16_t)CY_ETH_SIZE_MAX_FRAME)
{
return -RT_ERROR;
}
for(q = p; q != NULL; q = q->next)
{
rt_memcpy(data_buffer + framelen, q->payload, q->len);
framelen += (uint32_t)q->len;
}
eth_status = Cy_ETHIF_TransmitFrame(ifx_device->eth_base_type, data_buffer, framelen, CY_ETH_QS0_0, true);
if(eth_status != CY_ETHIF_SUCCESS)
{
rt_kprintf("failed to send outgoing packet:[%d]\n", eth_status);
}
return RT_EOK;
}
static rt_err_t rt_ifx_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
LOG_D("emac open");
return RT_EOK;
}
static rt_err_t rt_ifx_eth_close(rt_device_t dev)
{
LOG_D("emac close");
return RT_EOK;
}
static rt_ssize_t rt_ifx_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
LOG_D("emac read");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_ssize_t rt_ifx_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
LOG_D("emac write");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_ifx_eth_control(rt_device_t dev, int cmd, void *args)
{
rt_ifx_eth_t eth_device = (rt_ifx_eth_t)dev;
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args)
{
SMEMCPY(args, eth_device->dev_addr, 6);
}
else
{
return -RT_ERROR;
}
break;
default :
break;
}
return RT_EOK;
}
static void phy_monitor_thread_entry(void *parameter)
{
static rt_uint32_t phy_status = 0;
rt_uint32_t phy_status_now = 0;
while (1)
{
phy_status_now = Cy_EPHY_GetLinkStatus(&ifx_eth_device.phy_obj);
if(phy_status_now != phy_status)
{
if(phy_status_now == 1UL)
{
rt_kprintf("Link Up\n");
eth_device_linkchange(&ifx_eth_device.parent, RT_TRUE);
}
else
{
rt_kprintf("Link Dowm\n");
eth_device_linkchange(&ifx_eth_device.parent, RT_FALSE);
}
phy_status = phy_status_now;
}
rt_thread_mdelay(1000);
}
}
static cy_en_ethif_speed_sel_t ecm_config_to_speed_sel( cy_ecm_phy_config_t *config)
{
cy_en_ethif_speed_sel_t speed_sel;
if( config->interface_speed_type == CY_ECM_SPEED_TYPE_MII)
{
speed_sel = (cy_en_ethif_speed_sel_t)config->phy_speed;
}
else if( config->interface_speed_type == CY_ECM_SPEED_TYPE_GMII)
{
speed_sel = CY_ETHIF_CTL_GMII_1000;
}
else if( config->interface_speed_type == CY_ECM_SPEED_TYPE_RGMII)
{
if(config->phy_speed == CY_ECM_PHY_SPEED_10M)
{
speed_sel = CY_ETHIF_CTL_RGMII_10;
}
else if(config->phy_speed == CY_ECM_PHY_SPEED_100M)
{
speed_sel = CY_ETHIF_CTL_RGMII_100;
}
else
{
speed_sel = CY_ETHIF_CTL_RGMII_1000;
}
}
else
{
speed_sel = (config->phy_speed == CY_ECM_PHY_SPEED_10M)?CY_ETHIF_CTL_RMII_10 : CY_ETHIF_CTL_RMII_100;
}
return speed_sel;
}
static void eth_clock_config(cy_en_ethif_speed_sel_t speed_sel, cy_ecm_phy_speed_t phy_speed)
{
if((speed_sel == CY_ETHIF_CTL_MII_10) && (phy_speed == CY_ECM_PHY_SPEED_10M))
stcWrapperConfig.stcInterfaceSel = CY_ETHIF_CTL_MII_10; /** 10 Mbps MII */
else if((speed_sel == CY_ETHIF_CTL_MII_100) && (phy_speed == CY_ECM_PHY_SPEED_100M))
stcWrapperConfig.stcInterfaceSel = CY_ETHIF_CTL_MII_100; /** 100 Mbps MII */
else if((speed_sel == CY_ETHIF_CTL_GMII_1000) && (phy_speed == CY_ECM_PHY_SPEED_1000M))
stcWrapperConfig.stcInterfaceSel = CY_ETHIF_CTL_GMII_1000; /** 1000 Mbps GMII */
else if((speed_sel == CY_ETHIF_CTL_RGMII_10) && (phy_speed == CY_ECM_PHY_SPEED_10M))
stcWrapperConfig.stcInterfaceSel = CY_ETHIF_CTL_RGMII_10; /** 10 Mbps RGMII */
else if((speed_sel == CY_ETHIF_CTL_RGMII_100) && (phy_speed == CY_ECM_PHY_SPEED_100M))
stcWrapperConfig.stcInterfaceSel = CY_ETHIF_CTL_RGMII_100; /** 100 Mbps RGMII */
else if((speed_sel == CY_ETHIF_CTL_RGMII_1000) && (phy_speed == CY_ECM_PHY_SPEED_1000M))
stcWrapperConfig.stcInterfaceSel = CY_ETHIF_CTL_RGMII_1000; /** 1000 Mbps RGMII */
else if((speed_sel == CY_ETHIF_CTL_RMII_10) && (phy_speed == CY_ECM_PHY_SPEED_10M))
stcWrapperConfig.stcInterfaceSel = CY_ETHIF_CTL_RMII_10; /** 10 Mbps RMII */
else if((speed_sel == CY_ETHIF_CTL_RMII_100) && (phy_speed == CY_ECM_PHY_SPEED_100M))
stcWrapperConfig.stcInterfaceSel = CY_ETHIF_CTL_RMII_100; /** 100 Mbps RMII */
else
stcWrapperConfig.stcInterfaceSel = CY_ETHIF_CTL_RGMII_1000; /** Error in configuration */
stcWrapperConfig.bRefClockSource = CY_ETHIF_EXTERNAL_HSIO; /** Assigning Ref_Clk to HSIO clock; use an external clock from HSIO */
if(phy_speed == CY_ECM_PHY_SPEED_10M)
stcWrapperConfig.u8RefClkDiv = 10; /** RefClk: 25 MHz; divide Refclock by 10 to have a 2.5-MHz Tx clock */
else if(phy_speed == CY_ECM_PHY_SPEED_100M)
stcWrapperConfig.u8RefClkDiv = 1; /** RefClk: 25 MHz; divide Refclock by 1 to have a 25-MHz Tx clock */
else if(phy_speed == CY_ECM_PHY_SPEED_1000M)
stcWrapperConfig.u8RefClkDiv = 1; /** RefClk: 25 MHz; divide Refclock by 1 to have a 25-MHz Tx clock */
else /*(phy_speed == CY_ECM_PHY_SPEED_1000M)*/
stcWrapperConfig.u8RefClkDiv = 1; /** RefClk: 125 MHz; divide Refclock by 1 to have a 125-MHz Tx clock || Although only relevant in RGMII/GMII modes */
return;
}
/* 读取PHY芯片函数 */
void phyRead(uint32_t phyId, uint32_t regAddress, uint32_t *value)
{
*value = Cy_ETHIF_PhyRegRead(ETH_REG_BASE, regAddress, phyId);
}
/* 写入PHY芯片函数 */
void phyWrite(uint32_t phyId, uint32_t regAddress, uint32_t value)
{
Cy_ETHIF_PhyRegWrite(ETH_REG_BASE, regAddress, value, phyId);
}
/* GPIO 初始化 */
static void ethernet_portpins_init (cy_ecm_speed_type_t interface_speed_type)
{
(void)interface_speed_type;
Cy_GPIO_Pin_Init(ETHx_TD0_PORT, ETHx_TD0_PIN, &ethx_tx0); /** TX0 */
Cy_GPIO_Pin_Init(ETHx_TD1_PORT, ETHx_TD1_PIN, &ethx_tx1); /** TX1 */
Cy_GPIO_Pin_Init(ETHx_TD2_PORT, ETHx_TD2_PIN, &ethx_tx2); /** TX2 */
Cy_GPIO_Pin_Init(ETHx_TD3_PORT, ETHx_TD3_PIN, &ethx_tx3); /** TX3 */
Cy_GPIO_Pin_Init(ETHx_TX_CTL_PORT, ETHx_TX_CTL_PIN, &ethx_txctl); /** TX_CTL */
Cy_GPIO_Pin_Init(ETHx_RD0_PORT, ETHx_RD0_PIN, &ethx_rx0); /** RX0 */
Cy_GPIO_Pin_Init(ETHx_RD1_PORT, ETHx_RD1_PIN, &ethx_rx1); /** RX1 */
Cy_GPIO_Pin_Init(ETHx_RD2_PORT, ETHx_RD2_PIN, &ethx_rx2); /** RX2 */
Cy_GPIO_Pin_Init(ETHx_RD3_PORT, ETHx_RD3_PIN, &ethx_rx3); /** RX3 */
Cy_GPIO_Pin_Init(ETHx_RX_CTL_PORT, ETHx_RX_CTL_PIN, &ethx_rxctl); /** RX_CTL */
Cy_GPIO_Pin_Init(ETHx_REF_CLK_PORT, ETHx_REF_CLK_PIN, &ethx_refclk); /** REF_CLK */
Cy_GPIO_Pin_Init(ETHx_TX_CLK_PORT, ETHx_TX_CLK_PIN, &ethx_txclk); /** TX_CLK */
Cy_GPIO_Pin_Init(ETHx_RX_CLK_PORT, ETHx_RX_CLK_PIN, &ethx_rxclk); /** RX_CLK */
Cy_GPIO_Pin_Init(ETHx_MDC_PORT, ETHx_MDC_PIN, &ethx_mdc); /** MDC */
Cy_GPIO_Pin_Init(ETHx_MDIO_PORT, ETHx_MDIO_PIN, &ethx_mdio); /** MDIO */
}
/* PHY芯片初始化 */
static void init_phy_DP83867IR (ETH_Type *reg_base, cy_ecm_phy_config_t *ecm_phy_config, cy_stc_ephy_t *phy_obj)
{
cy_stc_ephy_config_t phyConfig;
cy_en_ethif_speed_sel_t speed_sel;
uint32_t value = 0;
uint16_t configured_hw_speed;
cy_en_ethif_status_t eth_status;
/* Driver configuration is already done */
if(is_driver_configured == true)
{
/* Initialize the PHY */
Cy_EPHY_Init(phy_obj, phyRead, phyWrite);
/* If driver already configured and the auto negotiation is enabled, replace the speed and mode by the auto negotiated values decided during driver initialization */
if(ecm_phy_config->mode == CY_ECM_DUPLEX_AUTO || ecm_phy_config->phy_speed == CY_ECM_PHY_SPEED_AUTO)
{
phyRead( 0, REGISTER_ADDRESS_PHY_REG_BMCR, &value );
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_ERR, "REGISTER_ADDRESS_PHY_REG_BMCR = 0x%X\n", (unsigned long)value );
ecm_phy_config->mode = ((value & (REGISTER_PHY_REG_DUPLEX_MASK)) == 0) ? CY_ECM_DUPLEX_HALF : CY_ECM_DUPLEX_FULL;
configured_hw_speed = value & (REGISTER_PHY_REG_SPEED_MASK);
if(configured_hw_speed == REGISTER_PHY_REG_SPEED_MASK_10M)
{
ecm_phy_config->phy_speed = CY_ECM_PHY_SPEED_10M;
}
else if (configured_hw_speed == REGISTER_PHY_REG_SPEED_MASK_100M)
{
ecm_phy_config->phy_speed = CY_ECM_PHY_SPEED_100M;
}
else if(configured_hw_speed == REGISTER_PHY_REG_SPEED_MASK_1000M)
{
ecm_phy_config->phy_speed = CY_ECM_PHY_SPEED_1000M;
}
}
}
if(!is_driver_configured)
{
/* Auto Negotiation enable */
if(ecm_phy_config->phy_speed == CY_ECM_PHY_SPEED_AUTO || ecm_phy_config->mode == CY_ECM_DUPLEX_AUTO)
{
eth_status = Cy_ETHIF_MdioInit(reg_base, &stcENETConfig);
if (CY_ETHIF_SUCCESS != eth_status)
{
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_DEBUG, "Ethernet MAC Pre-Init failed with ethStatus=0x%X \n", eth_status );
return;
}
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_DEBUG, "Ethernet MAC Pre-Init success \n", 0);
/* Start auto negotiation */
phyConfig.speed = (cy_en_ephy_speed_t)CY_ECM_PHY_SPEED_AUTO;
phyConfig.duplex = (cy_en_ephy_duplex_t)CY_ECM_DUPLEX_AUTO;
/* Initialize the PHY */
Cy_EPHY_Init(phy_obj, phyRead, phyWrite);
Cy_EPHY_Configure( phy_obj, &phyConfig );
/* Required some delay to get PHY back to Run state */
cy_rtos_delay_milliseconds(100);
while (Cy_EPHY_GetAutoNegotiationStatus(phy_obj) != true)
{
cy_rtos_delay_milliseconds(100);
}
Cy_EPHY_getLinkPartnerCapabilities(phy_obj, &phyConfig);
ecm_phy_config->phy_speed = (cy_ecm_phy_speed_t)phyConfig.speed;
ecm_phy_config->mode = (cy_ecm_duplex_t)phyConfig.duplex;
}
speed_sel = ecm_config_to_speed_sel(ecm_phy_config);
/* Update the configuration based on user input */
eth_clock_config(speed_sel, ecm_phy_config->phy_speed);
/** Initialize ENET MAC */
eth_status = Cy_ETHIF_Init(reg_base, &stcENETConfig, &stcInterruptConfig);
if (CY_ETHIF_SUCCESS != eth_status)
{
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_DEBUG, "Ethernet MAC Init failed with ethStatus=0x%X \n", eth_status );
return;
}
if(!(ecm_phy_config->phy_speed == CY_ECM_PHY_SPEED_AUTO || ecm_phy_config->mode == CY_ECM_DUPLEX_AUTO))
{
/* Initialize the PHY */
Cy_EPHY_Init(phy_obj, phyRead, phyWrite);
}
is_driver_configured = true;
}
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_DEBUG, "Register driver callbacks \n", 0);
stcInterruptCB.rxframecb = cy_process_ethernet_data_cb;
/* Reset the PHY */
Cy_EPHY_Reset(phy_obj);
Cy_ETHIF_PhyRegWrite(reg_base, 0x1F, 0x8000, PHY_ADDR); /* Ext-Reg CTRl: Perform a full reset, including all registers */
cy_rtos_delay_milliseconds(30); /* Required delay of 30 ms to get PHY back to Run state after reset */
Cy_EPHY_Discover(phy_obj);
/* Check for supported PHYs */
if (PHY_ID_DP83867IR != phy_obj->phyId)
{
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_DEBUG, "Not supported physical ID \n", 0);
return;
}
phyConfig.duplex = ecm_phy_config->mode;
phyConfig.speed = ecm_phy_config->phy_speed;
Cy_EPHY_Configure(phy_obj, &phyConfig);
/* Enable PHY extended registers */
enable_phy_DP83867IR_extended_reg(reg_base, ecm_phy_config);
}
cy_rslt_t cy_eth_driver_initialization(ETH_Type *reg_base, cy_ecm_phy_config_t *ecm_phy_config, cy_stc_ephy_t *phy_obj)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
uint32_t retry_count = 0;
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_DEBUG, "%s(): START \n", __FUNCTION__ );
/** Configure Ethernet port pins */
ethernet_portpins_init(ecm_phy_config->interface_speed_type);
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_DEBUG, "GPIO_INIT_FINISH \n", __FUNCTION__ );
Cy_SysInt_Init(&irq_cfg_ethx_q0, Cy_Ethx_InterruptHandler);
Cy_SysInt_Init(&irq_cfg_ethx_q1, Cy_Ethx_InterruptHandler);
Cy_SysInt_Init(&irq_cfg_ethx_q2, Cy_Ethx_InterruptHandler);
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_DEBUG, "ETH_REG_BASE=[%p] reg_base = [%p] \n", ETH_REG_BASE, reg_base );
/* rx Q0 buffer pool */
stcENETConfig.pRxQbuffPool[0] = (cy_ethif_buffpool_t *)&pRx_Q_buff_pool;
stcENETConfig.pRxQbuffPool[1] = NULL;
/** Initialize PHY */
init_phy_DP83867IR(reg_base, ecm_phy_config, phy_obj);
NVIC_ClearPendingIRQ(NvicMux3_IRQn);
NVIC_EnableIRQ(NvicMux3_IRQn);
Cy_ETHIF_RegisterCallbacks(reg_base, &stcInterruptCB);
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_DEBUG, "%s():retry_count:[%d] END \n", __FUNCTION__, retry_count );
return result;
}
static void enable_phy_DP83867IR_extended_reg(ETH_Type *reg_base, cy_ecm_phy_config_t *ecm_phy_config)
{
if(ecm_phy_config->phy_speed == CY_ECM_PHY_SPEED_100M)
{
Cy_ETHIF_PhyRegWrite(reg_base, 0x10, 0x5028, PHY_ADDR); /** Disable auto negotiation for MDI/MDI-X **/
}
else if(ecm_phy_config->phy_speed == CY_ECM_PHY_SPEED_1000M || ecm_phy_config->phy_speed == CY_ECM_PHY_SPEED_AUTO)
{
uint32_t u32ReadData;
Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x001F, PHY_ADDR); /** Begin write access to the extended register */
Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0170, PHY_ADDR);
Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x401F, PHY_ADDR);
u32ReadData = Cy_ETHIF_PhyRegRead(reg_base, (uint8_t)0x0E, PHY_ADDR);
u32ReadData = u32ReadData & 0x0000; /** Change the I/O impedance on the PHY */
u32ReadData = u32ReadData | 0x010C;
Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, u32ReadData, PHY_ADDR); /** Enable clock from the PHY -> Route it to the MCU */
u32ReadData = Cy_ETHIF_PhyRegRead(reg_base, (uint8_t)0x0E, PHY_ADDR);
}
else
{
/* Do nothing */
}
/** Disable RGMII by accessing the extended register set || Please read datasheet section 8.4.2.1 for the procedure in detail */
Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x001F, PHY_ADDR); /** REGCR */
Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0032, PHY_ADDR); /** ADDAR, 0x0032 RGMII config register */
Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x401F, PHY_ADDR); /** REGCR; will force the next write/read access non-incremental */
if(ecm_phy_config->interface_speed_type != CY_ECM_SPEED_TYPE_RGMII)
{
Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0000, PHY_ADDR); /** Disable RGMII */
Cy_ETHIF_PhyRegRead(reg_base, (uint8_t)0x0E, PHY_ADDR); /** Read RGMII mode status */
}
else
{
Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x00D3, PHY_ADDR); /** Enable Tx and RX clock delay in the RGMII configuration register */
Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x001F, PHY_ADDR); /** REGCR */
Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0086, PHY_ADDR); /** ADDAR; 0x0086 delay config register */
Cy_ETHIF_PhyRegWrite(reg_base, 0x0D, 0x401F, PHY_ADDR); /** REGCR; will force the next write/read access non-incremental */
Cy_ETHIF_PhyRegWrite(reg_base, 0x0E, 0x0066, PHY_ADDR); /** Adjust Tx and Rx clock delays in the PHY */
}/* EMAC_INTERFACE != EMAC_RGMII */
Cy_ETHIF_PhyRegWrite(reg_base, 0x1F, 0x4000, PHY_ADDR); /** CTRL */
cy_rtos_delay_milliseconds(30);/** Some more delay to get the PHY adapted to new interface */
Cy_ETHIF_PhyRegRead(reg_base, (uint8_t)0x11, PHY_ADDR);
}
static rt_err_t rt_ifx_eth_init(rt_device_t dev)
{
rt_err_t state = RT_EOK;
cy_ecm_phy_config_t phy_interface_type;
ifx_eth_device.eth_base_type = ETH_INTERFACE_TYPE;
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_INFO, "Device's eth_base_type is:%d\n", ETH_INTERFACE_TYPE);
phy_interface_type.interface_speed_type = CY_ECM_SPEED_TYPE_RGMII;
phy_interface_type.phy_speed = CY_ECM_PHY_SPEED_1000M;
phy_interface_type.mode = CY_ECM_DUPLEX_FULL;
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_INFO, "Using default phy_interface_type\nType :%d\nSpeed :%d\nMode :%d\n"
,phy_interface_type.interface_speed_type
,phy_interface_type.phy_speed
,phy_interface_type.mode);
cy_eth_driver_initialization(ifx_eth_device.eth_base_type, &phy_interface_type, &(ifx_eth_device.phy_obj));
return state;
}
static int rt_hw_ifx_eth_init(void)
{
rt_err_t result = RT_EOK;
recv_frame_buffer_addr_mb = rt_mb_create("Eth_rx_mb", Eth_Mempool_Num, RT_IPC_FLAG_PRIO);
if(recv_frame_buffer_addr_mb == RT_NULL)
{
LOG_I("Eth MailBox Init Fail");
}
for(rt_uint8_t i = 0; i < CY_ETH_DEFINE_TOTAL_BD_PER_RXQUEUE; i++)
{
pRx_Q_buff_pool[i] = rt_malloc(sizeof(uint8) * CY_ETH_SIZE_MAX_FRAME);
}
ifx_eth_device.dev_addr[0] = 0x00;
ifx_eth_device.dev_addr[1] = 0x03;
ifx_eth_device.dev_addr[2] = 0x19;
ifx_eth_device.dev_addr[3] = 0x45;
ifx_eth_device.dev_addr[4] = 0x00;
ifx_eth_device.dev_addr[5] = 0x00;
cy_ecm_log_msg( CYLF_MIDDLEWARE, CY_LOG_INFO, "Assigning default MAC address 00-03-19-45-00-00\n", 0);
ifx_eth_device.parent.parent.init = rt_ifx_eth_init;
ifx_eth_device.parent.parent.open = rt_ifx_eth_open;
ifx_eth_device.parent.parent.close = rt_ifx_eth_close;
ifx_eth_device.parent.parent.read = rt_ifx_eth_read;
ifx_eth_device.parent.parent.write = rt_ifx_eth_write;
ifx_eth_device.parent.parent.control = rt_ifx_eth_control;
ifx_eth_device.parent.parent.user_data = RT_NULL;
ifx_eth_device.parent.eth_rx = rt_ifx_eth_rx;
ifx_eth_device.parent.eth_tx = rt_ifx_eth_tx;
result = eth_device_init(&(ifx_eth_device.parent), "e0");
if(result != RT_EOK)
{
LOG_E("emac device init faild: %d", result);
result = -RT_ERROR;
return result;
}
else
{
LOG_D("emac device init success");
}
rt_thread_t tid;
tid = rt_thread_create("phy",
phy_monitor_thread_entry,
RT_NULL,
1024,
RT_THREAD_PRIORITY_MAX - 2,
2);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("phy thread init faild: %d", result);
result = -RT_ERROR;
return result;
}
return result;
}
INIT_DEVICE_EXPORT(rt_hw_ifx_eth_init);

92
bsp/Infineon/libraries/HAL_Drivers/drv_eth.h Normal file
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@ -0,0 +1,92 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-09-23 LZerro first version
*/
#ifndef __DRV_ETH_H__
#define __DRV_ETH_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#include "eth_config.h"
/* The PHY basic control register */
#define PHY_BASIC_CONTROL_REG 0x00U
#define PHY_RESET_MASK (1<<15)
#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
/* The PHY basic status register */
#define PHY_BASIC_STATUS_REG 0x01U
#define PHY_LINKED_STATUS_MASK (1<<2)
#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
/* The PHY ID one register */
#define PHY_ID1_REG 0x02U
/* The PHY ID two register */
#define PHY_ID2_REG 0x03U
/* The PHY auto-negotiate advertise register */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
/** PHY duplex mode */
typedef enum
{
CY_ECM_DUPLEX_HALF, /**< Half duplex */
CY_ECM_DUPLEX_FULL, /**< Full duplex */
CY_ECM_DUPLEX_AUTO /**< Both half/full duplex */
} cy_ecm_duplex_t;
/** PHY speed */
typedef enum
{
CY_ECM_PHY_SPEED_10M, /**< 10 Mbps */
CY_ECM_PHY_SPEED_100M, /**< 100 Mbps */
CY_ECM_PHY_SPEED_1000M, /**< 1000 Mbps */
CY_ECM_PHY_SPEED_AUTO /**< All 10/100/1000 Mbps */
} cy_ecm_phy_speed_t;
/** Standard interface type */
typedef enum
{
CY_ECM_SPEED_TYPE_MII, /**< Media-Independent Interface (MII) */
CY_ECM_SPEED_TYPE_GMII, /**< Gigabit Media-Independent Interface (GMII) */
CY_ECM_SPEED_TYPE_RGMII, /**< Reduced Gigabit Media-Independent Interface (RGMII) */
CY_ECM_SPEED_TYPE_RMII /**< Reduced Media-Independent Interface (RMII) */
} cy_ecm_speed_type_t;
typedef struct
{
cy_ecm_speed_type_t interface_speed_type; /**< Standard interface to be used for data transfer */
cy_ecm_phy_speed_t phy_speed; /**< Physical transfer speed */
cy_ecm_duplex_t mode; /**< Transfer mode */
} cy_ecm_phy_config_t;
extern int eth_index_internal;
#define ETH_INTERFACE_TYPE ETH1
/* After hardware initialization, max wait time to get the physical link up */
#define MAX_WAIT_ETHERNET_PHY_STATUS (10000)
#define REGISTER_ADDRESS_PHY_REG_BMCR PHYREG_00_BMCR /* BMCR register (0x0000) to read the speed and duplex mode */
#define REGISTER_PHY_REG_DUPLEX_MASK PHYBMCR_FULL_DUPLEX_Msk /* Bit 8 of BMCR register to read the duplex mode */
#define REGISTER_PHY_REG_SPEED_MASK (0x2040) /* Bit 6, 13: BMCR register to read the speed */
#define REGISTER_PHY_REG_SPEED_MASK_10M (0x0000) /* Bit 6, 13: Both are set to 0 for 10M speed */
#define REGISTER_PHY_REG_SPEED_MASK_100M (0x2000) /* Bit 6, 13: Set to 0 and 1 respectively for 100M speed */
#define REGISTER_PHY_REG_SPEED_MASK_1000M (0x0040) /* Bit 6, 13: Set to 1 and 0 respectively for 1000M speed */
#endif /* __DRV_ETH_H__ */

2
bsp/Infineon/libraries/HAL_Drivers/drv_flash.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/Infineon/libraries/HAL_Drivers/drv_flash.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/Infineon/libraries/HAL_Drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/Infineon/libraries/HAL_Drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -13,7 +13,7 @@
#include <board.h>
#ifdef BSP_USING_TIM
//#define DRV_DEBUG
/*#define DRV_DEBUG*/
#define LOG_TAG "drv.hwtimer"
#include <drv_log.h>

2
bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

5
bsp/Infineon/libraries/HAL_Drivers/drv_i2c.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -101,7 +101,8 @@ static struct ifx_i2c_config i2c_config[] =
#endif
};
static struct ifx_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0};
static struct ifx_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] =
{0};
static int ifx_i2c_read(struct ifx_i2c *hi2c, rt_uint16_t slave_address, rt_uint8_t *p_buffer, rt_uint16_t data_byte)
{

2
bsp/Infineon/libraries/HAL_Drivers/drv_log.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/Infineon/libraries/HAL_Drivers/drv_pwm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -14,7 +14,7 @@
#include <drivers/dev_pwm.h>
#include "drv_gpio.h"
//#define DRV_DEBUG
/*#define DRV_DEBUG*/
#define LOG_TAG "drv.pwm"
#include <drv_log.h>
@ -89,12 +89,12 @@ static rt_err_t drv_pwm_enable(cyhal_pwm_t *htim, struct rt_pwm_configuration *c
{
if (!enable)
{
htim->tcpwm.resource.channel_num = channel;
htim->tcpwm.resource.channel_num = channel;
cyhal_pwm_stop(htim);
}
else
{
htim->tcpwm.resource.channel_num = channel;
htim->tcpwm.resource.channel_num = channel;
cyhal_pwm_start(htim);
}
}

2
bsp/Infineon/libraries/HAL_Drivers/drv_pwm.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

76
bsp/Infineon/libraries/HAL_Drivers/drv_rtc.c
View File

@ -1,11 +1,12 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-07-25 Rbb666 first version
* 2024-11-06 kurisaw add alarm function
*/
#include <rtthread.h>
@ -15,13 +16,21 @@
#ifdef BSP_USING_RTC
//#define DRV_DEBUG
/*#define DRV_DEBUG*/
#define LOG_TAG "drv.rtc"
#include <drv_log.h>
cyhal_rtc_t rtc_obj;
static rt_rtc_dev_t ifx32_rtc_dev;
struct rtc_device_object
{
rt_rtc_dev_t rtc_dev;
#ifdef RT_USING_ALARM
struct rt_rtc_wkalarm wkalarm;
#endif
};
static struct rtc_device_object ifx32_rtc_dev;
static int get_day_of_week(int day, int month, int year)
{
@ -105,6 +114,10 @@ static rt_err_t _rtc_init(void)
return -RT_ERROR;
}
#ifdef RT_USING_ALARM
cyhal_rtc_register_callback(&rtc_obj, rtc_alarm_callback, NULL);
cyhal_rtc_enable_event(&rtc_obj, CYHAL_RTC_ALARM, 3u, true);
#endif
return RT_EOK;
}
@ -133,13 +146,62 @@ static rt_err_t _rtc_set_secs(time_t *sec)
return result;
}
#if defined(RT_USING_ALARM)
static rt_err_t _rtc_get_alarm(struct rt_rtc_wkalarm *alarm)
{
#ifdef RT_USING_ALARM
*alarm = ifx32_rtc_dev.wkalarm;
LOG_D("GET_ALARM %d:%d:%d",ifx32_rtc_dev.wkalarm.tm_hour,
ifx32_rtc_dev.wkalarm.tm_min,ifx32_rtc_dev.wkalarm.tm_sec);
return RT_EOK;
#else
return -RT_ERROR;
#endif
}
static rt_err_t _rtc_set_alarm(struct rt_rtc_wkalarm *alarm)
{
#ifdef RT_USING_ALARM
LOG_D("RT_DEVICE_CTRL_RTC_SET_ALARM");
if (alarm != RT_NULL)
{
ifx32_rtc_dev.wkalarm.enable = alarm->enable;
ifx32_rtc_dev.wkalarm.tm_hour = alarm->tm_hour;
ifx32_rtc_dev.wkalarm.tm_min = alarm->tm_min;
ifx32_rtc_dev.wkalarm.tm_sec = alarm->tm_sec;
cyhal_rtc_set_alarm_by_seconds(&rtc_obj, 1);
}
else
{
LOG_E("RT_DEVICE_CTRL_RTC_SET_ALARM error!!");
return -RT_ERROR;
}
LOG_D("SET_ALARM %d:%d:%d",alarm->tm_hour,
alarm->tm_min, alarm->tm_sec);
return RT_EOK;
#else
return -RT_ERROR;
#endif
}
#ifdef RT_USING_ALARM
void rtc_alarm_callback(void)
{
rt_interrupt_enter();
rt_alarm_update(0, 0);
rt_interrupt_leave();
}
#endif
static const struct rt_rtc_ops _rtc_ops =
{
_rtc_init,
_rtc_get_secs,
_rtc_set_secs,
RT_NULL,
RT_NULL,
_rtc_get_alarm,
_rtc_set_alarm,
ifx_rtc_get_timeval,
RT_NULL,
};
@ -153,9 +215,9 @@ static int rt_hw_rtc_init(void)
{
rt_err_t result = RT_EOK;
ifx32_rtc_dev.ops = &_rtc_ops;
ifx32_rtc_dev.rtc_dev.ops = &_rtc_ops;
if (rt_hw_rtc_register(&ifx32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL) != RT_EOK)
if (rt_hw_rtc_register(&(ifx32_rtc_dev.rtc_dev), "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL) != RT_EOK)
{
LOG_E("rtc init failed");
result = -RT_ERROR;

4
bsp/Infineon/libraries/HAL_Drivers/drv_sdcard.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,7 +15,7 @@
#ifdef BSP_USING_SDCARD
//#define DRV_DEBUG
/*#define DRV_DEBUG*/
#define LOG_TAG "drv.sdio"
#include <drv_log.h>

4
bsp/Infineon/libraries/HAL_Drivers/drv_soft_i2c.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -13,7 +13,7 @@
#ifdef RT_USING_I2C
//#define DRV_DEBUG
/*#define DRV_DEBUG*/
#define LOG_TAG "drv.i2c"
#include <drv_log.h>

2
bsp/Infineon/libraries/HAL_Drivers/drv_soft_i2c.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

7
bsp/Infineon/libraries/HAL_Drivers/drv_spi.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -13,7 +13,7 @@
#ifdef RT_USING_SPI
//#define DRV_DEBUG
/*#define DRV_DEBUG*/
#define DBG_TAG "drv.spi"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
@ -60,7 +60,8 @@ static struct ifx_spi_handle spi_bus_obj[] =
#endif
};
static struct ifx_spi spi_config[sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0])] = {0};
static struct ifx_spi spi_config[sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0])] =
{0};
/* private rt-thread spi ops function */
static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);

2
bsp/Infineon/libraries/HAL_Drivers/drv_spi.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

5
bsp/Infineon/libraries/HAL_Drivers/drv_uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -64,7 +64,8 @@ static struct ifx_uart_config uart_config[] =
#endif
};
static struct ifx_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
static struct ifx_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] =
{0};
static void uart_isr(struct rt_serial_device *serial)
{

2
bsp/Infineon/libraries/HAL_Drivers/drv_uart.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

4
bsp/Infineon/libraries/HAL_Drivers/drv_wdt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -12,7 +12,7 @@
#ifdef RT_USING_WDT
//#define DRV_DEBUG
/*#define DRV_DEBUG*/
#define LOG_TAG "drv.wdt"
#include <drv_log.h>

78
bsp/Infineon/libraries/HAL_Drivers/eth_config.h Normal file
View File

@ -0,0 +1,78 @@
#ifndef CY_ETH_USER_CONFIG
#define CY_ETH_USER_CONFIG
#include "cy_ethif.h"
#include "cy_ephy.h"
/*#include "cy_ecm.h"*/
#define CY_GIG_ETH_TYPE ETH1
#define CY_GIG_ETH_INSTANCE_NUM (1)
#define ETH_REG_BASE CY_GIG_ETH_TYPE
#define CY_GIG_ETH_TX_CLK_PORT GPIO_PRT26
#define CY_GIG_ETH_TX_CLK_PIN 2
#define CY_GIG_ETH_TX_CLK_PIN_MUX P26_2_ETH1_TX_CLK
#define CY_GIG_ETH_TX_CTL_PORT GPIO_PRT26
#define CY_GIG_ETH_TX_CTL_PIN 1
#define CY_GIG_ETH_TX_CTL_PIN_MUX P26_1_ETH1_TX_CTL
#define CY_GIG_ETH_TD0_PORT GPIO_PRT26
#define CY_GIG_ETH_TD0_PIN 3
#define CY_GIG_ETH_TD0_PIN_MUX P26_3_ETH1_TXD0
#define CY_GIG_ETH_TD1_PORT GPIO_PRT26
#define CY_GIG_ETH_TD1_PIN 4
#define CY_GIG_ETH_TD1_PIN_MUX P26_4_ETH1_TXD1
#define CY_GIG_ETH_TD2_PORT GPIO_PRT26
#define CY_GIG_ETH_TD2_PIN 5
#define CY_GIG_ETH_TD2_PIN_MUX P26_5_ETH1_TXD2
#define CY_GIG_ETH_TD3_PORT GPIO_PRT26
#define CY_GIG_ETH_TD3_PIN 6
#define CY_GIG_ETH_TD3_PIN_MUX P26_6_ETH1_TXD3
#define CY_GIG_ETH_RX_CLK_PORT GPIO_PRT27
#define CY_GIG_ETH_RX_CLK_PIN 4
#define CY_GIG_ETH_RX_CLK_PIN_MUX P27_4_ETH1_RX_CLK
#define CY_GIG_ETH_RX_CTL_PORT GPIO_PRT27
#define CY_GIG_ETH_RX_CTL_PIN 3
#define CY_GIG_ETH_RX_CTL_PIN_MUX P27_3_ETH1_RX_CTL
#define CY_GIG_ETH_RD0_PORT GPIO_PRT26
#define CY_GIG_ETH_RD0_PIN 7
#define CY_GIG_ETH_RD0_PIN_MUX P26_7_ETH1_RXD0
#define CY_GIG_ETH_RD1_PORT GPIO_PRT27
#define CY_GIG_ETH_RD1_PIN 0
#define CY_GIG_ETH_RD1_PIN_MUX P27_0_ETH1_RXD1
#define CY_GIG_ETH_RD2_PORT GPIO_PRT27
#define CY_GIG_ETH_RD2_PIN 1
#define CY_GIG_ETH_RD2_PIN_MUX P27_1_ETH1_RXD2
#define CY_GIG_ETH_RD3_PORT GPIO_PRT27
#define CY_GIG_ETH_RD3_PIN 2
#define CY_GIG_ETH_RD3_PIN_MUX P27_2_ETH1_RXD3
#define CY_GIG_ETH_MDC_PORT GPIO_PRT27
#define CY_GIG_ETH_MDC_PIN 6
#define CY_GIG_ETH_MDC_PIN_MUX P27_6_ETH1_MDC
#define CY_GIG_ETH_MDIO_PORT GPIO_PRT27
#define CY_GIG_ETH_MDIO_PIN 5
#define CY_GIG_ETH_MDIO_PIN_MUX P27_5_ETH1_MDIO
#define CY_GIG_ETH_REF_CLK_PORT GPIO_PRT26
#define CY_GIG_ETH_REF_CLK_PIN 0
#define CY_GIG_ETH_REF_CLK_PIN_MUX P26_0_ETH1_REF_CLK
/* Setup IRQ source for 0, 1, and 2 priority queue */
#define CY_GIG_ETH_IRQN0 eth_1_interrupt_eth_0_IRQn
#define CY_GIG_ETH_IRQN1 eth_1_interrupt_eth_1_IRQn
#define CY_GIG_ETH_IRQN2 eth_1_interrupt_eth_2_IRQn
#endif /* CY_ETH_USER_CONFIG */

2
bsp/Infineon/libraries/HAL_Drivers/uart_config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

5
bsp/Infineon/xmc7200-kit_xmc7200_evk/board/Kconfig
View File

@ -37,6 +37,11 @@ menu "On-chip Peripheral Drivers"
range 0 7
default 3
endif
config BSP_USING_ETH
bool "Enable ETH"
select RT_USING_ETH
default n
endmenu

11
bsp/airm2m/air105/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,8 +7,11 @@
* Date Author Notes
* 2022-02-22 airm2m first version
*/
#include "board.h"
#include "drv_common.h"
#include "drv_gpio.h"
#include "drv_usart_v2.h"
uint32_t SystemCoreClock;
extern const uint32_t __isr_start_address;
@ -38,7 +41,7 @@ void SystemInit(void)
__enable_irq();
}
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
SystemCoreClock = HSE_VALUE * (((SYSCTRL->FREQ_SEL & SYSCTRL_FREQ_SEL_XTAL_Mask) >> SYSCTRL_FREQ_SEL_XTAL_Pos) + 1);
}
@ -56,7 +59,7 @@ void rt_hw_board_init(void)
rt_hw_systick_init();
DMA_GlobalInit();
Uart_GlobalInit();
DMA_TakeStream(DMA1_STREAM_1);//for qspi
DMA_TakeStream(DMA1_STREAM_1);/* for qspi */
CoreTick_Init();
#ifdef RT_USING_PIN
rt_hw_pin_init();

4
bsp/airm2m/air105/libraries/HAL_Driver/Inc/core_irq.h
View File

@ -21,14 +21,14 @@
#ifndef __CORE_IRQ_H__
#define __CORE_IRQ_H__
#include <stdint.h>
/**
* @brief 设置中断回调函数
*
* @param Irq 中断号 0~IRQ_LINE_MAX
* @param Handler 中断回调函数，如 void Irq_Handler(uint32_t IrqLine, void *pData); 可以多个中断号对应1个中断函数，回调时传入中断号和用户数据
*/
void ISR_SetHandler(int32_t Irq, void *Handler);
void ISR_SetHandler(int32_t Irq, void *Handler, void *pData);
/**
* @brief 设置中断优先级
*

16
bsp/airm2m/air105/libraries/HAL_Driver/Src/core_dma.c
View File

@ -18,11 +18,11 @@
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "core_irq.h"
#include "user.h"
typedef struct
{
const DMA_TypeDef *RegBase;
DMA_TypeDef *RegBase;
const uint32_t Index;
CBFuncEx_t CB;
void *pData;
@ -65,17 +65,17 @@ typedef struct
/************ operation definition for DMA DMA_CFG_L REGISTER ************/
#define DMA_CFG_HS_SEL_SRC_Pos (11)
#define DMA_CFG_HS_SEL_SRC_Mask (0x01U<<DMA_CFG_HS_SEL_SRC_Pos)//0 HARD 1 SOFT
#define DMA_CFG_HS_SEL_SRC_Mask (0x01U<<DMA_CFG_HS_SEL_SRC_Pos)/*0 HARD 1 SOFT*/
#define DMA_CFG_HS_SEL_DST_Pos (10)
#define DMA_CFG_HS_SEL_DST_Mask (0x01U<<DMA_CFG_HS_SEL_DST_Pos)
/************ operation definition for DMA DMA_CFG_H REGISTER ************/
#define DMA_CFG_DEST_PER_Pos (11)
#define DMA_CFG_DEST_PER_Mask (0x07U<<DMA_CFG_DEST_PER_Pos)//need write current channel num
#define DMA_CFG_DEST_PER_Mask (0x07U<<DMA_CFG_DEST_PER_Pos)/*need write current channel num*/
#define DMA_CFG_SRC_PER_Pos (7)
#define DMA_CFG_SRC_PER_Mask (0x07U<<DMA_CFG_SRC_PER_Pos)//need write current channel num
#define DMA_CFG_SRC_PER_Mask (0x07U<<DMA_CFG_SRC_PER_Pos)/*need write current channel num*/
/************ operation definition for DMA DMA_LLP_L REGISTER ************/
#define DMAC_LLP_NEXT_LLI_MSK (0x3)
@ -212,7 +212,7 @@ int DMA_ConfigStream(uint8_t Stream, void *Config)
(DMA_InitStruct->DMA_PeripheralDataSize << DMA_CTL_DST_TR_WIDTH_Pos);
hwDMAChannal[Stream].TxDir = 1;
// hwDMA->CFG_L = (1 << 18);
/* hwDMA->CFG_L = (1 << 18); */
hwDMA->CFG_L = 0;
break;
default:
@ -333,7 +333,7 @@ uint32_t DMA_GetDataLength(uint8_t Stream, uint32_t FirstAddress)
static void DMA_IrqHandle(int32_t IrqLine, void *pData)
{
uint32_t i;
// DBG("%x", DMA->StatusTfr_L);
/* DBG("%x", DMA->StatusTfr_L); */
if (DMA->StatusInt_L & (1 << 0))
{
for(i = 0; i < DMA_STREAM_QTY; i++)
@ -352,7 +352,7 @@ static void DMA_IrqHandle(int32_t IrqLine, void *pData)
if (DMA->StatusErr_L & (1 << i))
{
DMA->ClearErr_L = (1 << i);
hwDMAChannal[i].CB(hwDMAChannal[i].pData, 0xffffffff);
hwDMAChannal[i].CB(hwDMAChannal[i].pData, (void *)0xffffffff);
}
}
}

6
bsp/airm2m/air105/libraries/rt_drivers/drv_common.h
View File

@ -29,6 +29,12 @@ void _Error_Handler(char *s, int num);
#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
/**
* This function is mainly used for SysTick initialization
*
*/
void rt_hw_systick_init(void);
#ifdef __cplusplus
}
#endif

9
bsp/airm2m/air105/makesoc.py
View File

@ -1,9 +1,7 @@
import os
import sys
import shutil
import urllib
import urllib.request
out_path='./'
bin_file_name='rtthread.bin'
pack_path='./pack'
@ -17,13 +15,14 @@ if __name__=='__main__':
os.remove(out_file+'.soc')
if not os.path.exists(pack_path+'/bootloader.bin'):
urllib.urlretrieve("http://cdndownload.openluat.com/rt-thread/airm2m/air105/bootloader.bin", pack_path+'/bootloader.bin')
urllib.request.urlretrieve("http://cdndownload.openluat.com/rt-thread/airm2m/air105/bootloader.bin", pack_path + '/bootloader.bin')
if not os.path.exists(pack_path+'/soc_download.exe'):
urllib.urlretrieve("http://cdndownload.openluat.com/rt-thread/airm2m/air105/soc_download.exe", pack_path+'/soc_download.exe')
urllib.request.urlretrieve("http://cdndownload.openluat.com/rt-thread/airm2m/air105/bootloader.bin", pack_path + '/bootloader.bin')
shutil.copy(out_path+bin_file_name, pack_path+'/'+bin_file_name)
shutil.make_archive(out_file, 'zip', root_dir=pack_path)
os.remove(pack_path+'/'+bin_file_name)
os.rename(out_file+'.zip',out_file+'.soc')
print('end')

2
bsp/allwinner_tina/libcpu/interrupt.c
View File

@ -14,7 +14,7 @@
#include "interrupt.h"
extern rt_uint32_t rt_interrupt_nest;
extern rt_atomic_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;

3
bsp/apm32/apm32f030r8-miniboard/applications/main.c
View File

@ -17,11 +17,10 @@
int main(void)
{
int count = 1;
/* set LED2 pin mode to output */
rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
while (count++)
while (1)
{
rt_pin_write(LED2_PIN, PIN_HIGH);
rt_thread_mdelay(500);

3
bsp/apm32/apm32f051r8-evalboard/applications/main.c
View File

@ -17,11 +17,10 @@
int main(void)
{
int count = 1;
/* set LED2 pin mode to output */
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
while (count++)
while (1)
{
rt_pin_write(LED1_PIN, PIN_HIGH);
rt_thread_mdelay(500);

2
bsp/asm9260t/platform/interrupt.c
View File

@ -15,7 +15,7 @@
#define MAX_HANDLERS (64)
extern rt_uint32_t rt_interrupt_nest;
extern rt_atomic_t rt_interrupt_nest;
/* exception and interrupt handler table */
struct rt_irq_desc irq_desc[MAX_HANDLERS];

349
bsp/at32/libraries/rt_drivers/drv_pwm.c
View File

@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2022-05-16 shelton first version
* 2024-09-24 shelton update driver
*/
#include "drv_common.h"
@ -19,8 +20,8 @@
#include <drv_log.h>
#define MAX_PERIOD 65535
struct rt_device_pwm pwm_device;
#define MIN_PERIOD 3
#define MIN_PULSE 2
struct at32_pwm
{
@ -154,6 +155,54 @@ static void tmr_pclk_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
}
}
static rt_err_t at32_hw_pwm_init(struct at32_pwm *instance)
{
tmr_output_config_type tmr_oc_config_struct;
tmr_type *tmr_x = instance->tmr_x;
at32_msp_tmr_init(tmr_x);
tmr_base_init(tmr_x, 0, 0);
tmr_clock_source_div_set(tmr_x, TMR_CLOCK_DIV1);
/* pwm mode configuration */
tmr_output_default_para_init(&tmr_oc_config_struct);
/* config pwm mode */
tmr_oc_config_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
/* config tmr pwm output */
if(instance->channel & 0x01)
{
tmr_output_channel_config(tmr_x, TMR_SELECT_CHANNEL_1, &tmr_oc_config_struct);
tmr_output_channel_buffer_enable(tmr_x, TMR_SELECT_CHANNEL_1, TRUE);
}
if(instance->channel & 0x02)
{
tmr_output_channel_config(tmr_x, TMR_SELECT_CHANNEL_2, &tmr_oc_config_struct);
tmr_output_channel_buffer_enable(tmr_x, TMR_SELECT_CHANNEL_2, TRUE);
}
if(instance->channel & 0x04)
{
tmr_output_channel_config(tmr_x, TMR_SELECT_CHANNEL_3, &tmr_oc_config_struct);
tmr_output_channel_buffer_enable(tmr_x, TMR_SELECT_CHANNEL_3, TRUE);
}
if(instance->channel & 0x08)
{
tmr_output_channel_config(tmr_x, TMR_SELECT_CHANNEL_4, &tmr_oc_config_struct);
tmr_output_channel_buffer_enable(tmr_x, TMR_SELECT_CHANNEL_4, TRUE);
}
/* enable output */
tmr_output_enable(tmr_x, TRUE);
/* enable overflow request */
tmr_overflow_request_source_set(tmr_x, TRUE);
return RT_EOK;
}
static rt_err_t drv_pwm_enable(tmr_type* tmr_x, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
/* get the value of channel */
@ -243,10 +292,9 @@ static rt_err_t drv_pwm_enable(tmr_type* tmr_x, struct rt_pwm_configuration *con
static rt_err_t drv_pwm_get(tmr_type* tmr_x, struct rt_pwm_configuration *configuration)
{
crm_clocks_freq_type clocks_struct;
rt_uint32_t pr, div, c1dt, c2dt, c3dt, c4dt;
rt_uint32_t pr, div, c1dt, c2dt, c3dt, c4dt, tmr_clock;
rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0;
rt_uint32_t channel = configuration->channel;
rt_uint64_t tmr_clock;
pr = tmr_x->pr;
div = tmr_x->div;
@ -256,7 +304,6 @@ static rt_err_t drv_pwm_get(tmr_type* tmr_x, struct rt_pwm_configuration *config
c4dt = tmr_x->c4dt;
tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
crm_clocks_freq_get(&clocks_struct);
if(
@ -303,17 +350,11 @@ static rt_err_t drv_pwm_get(tmr_type* tmr_x, struct rt_pwm_configuration *config
static rt_err_t drv_pwm_set(tmr_type* tmr_x, struct rt_pwm_configuration *configuration)
{
crm_clocks_freq_type clocks_struct;
tmr_output_config_type tmr_oc_config_struct;
tmr_channel_select_type channel_select;
rt_uint32_t period, pulse, channel, tmr_clock;
rt_uint32_t period, pulse, channel, psc, tmr_clock;
rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0;
rt_uint64_t psc;
/* init timer pin and enable clock */
at32_msp_tmr_init(tmr_x);
tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
crm_clocks_freq_get(&clocks_struct);
if(
@ -347,33 +388,161 @@ static rt_err_t drv_pwm_set(tmr_type* tmr_x, struct rt_pwm_configuration *config
period = (unsigned long long)configuration->period * tmr_clock / 1000ULL;;
psc = period / MAX_PERIOD + 1;
period = period / psc;
tmr_div_value_set(tmr_x, psc - 1);
if(period < MIN_PERIOD)
{
period = MIN_PERIOD;
}
tmr_period_value_set(tmr_x, period - 1);
/* calculate pulse width */
pulse = (unsigned long long)configuration->pulse * tmr_clock / psc / 1000ULL;
if(pulse < MIN_PULSE)
{
pulse = MIN_PULSE;
}
else if(pulse >= period)
{
pulse = period + 1;
}
/* get channel parameter */
channel = configuration->channel;
if(channel == 1)
{
channel_select = TMR_SELECT_CHANNEL_1;
}
else if(channel == 2)
{
channel_select = TMR_SELECT_CHANNEL_2;
}
else if(channel == 3)
{
channel_select = TMR_SELECT_CHANNEL_3;
}
else if(channel == 4)
{
channel_select = TMR_SELECT_CHANNEL_4;
}
tmr_channel_value_set(tmr_x, channel_select, pulse);
/* if you want the pwm setting to take effect immediately,
please uncommon the following code, but it will cause the last pwm cycle not complete. */
//tmr_counter_value_set(tmr_x, 0);
//tmr_x->swevt_bit.ovfswtr = TRUE;
return RT_EOK;
}
static rt_err_t drv_pwm_set_period(tmr_type* tmr_x, struct rt_pwm_configuration *configuration)
{
crm_clocks_freq_type clocks_struct;
rt_uint32_t period, psc, tmr_clock;
rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0;
tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
crm_clocks_freq_get(&clocks_struct);
if(
#if defined (TMR1)
(tmr_x == TMR1)
#endif
#if defined (TMR8)
|| (tmr_x == TMR8)
#endif
#if defined (TMR9)
|| (tmr_x == TMR9)
#endif
#if defined (TMR10)
|| (tmr_x == TMR10)
#endif
#if defined (TMR11)
|| (tmr_x == TMR11)
#endif
)
{
tmr_clock = clocks_struct.apb2_freq * pclk2_doubler;
}
else
{
tmr_clock = clocks_struct.apb1_freq * pclk1_doubler;
}
/* convert nanosecond to frequency and duty cycle. */
tmr_clock /= 1000000UL;
/* calculate pwm period */
period = (unsigned long long)configuration->period * tmr_clock / 1000ULL;;
psc = period / MAX_PERIOD + 1;
period = period / psc;
tmr_div_value_set(tmr_x, psc - 1);
if(period < MIN_PERIOD)
{
period = MIN_PERIOD;
}
tmr_period_value_set(tmr_x, period - 1);
return RT_EOK;
}
static rt_err_t drv_pwm_set_pulse(tmr_type* tmr_x, struct rt_pwm_configuration *configuration)
{
crm_clocks_freq_type clocks_struct;
tmr_channel_select_type channel_select;
rt_uint32_t period, pulse, channel, psc, tmr_clock;
rt_uint32_t pclk1_doubler = 0, pclk2_doubler = 0;
tmr_pclk_get(&pclk1_doubler, &pclk2_doubler);
crm_clocks_freq_get(&clocks_struct);
if(
#if defined (TMR1)
(tmr_x == TMR1)
#endif
#if defined (TMR8)
|| (tmr_x == TMR8)
#endif
#if defined (TMR9)
|| (tmr_x == TMR9)
#endif
#if defined (TMR10)
|| (tmr_x == TMR10)
#endif
#if defined (TMR11)
|| (tmr_x == TMR11)
#endif
)
{
tmr_clock = clocks_struct.apb2_freq * pclk2_doubler;
}
else
{
tmr_clock = clocks_struct.apb1_freq * pclk1_doubler;
}
/* convert nanosecond to frequency and duty cycle. */
tmr_clock /= 1000000UL;
/* calculate pwm period */
period = (unsigned long long)configuration->period * tmr_clock / 1000ULL;;
psc = period / MAX_PERIOD + 1;
/* calculate pulse width */
pulse = (unsigned long long)configuration->pulse * tmr_clock / psc / 1000ULL;
if(pulse < MIN_PULSE)
{
pulse = MIN_PULSE;
}
else if(pulse >= period)
{
pulse = period + 1;
}
/* get channel parameter */
channel = configuration->channel;
/* tmr base init */
tmr_base_init(tmr_x, period - 1, psc - 1);
tmr_clock_source_div_set(tmr_x, TMR_CLOCK_DIV1);
/* pwm mode configuration */
tmr_output_default_para_init(&tmr_oc_config_struct);
/* config pwm mode */
tmr_oc_config_struct.oc_mode = TMR_OUTPUT_CONTROL_PWM_MODE_A;
if (!configuration->complementary)
{
tmr_oc_config_struct.oc_idle_state = FALSE;
tmr_oc_config_struct.oc_output_state = FALSE;
tmr_oc_config_struct.oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
}
else
{
tmr_oc_config_struct.occ_idle_state = FALSE;
tmr_oc_config_struct.occ_output_state = FALSE;
tmr_oc_config_struct.occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
}
if(channel == 1)
{
channel_select = TMR_SELECT_CHANNEL_1;
@ -391,14 +560,7 @@ static rt_err_t drv_pwm_set(tmr_type* tmr_x, struct rt_pwm_configuration *config
channel_select = TMR_SELECT_CHANNEL_4;
}
/* config tmr pwm output */
tmr_output_channel_config(tmr_x, channel_select, &tmr_oc_config_struct);
tmr_output_channel_buffer_enable(tmr_x, channel_select, TRUE);
tmr_channel_value_set(tmr_x, channel_select, pulse);
/* enable tmr period buffer */
tmr_period_buffer_enable(tmr_x, TRUE);
/* enable output */
tmr_output_enable(tmr_x, TRUE);
return RT_EOK;
}
@ -410,16 +572,16 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
switch (cmd)
{
case PWMN_CMD_ENABLE:
configuration->complementary = RT_TRUE;
case PWM_CMD_ENABLE:
return drv_pwm_enable(tmr_x, configuration, RT_TRUE);
case PWMN_CMD_DISABLE:
configuration->complementary = RT_FALSE;
case PWM_CMD_DISABLE:
return drv_pwm_enable(tmr_x, configuration, RT_FALSE);
case PWM_CMD_SET:
return drv_pwm_set(tmr_x, configuration);
case PWM_CMD_SET_PERIOD:
return drv_pwm_set_period(tmr_x, configuration);
case PWM_CMD_SET_PULSE:
return drv_pwm_set_pulse(tmr_x, configuration);
case PWM_CMD_GET:
return drv_pwm_get(tmr_x, configuration);
default:
@ -430,118 +592,118 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
static void pwm_get_channel(void)
{
#ifdef BSP_USING_PWM1_CH1
at32_pwm_obj[PWM1_INDEX].channel = 1;
at32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM1_CH2
at32_pwm_obj[PWM1_INDEX].channel = 2;
at32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM1_CH3
at32_pwm_obj[PWM1_INDEX].channel = 3;
at32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM1_CH4
at32_pwm_obj[PWM1_INDEX].channel = 4;
at32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM2_CH1
at32_pwm_obj[PWM2_INDEX].channel = 1;
at32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM2_CH2
at32_pwm_obj[PWM2_INDEX].channel = 2;
at32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM2_CH3
at32_pwm_obj[PWM2_INDEX].channel = 3;
at32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM2_CH4
at32_pwm_obj[PWM2_INDEX].channel = 4;
at32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM3_CH1
at32_pwm_obj[PWM3_INDEX].channel = 1;
at32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM3_CH2
at32_pwm_obj[PWM3_INDEX].channel = 2;
at32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM3_CH3
at32_pwm_obj[PWM3_INDEX].channel = 3;
at32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM3_CH4
at32_pwm_obj[PWM3_INDEX].channel = 4;
at32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM4_CH1
at32_pwm_obj[PWM4_INDEX].channel = 1;
at32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM4_CH2
at32_pwm_obj[PWM4_INDEX].channel = 2;
at32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM4_CH3
at32_pwm_obj[PWM4_INDEX].channel = 3;
at32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM4_CH4
at32_pwm_obj[PWM4_INDEX].channel = 4;
at32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM5_CH1
at32_pwm_obj[PWM5_INDEX].channel = 1;
at32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM5_CH2
at32_pwm_obj[PWM5_INDEX].channel = 2;
at32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM5_CH3
at32_pwm_obj[PWM5_INDEX].channel = 3;
at32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM5_CH4
at32_pwm_obj[PWM5_INDEX].channel = 4;
at32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM6_CH1
at32_pwm_obj[PWM6_INDEX].channel = 1;
at32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM6_CH2
at32_pwm_obj[PWM6_INDEX].channel = 2;
at32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM6_CH3
at32_pwm_obj[PWM6_INDEX].channel = 3;
at32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM6_CH4
at32_pwm_obj[PWM6_INDEX].channel = 4;
at32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM7_CH1
at32_pwm_obj[PWM7_INDEX].channel = 1;
at32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM7_CH2
at32_pwm_obj[PWM7_INDEX].channel = 2;
at32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM7_CH3
at32_pwm_obj[PWM7_INDEX].channel = 3;
at32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM7_CH4
at32_pwm_obj[PWM7_INDEX].channel = 4;
at32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM8_CH1
at32_pwm_obj[PWM8_INDEX].channel = 1;
at32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM8_CH2
at32_pwm_obj[PWM8_INDEX].channel = 2;
at32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM8_CH3
at32_pwm_obj[PWM8_INDEX].channel = 3;
at32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM8_CH4
at32_pwm_obj[PWM8_INDEX].channel = 4;
at32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM9_CH1
at32_pwm_obj[PWM9_INDEX].channel = 1;
at32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM9_CH2
at32_pwm_obj[PWM9_INDEX].channel = 2;
at32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
#endif
#ifdef BSP_USING_PWM9_CH3
at32_pwm_obj[PWM9_INDEX].channel = 3;
at32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
#endif
#ifdef BSP_USING_PWM9_CH4
at32_pwm_obj[PWM9_INDEX].channel = 4;
at32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
#endif
#ifdef BSP_USING_PWM12_CH1
at32_pwm_obj[PWM12_INDEX].channel = 1;
at32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
#endif
#ifdef BSP_USING_PWM12_CH2
at32_pwm_obj[PWM12_INDEX].channel = 2;
at32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
#endif
}
@ -554,17 +716,26 @@ static int rt_hw_pwm_init(void)
for(i = 0; i < sizeof(at32_pwm_obj) / sizeof(at32_pwm_obj[0]); i++)
{
if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tmr_x) == RT_EOK)
if(at32_hw_pwm_init(&at32_pwm_obj[i]) != RT_EOK)
{
LOG_D("%s register success", at32_pwm_obj[i].name);
LOG_E("%s init failed", at32_pwm_obj[i].name);
result = -RT_ERROR;
goto __exit;
}
else
{
LOG_D("%s register failed", at32_pwm_obj[i].name);
result = -RT_ERROR;
if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tmr_x) == RT_EOK)
{
LOG_D("%s register success", at32_pwm_obj[i].name);
}
else
{
LOG_D("%s register failed", at32_pwm_obj[i].name);
result = -RT_ERROR;
}
}
}
__exit:
return result;
}

2
bsp/at91/at91sam9260/platform/interrupt.c
View File

@ -13,7 +13,7 @@
#include "interrupt.h"
#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
extern rt_uint32_t rt_interrupt_nest;
extern rt_atomic_t rt_interrupt_nest;
/* exception and interrupt handler table */
struct rt_irq_desc irq_desc[MAX_HANDLERS];

2
bsp/at91/at91sam9g45/platform/interrupt.c
View File

@ -15,7 +15,7 @@
#define AIC_IRQS 32
#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
extern rt_uint32_t rt_interrupt_nest;
extern rt_atomic_t rt_interrupt_nest;
/* exception and interrupt handler table */
struct rt_irq_desc irq_desc[MAX_HANDLERS];

2
bsp/bf533/rtconfig.h
View File

@ -31,7 +31,7 @@
//#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 8
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 1000
#define RT_TICK_PER_SECOND 1000
/* SECTION: IPC */
/* Using Semaphore */

2
bsp/bluetrum/ab32vg1-ab-prougen/board/board.c
View File

@ -27,7 +27,7 @@ typedef void (*spiflash_init_func)(uint8_t sf_read, uint8_t dummy);
static struct rt_mutex mutex_spiflash = {0};
static struct rt_mutex mutex_cache = {0};
extern volatile rt_uint8_t rt_interrupt_nest;
extern volatile rt_atomic_t rt_interrupt_nest;
extern uint32_t __heap_start, __heap_end;
#ifdef RT_USING_CONSOLE

2
bsp/cvitek/c906_little/board/interrupt.c
View File

@ -15,7 +15,7 @@
#include "encoding.h"
#include "mmio.h"
extern rt_uint32_t rt_interrupt_nest;
extern rt_atomic_t rt_interrupt_nest;
extern rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
extern rt_uint32_t rt_thread_switch_interrupt_flag;

6
bsp/cvitek/drivers/drv_pinmux.c
View File

@ -116,7 +116,10 @@ struct fmux pinmux_array[] = {
FS_PINMUX(SD1_CLK),
FS_PINMUX(PWM0_BUCK),
FS_PINMUX(ADC1),
FS_PINMUX(PKG_TYPE0),
FS_PINMUX(USB_VBUS_DET),
FS_PINMUX(PKG_TYPE1),
FS_PINMUX(PKG_TYPE2),
FS_PINMUX(MUX_SPI1_MISO),
FS_PINMUX(MUX_SPI1_MOSI),
FS_PINMUX(MUX_SPI1_CS),
@ -142,9 +145,6 @@ struct fmux pinmux_array[] = {
FS_PINMUX(PAD_MIPI_TXP1),
FS_PINMUX(PAD_MIPI_TXM0),
FS_PINMUX(PAD_MIPI_TXP0),
FS_PINMUX(PKG_TYPE0),
FS_PINMUX(PKG_TYPE1),
FS_PINMUX(PKG_TYPE2),
FS_PINMUX(PAD_AUD_AINL_MIC),
FS_PINMUX(PAD_AUD_AINR_MIC),
FS_PINMUX(PAD_AUD_AOUTL),

78
bsp/cvitek/drivers/drv_pinmux.h
View File

@ -12,22 +12,29 @@
/**
* @brief Function Selection Type
*
* FIXME: At present, we only define the ones we will use,
* not all of them. We will need to add them later.
*/
typedef enum _fs_type
{
fs_none = 0,
ADC1,
ADC2,
ADC3,
AUX0,
AUX1,
AUX2,
CAM_HS0,
CAM_MCLK0,
CAM_MCLK1,
CAM_PD0,
CAM_PD1,
CAM_RST0,
CAM_VS0,
CLK25M,
CLK32K,
CR_4WTDI,
CR_4WTDO,
CV_SCL0,
CV_SDA0,
DBG_0,
DBG_1,
DBG_2,
@ -49,6 +56,10 @@ typedef enum _fs_type
DBG_19,
EMMC_CLK,
EMMC_CMD,
EMMC_DAT0,
EMMC_DAT1,
EMMC_DAT2,
EMMC_DAT3,
EMMC_DAT_0,
EMMC_DAT_1,
EMMC_DAT_2,
@ -56,6 +67,8 @@ typedef enum _fs_type
EMMC_RSTN,
EPHY_LNK_LED,
EPHY_SPD_LED,
GPIO_RTX,
GPIO_ZQ,
IIC0_SCL,
IIC0_SDA,
IIC1_SCL,
@ -95,9 +108,41 @@ typedef enum _fs_type
MUX_SPI1_MISO,
MUX_SPI1_MOSI,
MUX_SPI1_SCK,
PAD_AUD_AINL_MIC,
PAD_AUD_AINR_MIC,
PAD_AUD_AOUTL,
PAD_AUD_AOUTR,
PAD_ETH_RXM,
PAD_ETH_RXP,
PAD_ETH_TXM,
PAD_ETH_TXP,
PAD_MIPIRX0N,
PAD_MIPIRX0P,
PAD_MIPIRX1N,
PAD_MIPIRX1P,
PAD_MIPIRX2N,
PAD_MIPIRX2P,
PAD_MIPIRX3N,
PAD_MIPIRX3P,
PAD_MIPIRX4N,
PAD_MIPIRX4P,
PAD_MIPIRX5N,
PAD_MIPIRX5P,
PAD_MIPI_TXM0,
PAD_MIPI_TXM1,
PAD_MIPI_TXM2,
PAD_MIPI_TXM3,
PAD_MIPI_TXM4,
PAD_MIPI_TXP0,
PAD_MIPI_TXP1,
PAD_MIPI_TXP2,
PAD_MIPI_TXP3,
PAD_MIPI_TXP4,
PKG_TYPE0,
PKG_TYPE1,
PKG_TYPE2,
PTEST,
PWM0_BUCK,
PWM_0,
PWM_1,
PWM_2,
@ -115,6 +160,9 @@ typedef enum _fs_type
PWM_14,
PWM_15,
PWR_BUTTON1,
PWR_GPIO0,
PWR_GPIO1,
PWR_GPIO2,
PWR_GPIO_0,
PWR_GPIO_1,
PWR_GPIO_2,
@ -195,12 +243,22 @@ typedef enum _fs_type
RMII0_TXD1,
RMII0_TXEN,
RSTN,
SD0_CD,
SD0_CLK,
SD0_CMD,
SD0_D0,
SD0_D1,
SD0_D2,
SD0_D3,
SD0_PWR_EN,
SD1_CLK,
SD1_CMD,
SD1_D0,
SD1_D1,
SD1_D2,
SD1_D3,
SD1_GPIO0,
SD1_GPIO1,
SDIO0_CD,
SDIO0_CLK,
SDIO0_CMD,
@ -237,6 +295,7 @@ typedef enum _fs_type
SPINOR_MOSI,
SPINOR_SCK,
SPINOR_WP_X,
SPK_EN,
UART0_RX,
UART0_TX,
UART1_CTS,
@ -304,6 +363,18 @@ typedef enum _fs_type
VI2_D_5,
VI2_D_6,
VI2_D_7,
VIVO_CLK,
VIVO_D0,
VIVO_D1,
VIVO_D2,
VIVO_D3,
VIVO_D4,
VIVO_D5,
VIVO_D6,
VIVO_D7,
VIVO_D8,
VIVO_D9,
VIVO_D10,
VO_CLK0,
VO_CLK1,
VO_D_0,
@ -429,6 +500,7 @@ typedef enum _fs_type
XGPIOC_23,
XGPIOC_24,
XGPIOC_25,
XTAL_XIN,
} fs_type;
/**

2
bsp/dm365/platform/interrupt.c
View File

@ -15,7 +15,7 @@
#define MAX_HANDLERS 64
extern rt_uint32_t rt_interrupt_nest;
extern rt_atomic_t rt_interrupt_nest;
struct rt_irq_desc irq_desc[MAX_HANDLERS];

2
bsp/efm32/rtconfig.h
View File

@ -62,7 +62,7 @@
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO (4)
#define RT_TIMER_THREAD_STACK_SIZE (512)
#define RT_TIMER_TICK_PER_SECOND (10)
#define RT_TICK_PER_SECOND (10)
/* SECTION: IPC */
/* Using Semaphore*/

34
bsp/essemi/es32f0654/board/linker_scripts/link.icf Normal file
View File

@ -0,0 +1,34 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x0003E000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00038000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x400;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

155
bsp/essemi/es32f0654/board/linker_scripts/link.lds Normal file
View File

@ -0,0 +1,155 @@
/*
*****************************************************************************
**
** File : es32f0654.ld
**
** Abstract : Linker script for ES32F0654 Device with
** 256K-Byte FLASH, 32K-Byte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20008000; /* end of 32K RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00008000, LENGTH = 224K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
MEMORY_B1 (rx) : ORIGIN = 0x20008000, LENGTH = 0K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.ARM.attributes : { *(.ARM.attributes) } > FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array*))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = .;
/* Initialized data sections goes into RAM, load LMA copy after code */
.data : AT ( _sidata )
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
PROVIDE ( end = _ebss );
PROVIDE ( _end = _ebss );
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
/* MEMORY_bank1 section, code must be located here explicitly */
/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
.memory_b1_text :
{
*(.mb1text) /* .mb1text sections (code) */
*(.mb1text*) /* .mb1text* sections (code) */
*(.mb1rodata) /* read-only data (constants) */
*(.mb1rodata*)
} >MEMORY_B1
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
}

0
bsp/essemi/es32f0654/drivers/linker_scripts/link.sct → bsp/essemi/es32f0654/board/linker_scripts/link.sct
View File

6
bsp/essemi/es32f0654/rtconfig.py
View File

@ -46,7 +46,7 @@ if PLATFORM == 'gcc':
DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
@ -69,7 +69,7 @@ elif PLATFORM == 'armcc':
DEVICE = ' --device DARMSTM'
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
LFLAGS = DEVICE + ' --scatter "board/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib'
@ -121,7 +121,7 @@ elif PLATFORM == 'iccarm':
AFLAGS += ' --fpu None'
AFLAGS += ' -S'
LFLAGS = ' --config "drivers\linker_scripts\link.icf"'
LFLAGS = ' --config "board\linker_scripts\link.icf"'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
if BUILD == 'debug':

0
bsp/essemi/es32f365x/drivers/linker_scripts/link.icf → bsp/essemi/es32f365x/board/linker_scripts/link.icf
View File

155
bsp/essemi/es32f365x/board/linker_scripts/link.lds Normal file
View File

@ -0,0 +1,155 @@
/*
*****************************************************************************
**
** File : es32f3696.ld
**
** Abstract : Linker script for ES32F3696 Device with
** 512K-Byte FLASH, 96K-Byte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20018000; /* end of 32K RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00008000, LENGTH = 480K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
MEMORY_B1 (rx) : ORIGIN = 0x20018000, LENGTH = 0K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.ARM.attributes : { *(.ARM.attributes) } > FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array*))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = .;
/* Initialized data sections goes into RAM, load LMA copy after code */
.data : AT ( _sidata )
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
PROVIDE ( end = _ebss );
PROVIDE ( _end = _ebss );
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
/* MEMORY_bank1 section, code must be located here explicitly */
/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
.memory_b1_text :
{
*(.mb1text) /* .mb1text sections (code) */
*(.mb1text*) /* .mb1text* sections (code) */
*(.mb1rodata) /* read-only data (constants) */
*(.mb1rodata*)
} >MEMORY_B1
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
}

0
bsp/essemi/es32f365x/drivers/linker_scripts/link.sct → bsp/essemi/es32f365x/board/linker_scripts/link.sct
View File

6
bsp/essemi/es32f365x/rtconfig.py
View File

@ -46,7 +46,7 @@ if PLATFORM == 'gcc':
DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
@ -69,7 +69,7 @@ elif PLATFORM == 'armcc':
DEVICE = ' --device DARMSTM'
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
LFLAGS = DEVICE + ' --scatter "board/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib'
@ -121,7 +121,7 @@ elif PLATFORM == 'iccarm':
AFLAGS += ' --fpu None'
AFLAGS += ' -S'
LFLAGS = ' --config "drivers\linker_scripts\link.icf"'
LFLAGS = ' --config "board\linker_scripts\link.icf"'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
if BUILD == 'debug':

28
bsp/fm33lc026/board/linker_scripts/link.icf Normal file
View File

@ -0,0 +1,28 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20005FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0400;
define symbol __ICFEDIT_size_heap__ = 0x000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK};

157
bsp/fm33lc026/board/linker_scripts/link.lds Normal file
View File

@ -0,0 +1,157 @@
/*
* linker script for STM32F10x with GNU ld
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */
RAM (rw) : ORIGIN = 0x20000000, LENGTH = 24K /* 16K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x400;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
_etext = .;
} > ROM = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > ROM
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
.stack :
{
. = ALIGN(4);
_sstack = .;
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >RAM
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > RAM
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

16
bsp/fm33lc026/board/linker_scripts/link.sct Normal file
View File

@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00006000 { ; RW data
.ANY (+RW +ZI)
}
}

4
bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/core_cm0plus.h
View File

@ -195,8 +195,8 @@
#endif
#include "core_cminstr.h" /* Core Instruction Access */
#include "core_cmfunc.h" /* Core Function Access */
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}

2
bsp/gd32/README.md
View File

@ -23,6 +23,8 @@ GD32 系列 BSP 目前支持情况如下表所示：
| [gd32407v-lckfb](arm/gd32407v-lckfb) | 立创天空星 GD32F407VET6 开发板 |
| [gd32450z-eval](arm/gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 |
| [gd32470z-lckfb](arm/gd32470z-lckfb) | 立创梁山派 GD32F470ZGT6 开发板 |
| **E5 系列** | |
| [gd32e503v-eval](arm/gd32e503v-eval) | 兆易创新 官方 GD32E503V-EVAL 开发板 |
| **RISC-V 系列** | |
| **VF1 系列** | |
| [gd32vf103v-eval](risc-v/gd32vf103v-eval) | 兆易创新 官方 GGD32VF103V-EVAL 开发板 |

2
bsp/gd32/arm/README.md
View File

@ -22,6 +22,8 @@ GD32 ARM 系列 BSP 目前支持情况如下表所示：
| [gd32407v-lckfb](gd32407v-lckfb) | 立创天空星 GD32F407VET6 开发板 |
| [gd32450z-eval](gd32450z-eval) | 兆易创新 官方 GD32450Z-EVAL 开发板 |
| [gd32470z-lckfb](gd32470z-lckfb) | 立创梁山派 GD32F470ZGT6 开发板 |
| **E5 系列** | |
| [gd32e503v-eval](gd32e503v-eval) | 兆易创新 官方 GD32E503V-EVAL 开发板 |
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：

300
bsp/gd32/arm/gd32e503v-eval/.config Normal file
View File

@ -0,0 +1,300 @@
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_AMP is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_CPUS_NR=1
CONFIG_RT_ALIGN_SIZE=8
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
# CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
#
# kservice optimization
#
# CONFIG_RT_USING_TINY_FFS is not set
# end of kservice optimization
#
# klibc optimization
#
# CONFIG_RT_KLIBC_USING_STDLIB is not set
# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set
# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set
# end of klibc optimization
CONFIG_RT_USING_DEBUG=y
CONFIG_RT_DEBUGING_ASSERT=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
# CONFIG_RT_DEBUGING_AUTO_INIT is not set
CONFIG_RT_USING_OVERFLOW_CHECK=y
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
# CONFIG_RT_USING_SIGNALS is not set
# end of Inter-Thread communication
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
# end of Memory Management
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x50200
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
CONFIG_FINSH_USING_OPTION_COMPLETION=y
#
# DFS: device virtual file system
#
# CONFIG_RT_USING_DFS is not set
# end of DFS: device virtual file system
# CONFIG_RT_USING_FAL is not set
#
# Device Drivers
#
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_DEV_BUS is not set
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_KTIME is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
# end of Device Drivers
#
# C/C++ and POSIX layer
#
#
# ISO-ANSI C layer
#
#
# Timezone and Daylight Saving Time
#
# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# end of Timezone and Daylight Saving Time
# end of ISO-ANSI C layer
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
# end of Interprocess Communication (IPC)
# end of POSIX (Portable Operating System Interface) layer
# CONFIG_RT_USING_CPLUSPLUS is not set
# end of C/C++ and POSIX layer
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
# end of Network
#
# Memory protection
#
# CONFIG_RT_USING_MEM_PROTECTION is not set
# CONFIG_RT_USING_HW_STACK_GUARD is not set
# end of Memory protection
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RESOURCE_ID is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set
# end of Utilities
# CONFIG_RT_USING_VBUS is not set
#
# Using USB legacy version
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
# end of Using USB legacy version
# CONFIG_RT_USING_FDT is not set
# end of RT-Thread Components
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
# end of RT-Thread Utestcases
#
# Hardware Drivers Config
#
#
# SOC Series
#
CONFIG_SOC_SERIES_GD32E50x=y
CONFIG_SOC_GD32503V=y
# end of SOC Series
#
# Onboard Peripheral Drivers
#
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_UART0_RX_USING_DMA is not set
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_TIM is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_USBD is not set
# CONFIG_BSP_USING_USBH is not set
# end of On-chip Peripheral Drivers
#
# Board extended module Drivers
#
# end of Hardware Drivers Config

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mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../../..
PKGS_DIR := packages
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
rsource "board/Kconfig"

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# GD32E503V-EVAL 开发板 BSP 说明
## 简介
GD32E503V-EVAL 评估板使用 GD32E503VET6 作为主控制器。评估板使用 GD-Link Mini
USB 接口提供 5V 电源。提供包括扩展引脚在内的及 Reset， Boot， K2， LED， I2S， I2CEEPROM， LCD， NAND Flash， SPI-Flash， SDIO， USB， USART 转 USB 接口等外设资源。
该开发板常用 ** 板载资源 ** 如下：
- GD32E503VET6，主频 180MHz，512KB FLASH ，128KB RAM
- 常用外设
- LED ：5 个，LEDPWR (电源指示灯），LED1（PC0），LED2（PC2），LED3（PE0），LED4（PE1）
- 按键：5 个，KEY_A（用户按键，PA0），KEY_B（用户按键，PC13），KEY_C（用户按键，PB14），KEY_D（用户按键，PC5），KEY_Cet（用户按键，PC4）
- General TM * 10、Advanced TM * 2、Basic TM * 2
- 系统时钟 * 1
- 看门狗 * 2
- RTC * 1
- USART * 4、UART * 2
- I2C * 2、I2S * 2
- SPI * 3
- CAN2.0B * 1
- USB2.0 OTG FS * 1
- TFT-LCD
- EXMC/SDRAM * 1
- ADC * 3
- DAC * 2
- 最多支持 100GPIOs
- 常用接口：USB 接口
- 调试接口：GD-LINK
## 外设支持
本 BSP 目前对外设的支持情况如下：
| ** 片上外设 ** | ** 支持情况 ** | ** 备注 ** |
| :----------- | :----------: | :------------------------------- |
| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...111 |
| UART | 支持 | UART0 - UART5 |
| ** 扩展模块 ** | ** 支持情况 ** | ** 备注 ** |
| 暂无 | 暂不支持 | 暂不支持 |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境，也可使用 RT-Thread Studio 开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，使用 USB 转 232 连接 USART1，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 GD-Link 仿真器下载程序，在通过 GD-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后，系统会自动运行，LED 闪烁。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.4 build Jan 9 2021
2006 - 2021 Copyright by rt-thread team
msh >
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口 1 的功能，如果需使用高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。
3. 输入 `pkgs --update` 命令更新软件包。
4. 输入 `scons --target=mdk4/mdk5/iar` 命令重新生成工程。
## 注意事项
暂无
## 联系人信息
维护人:
- [drifting1024](https://github.com/drifting1024), 邮箱：<drifting1024@163.com>

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
gd32_library = 'GD32E50x_Firmware_Library'
rtconfig.BSP_LIBRARY_TYPE = gd32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, gd32_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'gd32_drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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from building import *
import os
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 BruceOu first implementation
*/
#include <stdio.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
/* defined the LED1 pin: PC0 */
#define LED1_PIN GET_PIN(C, 0)
int main(void)
{
int count = 1;
/* set LED1 pin mode to output */
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
while (count++)
{
rt_pin_write(LED1_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED1_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
return RT_EOK;
}

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menu "Hardware Drivers Config"
menu "SOC Series"
menuconfig SOC_SERIES_GD32E50x
bool "Enable GD32E50x"
default y
select SERIES_GD32E50x
if SOC_SERIES_GD32E50x
config SOC_GD32503V
bool "Enable GD32503V"
select GD32503V
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
endif
endmenu
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0"
default n
config BSP_UART0_RX_USING_DMA
bool "Enable UART0 RX DMA"
depends on BSP_USING_UART0
select RT_SERIAL_USING_DMA
default n
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1
select RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2
select RT_SERIAL_USING_DMA
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3
select RT_SERIAL_USING_DMA
default n
config BSP_USING_UART4
bool "Enable UART4"
default n
config BSP_UART4_RX_USING_DMA
bool "Enable UART4 RX DMA"
depends on BSP_USING_UART4
select RT_SERIAL_USING_DMA
default n
config BSP_USING_UART5
bool "Enable UART5"
default n
config BSP_UART5_RX_USING_DMA
bool "Enable UART5 RX DMA"
depends on BSP_USING_UART5
select RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 1 216
default 24
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 1 216
default 25
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "Enable ADC0"
default n
config BSP_USING_ADC1
bool "Enable ADC1"
default n
config BSP_USING_ADC2
bool "Enable ADC2"
default n
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM10
bool "Enable TIM10"
default n
config BSP_USING_TIM11
bool "Enable TIM11"
default n
config BSP_USING_TIM12
bool "Enable TIM13"
default n
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_ONCHIP_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
config BSP_USING_USBD
bool "Enable USB Device"
select RT_USING_USB_DEVICE
default n
menuconfig BSP_USING_USBH
bool "Enable USB Host"
select RT_USING_USB_HOST
default n
if BSP_USING_USBH
menuconfig RT_USBH_MSTORAGE
bool "Enable Udisk Drivers"
default n
if RT_USBH_MSTORAGE
config UDISK_MOUNTPOINT
string "Udisk mount dir"
default "/"
endif
endif
rsource "../../libraries/gd32_drivers/Kconfig"
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
''')
path = [cwd]
startup_path_prefix = SDK_LIB
if rtconfig.PLATFORM in ['armcc', 'armclang']:
src += [startup_path_prefix + '/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/ARM/startup_gd32e50x_hd.s']
elif rtconfig.PLATFORM in ['iccarm']:
src += [startup_path_prefix + '/GD32E50x_Firmware_Library/CMSIS/GD/GD32E50x/Source/IAR/startup_gd32e50x_hd.s']
CPPDEFINES = ['GD32E50X', 'GD32E50X_HD']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-10-23 drifting1024 first implementation
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#ifdef RT_USING_SERIAL_V2
#include "drv_usart_v2.h"
#else
#include "drv_usart.h"
#endif
/**
* @brief This function is executed in case of error occurrence.
* @param None
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while (1)
{
}
/* USER CODE END Error_Handler */
}
/** System Clock Configuration
*/
void SystemClock_Config(void)
{
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
NVIC_SetPriority(SysTick_IRQn, 0);
}
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial GD32 board.
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x08000000 */
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
#endif
SystemClock_Config();
#ifdef RT_USING_SERIAL
rt_hw_usart_init();
#endif
#ifdef BSP_USING_SDRAM
rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
#else
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}
/*@}*/

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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-10-23 drifting1024 first implementation
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "gd32e50x.h"
#include "drv_gpio.h"
#include "gd32e50x_exti.h"
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
/* <o> Internal SRAM memory size[Kbytes] <96-128>*/
/* <i>Default: 128*/
#ifdef __ICCARM__
/* Use *.icf ram symbal, to avoid hardcode.*/
extern char __ICFEDIT_region_RAM_end__;
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
#else
#define GD32_SRAM_SIZE 128
#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
#endif
#ifdef __ARMCC_VERSION
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END GD32_SRAM_END
#endif

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/*!
\file gd32e50x_libopt.h
\brief library optional for gd32e50x
\version 2023-12-31, V1.4.0, firmware for GD32E50x
*/
/*
Copyright (c) 2023, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E50X_LIBOPT_H
#define GD32E50X_LIBOPT_H
#ifndef GD32EPRT
#include "gd32e50x_adc.h"
#include "gd32e50x_bkp.h"
#include "gd32e50x_can.h"
#include "gd32e50x_crc.h"
#include "gd32e50x_ctc.h"
#include "gd32e50x_dac.h"
#include "gd32e50x_dbg.h"
#include "gd32e50x_dma.h"
#include "gd32e50x_exmc.h"
#include "gd32e50x_exti.h"
#include "gd32e50x_fmc.h"
#include "gd32e50x_fwdgt.h"
#include "gd32e50x_gpio.h"
#include "gd32e50x_shrtimer.h"
#include "gd32e50x_i2c.h"
#include "gd32e50x_misc.h"
#include "gd32e50x_pmu.h"
#include "gd32e50x_rcu.h"
#include "gd32e50x_rtc.h"
#include "gd32e50x_spi.h"
#include "gd32e50x_timer.h"
#include "gd32e50x_usart.h"
#include "gd32e50x_wwdgt.h"
#include "gd32e50x_sqpi.h"
#if defined (GD32E50X_CL) || defined (GD32E508)
#include "gd32e50x_enet.h"
#include "gd32e50x_tmu.h"
#include "gd32e50x_cmp.h"
#else /* GD32E50X_CL or GD32E508 */
#include "gd32e50x_sdio.h"
#endif /* GD32E50X_CL or GD32E508 */
#else /* GD32EPRT */
#include "gd32e50x_adc.h"
#include "gd32e50x_bkp.h"
#include "gd32e50x_crc.h"
#include "gd32e50x_ctc.h"
#include "gd32e50x_dac.h"
#include "gd32e50x_dbg.h"
#include "gd32e50x_dma.h"
#include "gd32e50x_enet.h"
#include "gd32e50x_exmc.h"
#include "gd32e50x_exti.h"
#include "gd32e50x_fmc.h"
#include "gd32e50x_fwdgt.h"
#include "gd32e50x_gpio.h"
#include "gd32e50x_i2c.h"
#include "gd32e50x_misc.h"
#include "gd32e50x_pmu.h"
#include "gd32e50x_rcu.h"
#include "gd32e50x_rtc.h"
#include "gd32e50x_spi.h"
#include "gd32e50x_timer.h"
#include "gd32e50x_usart.h"
#include "gd32e50x_wwdgt.h"
#include "gd32e50x_sqpi.h"
#endif /* GD32EPRT */
#endif /* GD32E50X_LIBOPT_H */

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x201FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x200;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
export symbol __ICFEDIT_region_RAM_end__;
define symbol __region_RAM1_start__ = 0x10000000;
define symbol __region_RAM1_end__ = 0x1000FFFF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in RAM1_region { section .sram };

142
bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.ld Normal file
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/*
* linker script for GD32E50x with GNU ld
* BruceOu 2021-12-14
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
} > CODE = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
.stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >DATA
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

15
bsp/gd32/arm/gd32e503v-eval/board/linker_scripts/link.sct Normal file
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@ -0,0 +1,15 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00020000 { ; RW data
.ANY (+RW +ZI)
}
}

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0
bsp/nxp/imx/imxrt/imxrt1170-nxp-evk/m7/project.eww → bsp/gd32/arm/gd32e503v-eval/project.eww
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933
bsp/gd32/arm/gd32e503v-eval/project.uvoptx Normal file
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@ -0,0 +1,933 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59503607 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BE12477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32E50x_512 -FS08000000 -FL080000 -FP0($$Device:GD32E503VE$Flash\GD32E50x_512.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2V8M</Key>
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E50x_512 -FS08000000 -FL080000 -FP0($$Device:GD32E503VE$Flash\GD32E50x_512.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
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</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Applications</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
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<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
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<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>applications\main.c</PathWithFileName>
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</File>
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* kservice optimization */
/* end of kservice optimization */
/* klibc optimization */
/* end of klibc optimization */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_USING_OVERFLOW_CHECK
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* Hardware Drivers Config */
/* SOC Series */
#define SOC_SERIES_GD32E50x
#define SOC_GD32503V
/* end of SOC Series */
/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers Config */
#endif

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import os
# toolchains options
ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='keil'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M4.fp '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iccarm':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' -e'
CFLAGS += ' --fpu=VFPv4_sp'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu VFPv4_sp'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59503607 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BE12477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32E50x_512 -FS08000000 -FL080000 -FP0($$Device:GD32E503VE$Flash\GD32E50x_512.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2V8M</Key>
<Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E50x_512 -FS08000000 -FL080000 -FP0($$Device:GD32E503VE$Flash\GD32E50x_512.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

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