update LPC176X CMSIS
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1760 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong
parent
eb0af4e41e
commit
eb3ae3e3ca
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;/*****************************************************************************
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; * @file: startup_LPC17xx.s
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; * @purpose: CMSIS Cortex-M3 Core Device Startup File
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; * for the NXP LPC17xx Device Series
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; * @version: V1.02
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; * @date: 27. July 2009
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; * Copyright (C) 2009 ARM Limited. All rights reserved.
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; *****************************************************************************/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000200
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WDT_IRQHandler ; 16: Watchdog Timer
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DCD TIMER0_IRQHandler ; 17: Timer0
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DCD TIMER1_IRQHandler ; 18: Timer1
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DCD TIMER2_IRQHandler ; 19: Timer2
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DCD TIMER3_IRQHandler ; 20: Timer3
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DCD UART0_IRQHandler ; 21: UART0
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DCD UART1_IRQHandler ; 22: UART1
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DCD UART2_IRQHandler ; 23: UART2
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DCD UART3_IRQHandler ; 24: UART3
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DCD PWM1_IRQHandler ; 25: PWM1
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DCD I2C0_IRQHandler ; 26: I2C0
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DCD I2C1_IRQHandler ; 27: I2C1
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DCD I2C2_IRQHandler ; 28: I2C2
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DCD SPI_IRQHandler ; 29: SPI
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DCD SSP0_IRQHandler ; 30: SSP0
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DCD SSP1_IRQHandler ; 31: SSP1
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DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
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DCD RTC_IRQHandler ; 33: Real Time Clock
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DCD EINT0_IRQHandler ; 34: External Interrupt 0
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DCD EINT1_IRQHandler ; 35: External Interrupt 1
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DCD EINT2_IRQHandler ; 36: External Interrupt 2
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DCD EINT3_IRQHandler ; 37: External Interrupt 3
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DCD ADC_IRQHandler ; 38: A/D Converter
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DCD BOD_IRQHandler ; 39: Brown-Out Detect
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DCD USB_IRQHandler ; 40: USB
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DCD CAN_IRQHandler ; 41: CAN
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DCD DMA_IRQHandler ; 42: General Purpose DMA
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DCD I2S_IRQHandler ; 43: I2S
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DCD ENET_IRQHandler ; 44: Ethernet
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DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
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DCD MCPWM_IRQHandler ; 46: Motor Control PWM
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DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
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DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
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IF :LNOT::DEF:NO_CRP
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AREA |.ARM.__at_0x02FC|, CODE, READONLY
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CRP_Key DCD 0xFFFFFFFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT TIMER3_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT UART3_IRQHandler [WEAK]
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EXPORT PWM1_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT I2C2_IRQHandler [WEAK]
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EXPORT SPI_IRQHandler [WEAK]
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EXPORT SSP0_IRQHandler [WEAK]
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EXPORT SSP1_IRQHandler [WEAK]
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EXPORT PLL0_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT EINT0_IRQHandler [WEAK]
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EXPORT EINT1_IRQHandler [WEAK]
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EXPORT EINT2_IRQHandler [WEAK]
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EXPORT EINT3_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT BOD_IRQHandler [WEAK]
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EXPORT USB_IRQHandler [WEAK]
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EXPORT CAN_IRQHandler [WEAK]
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EXPORT DMA_IRQHandler [WEAK]
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EXPORT I2S_IRQHandler [WEAK]
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EXPORT ENET_IRQHandler [WEAK]
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EXPORT RIT_IRQHandler [WEAK]
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EXPORT MCPWM_IRQHandler [WEAK]
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EXPORT QEI_IRQHandler [WEAK]
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EXPORT PLL1_IRQHandler [WEAK]
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WDT_IRQHandler
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TIMER0_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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TIMER3_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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UART3_IRQHandler
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PWM1_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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I2C2_IRQHandler
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SPI_IRQHandler
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SSP0_IRQHandler
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SSP1_IRQHandler
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PLL0_IRQHandler
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RTC_IRQHandler
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EINT0_IRQHandler
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EINT1_IRQHandler
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EINT2_IRQHandler
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EINT3_IRQHandler
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ADC_IRQHandler
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BOD_IRQHandler
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USB_IRQHandler
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CAN_IRQHandler
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DMA_IRQHandler
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I2S_IRQHandler
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ENET_IRQHandler
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RIT_IRQHandler
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MCPWM_IRQHandler
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QEI_IRQHandler
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PLL1_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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@ -0,0 +1,239 @@
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/*****************************************************************************/
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/* startup_LPC17xx.s: Startup file for LPC17xx device series */
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/*****************************************************************************/
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/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */
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/*****************************************************************************/
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/*
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//*** <<< Use Configuration Wizard in Context Menu >>> ***
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*/
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/*
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// <h> Stack Configuration
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// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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*/
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.equ Stack_Size, 0x00000100
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.section ".stack", "w"
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.align 3
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.globl __cs3_stack_mem
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.globl __cs3_stack_size
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__cs3_stack_mem:
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.if Stack_Size
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.space Stack_Size
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.endif
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.size __cs3_stack_mem, . - __cs3_stack_mem
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.set __cs3_stack_size, . - __cs3_stack_mem
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/*
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// <h> Heap Configuration
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// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// </h>
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*/
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.equ Heap_Size, 0x00001000
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.section ".heap", "w"
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.align 3
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.globl __cs3_heap_start
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.globl __cs3_heap_end
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__cs3_heap_start:
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.if Heap_Size
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.space Heap_Size
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.endif
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__cs3_heap_end:
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/* Vector Table */
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.section ".cs3.interrupt_vector"
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.globl __cs3_interrupt_vector_cortex_m
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.type __cs3_interrupt_vector_cortex_m, %object
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__cs3_interrupt_vector_cortex_m:
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.long __cs3_stack /* Top of Stack */
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.long __cs3_reset /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External Interrupts */
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.long WDT_IRQHandler /* 16: Watchdog Timer */
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.long TIMER0_IRQHandler /* 17: Timer0 */
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.long TIMER1_IRQHandler /* 18: Timer1 */
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.long TIMER2_IRQHandler /* 19: Timer2 */
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.long TIMER3_IRQHandler /* 20: Timer3 */
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.long UART0_IRQHandler /* 21: UART0 */
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.long UART1_IRQHandler /* 22: UART1 */
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.long UART2_IRQHandler /* 23: UART2 */
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.long UART3_IRQHandler /* 24: UART3 */
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.long PWM1_IRQHandler /* 25: PWM1 */
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.long I2C0_IRQHandler /* 26: I2C0 */
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.long I2C1_IRQHandler /* 27: I2C1 */
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.long I2C2_IRQHandler /* 28: I2C2 */
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.long SPI_IRQHandler /* 29: SPI */
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.long SSP0_IRQHandler /* 30: SSP0 */
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.long SSP1_IRQHandler /* 31: SSP1 */
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.long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
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.long RTC_IRQHandler /* 33: Real Time Clock */
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.long EINT0_IRQHandler /* 34: External Interrupt 0 */
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.long EINT1_IRQHandler /* 35: External Interrupt 1 */
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.long EINT2_IRQHandler /* 36: External Interrupt 2 */
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.long EINT3_IRQHandler /* 37: External Interrupt 3 */
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.long ADC_IRQHandler /* 38: A/D Converter */
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.long BOD_IRQHandler /* 39: Brown-Out Detect */
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.long USB_IRQHandler /* 40: USB */
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.long CAN_IRQHandler /* 41: CAN */
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.long DMA_IRQHandler /* 42: General Purpose DMA */
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.long I2S_IRQHandler /* 43: I2S */
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.long ENET_IRQHandler /* 44: Ethernet */
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.long RIT_IRQHandler /* 45: Repetitive Interrupt Timer */
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.long MCPWM_IRQHandler /* 46: Motor Control PWM */
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.long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
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.long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
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.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
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.thumb
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/* Reset Handler */
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.section .cs3.reset,"x",%progbits
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.thumb_func
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.globl __cs3_reset_cortex_m
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.type __cs3_reset_cortex_m, %function
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__cs3_reset_cortex_m:
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.fnstart
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LDR R0, =SystemInit
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||||||
|
BLX R0
|
||||||
|
LDR R0,=_start
|
||||||
|
BX R0
|
||||||
|
.pool
|
||||||
|
.cantunwind
|
||||||
|
.fnend
|
||||||
|
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
|
||||||
|
|
||||||
|
.section ".text"
|
||||||
|
|
||||||
|
/* Exception Handlers */
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.type NMI_Handler, %function
|
||||||
|
NMI_Handler:
|
||||||
|
B .
|
||||||
|
.size NMI_Handler, . - NMI_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.type HardFault_Handler, %function
|
||||||
|
HardFault_Handler:
|
||||||
|
B .
|
||||||
|
.size HardFault_Handler, . - HardFault_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.type MemManage_Handler, %function
|
||||||
|
MemManage_Handler:
|
||||||
|
B .
|
||||||
|
.size MemManage_Handler, . - MemManage_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.type BusFault_Handler, %function
|
||||||
|
BusFault_Handler:
|
||||||
|
B .
|
||||||
|
.size BusFault_Handler, . - BusFault_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.type UsageFault_Handler, %function
|
||||||
|
UsageFault_Handler:
|
||||||
|
B .
|
||||||
|
.size UsageFault_Handler, . - UsageFault_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.type SVC_Handler, %function
|
||||||
|
SVC_Handler:
|
||||||
|
B .
|
||||||
|
.size SVC_Handler, . - SVC_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.type DebugMon_Handler, %function
|
||||||
|
DebugMon_Handler:
|
||||||
|
B .
|
||||||
|
.size DebugMon_Handler, . - DebugMon_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.type PendSV_Handler, %function
|
||||||
|
PendSV_Handler:
|
||||||
|
B .
|
||||||
|
.size PendSV_Handler, . - PendSV_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.type SysTick_Handler, %function
|
||||||
|
SysTick_Handler:
|
||||||
|
B .
|
||||||
|
.size SysTick_Handler, . - SysTick_Handler
|
||||||
|
|
||||||
|
|
||||||
|
/* IRQ Handlers */
|
||||||
|
|
||||||
|
.globl Default_Handler
|
||||||
|
.type Default_Handler, %function
|
||||||
|
Default_Handler:
|
||||||
|
B .
|
||||||
|
.size Default_Handler, . - Default_Handler
|
||||||
|
|
||||||
|
.macro IRQ handler
|
||||||
|
.weak \handler
|
||||||
|
.set \handler, Default_Handler
|
||||||
|
.endm
|
||||||
|
|
||||||
|
IRQ WDT_IRQHandler
|
||||||
|
IRQ TIMER0_IRQHandler
|
||||||
|
IRQ TIMER1_IRQHandler
|
||||||
|
IRQ TIMER2_IRQHandler
|
||||||
|
IRQ TIMER3_IRQHandler
|
||||||
|
IRQ UART0_IRQHandler
|
||||||
|
IRQ UART1_IRQHandler
|
||||||
|
IRQ UART2_IRQHandler
|
||||||
|
IRQ UART3_IRQHandler
|
||||||
|
IRQ PWM1_IRQHandler
|
||||||
|
IRQ I2C0_IRQHandler
|
||||||
|
IRQ I2C1_IRQHandler
|
||||||
|
IRQ I2C2_IRQHandler
|
||||||
|
IRQ SPI_IRQHandler
|
||||||
|
IRQ SSP0_IRQHandler
|
||||||
|
IRQ SSP1_IRQHandler
|
||||||
|
IRQ PLL0_IRQHandler
|
||||||
|
IRQ RTC_IRQHandler
|
||||||
|
IRQ EINT0_IRQHandler
|
||||||
|
IRQ EINT1_IRQHandler
|
||||||
|
IRQ EINT2_IRQHandler
|
||||||
|
IRQ EINT3_IRQHandler
|
||||||
|
IRQ ADC_IRQHandler
|
||||||
|
IRQ BOD_IRQHandler
|
||||||
|
IRQ USB_IRQHandler
|
||||||
|
IRQ CAN_IRQHandler
|
||||||
|
IRQ DMA_IRQHandler
|
||||||
|
IRQ I2S_IRQHandler
|
||||||
|
IRQ ENET_IRQHandler
|
||||||
|
IRQ RIT_IRQHandler
|
||||||
|
IRQ MCPWM_IRQHandler
|
||||||
|
IRQ QEI_IRQHandler
|
||||||
|
IRQ PLL1_IRQHandler
|
||||||
|
|
||||||
|
.end
|
||||||
|
|
@ -0,0 +1,341 @@
|
||||||
|
;/*****************************************************************************
|
||||||
|
; * @file: startup_LPC17xx.s
|
||||||
|
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
|
||||||
|
; * for the NXP LPC17xx Device Series
|
||||||
|
; * @version: V1.02
|
||||||
|
; * @date: 31. July 2009
|
||||||
|
; *----------------------------------------------------------------------------
|
||||||
|
; *
|
||||||
|
; * Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||||
|
; *
|
||||||
|
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
|
||||||
|
; * processor based microcontrollers. This file can be freely distributed
|
||||||
|
; * within development tools that are supporting such ARM based processors.
|
||||||
|
; *
|
||||||
|
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
; *
|
||||||
|
; ******************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
;
|
||||||
|
; The modules in this file are included in the libraries, and may be replaced
|
||||||
|
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||||
|
; a user defined start symbol.
|
||||||
|
; To override the cstartup defined in the library, simply add your modified
|
||||||
|
; version to the workbench project.
|
||||||
|
;
|
||||||
|
; The vector table is normally located at address 0.
|
||||||
|
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||||
|
; The name "__vector_table" has special meaning for C-SPY:
|
||||||
|
; it is where the SP start value is found, and the NVIC vector
|
||||||
|
; table register (VTOR) is initialized to this address if != 0.
|
||||||
|
;
|
||||||
|
; Cortex-M version
|
||||||
|
;
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
PUBLIC __vector_table_0x1c
|
||||||
|
PUBLIC __Vectors
|
||||||
|
PUBLIC __Vectors_End
|
||||||
|
PUBLIC __Vectors_Size
|
||||||
|
|
||||||
|
DATA
|
||||||
|
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK)
|
||||||
|
DCD Reset_Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler
|
||||||
|
DCD HardFault_Handler
|
||||||
|
DCD MemManage_Handler
|
||||||
|
DCD BusFault_Handler
|
||||||
|
DCD UsageFault_Handler
|
||||||
|
__vector_table_0x1c
|
||||||
|
DCD 0
|
||||||
|
DCD 0
|
||||||
|
DCD 0
|
||||||
|
DCD 0
|
||||||
|
DCD SVC_Handler
|
||||||
|
DCD DebugMon_Handler
|
||||||
|
DCD 0
|
||||||
|
DCD PendSV_Handler
|
||||||
|
DCD SysTick_Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WDT_IRQHandler ; 16: Watchdog Timer
|
||||||
|
DCD TIMER0_IRQHandler ; 17: Timer0
|
||||||
|
DCD TIMER1_IRQHandler ; 18: Timer1
|
||||||
|
DCD TIMER2_IRQHandler ; 19: Timer2
|
||||||
|
DCD TIMER3_IRQHandler ; 20: Timer3
|
||||||
|
DCD UART0_IRQHandler ; 21: UART0
|
||||||
|
DCD UART1_IRQHandler ; 22: UART1
|
||||||
|
DCD UART2_IRQHandler ; 23: UART2
|
||||||
|
DCD UART3_IRQHandler ; 24: UART3
|
||||||
|
DCD PWM1_IRQHandler ; 25: PWM1
|
||||||
|
DCD I2C0_IRQHandler ; 26: I2C0
|
||||||
|
DCD I2C1_IRQHandler ; 27: I2C1
|
||||||
|
DCD I2C2_IRQHandler ; 28: I2C2
|
||||||
|
DCD SPI_IRQHandler ; 29: SPI
|
||||||
|
DCD SSP0_IRQHandler ; 30: SSP0
|
||||||
|
DCD SSP1_IRQHandler ; 31: SSP1
|
||||||
|
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
|
||||||
|
DCD RTC_IRQHandler ; 33: Real Time Clock
|
||||||
|
DCD EINT0_IRQHandler ; 34: External Interrupt 0
|
||||||
|
DCD EINT1_IRQHandler ; 35: External Interrupt 1
|
||||||
|
DCD EINT2_IRQHandler ; 36: External Interrupt 2
|
||||||
|
DCD EINT3_IRQHandler ; 37: External Interrupt 3
|
||||||
|
DCD ADC_IRQHandler ; 38: A/D Converter
|
||||||
|
DCD BOD_IRQHandler ; 39: Brown-Out Detect
|
||||||
|
DCD USB_IRQHandler ; 40: USB
|
||||||
|
DCD CAN_IRQHandler ; 41: CAN
|
||||||
|
DCD DMA_IRQHandler ; 42: General Purpose DMA
|
||||||
|
DCD I2S_IRQHandler ; 43: I2S
|
||||||
|
DCD ENET_IRQHandler ; 44: Ethernet
|
||||||
|
DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
|
||||||
|
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
|
||||||
|
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
|
||||||
|
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors EQU __vector_table
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:REORDER(2)
|
||||||
|
Reset_Handler
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WDT_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
WDT_IRQHandler
|
||||||
|
B WDT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIMER0_IRQHandler
|
||||||
|
B TIMER0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
B TIMER1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
B TIMER2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
B TIMER3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
UART0_IRQHandler
|
||||||
|
B UART0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
UART1_IRQHandler
|
||||||
|
B UART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
UART2_IRQHandler
|
||||||
|
B UART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
UART3_IRQHandler
|
||||||
|
B UART3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PWM1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
PWM1_IRQHandler
|
||||||
|
B PWM1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
I2C0_IRQHandler
|
||||||
|
B I2C0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
I2C1_IRQHandler
|
||||||
|
B I2C1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
I2C2_IRQHandler
|
||||||
|
B I2C2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SPI_IRQHandler
|
||||||
|
B SPI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SSP0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SSP0_IRQHandler
|
||||||
|
B SSP0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SSP1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
SSP1_IRQHandler
|
||||||
|
B SSP1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PLL0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
PLL0_IRQHandler
|
||||||
|
B PLL0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
RTC_IRQHandler
|
||||||
|
B RTC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EINT0_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EINT0_IRQHandler
|
||||||
|
B EINT0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EINT1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EINT1_IRQHandler
|
||||||
|
B EINT1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EINT2_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EINT2_IRQHandler
|
||||||
|
B EINT2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EINT3_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
EINT3_IRQHandler
|
||||||
|
B EINT3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK BOD_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
BOD_IRQHandler
|
||||||
|
B BOD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USB_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
USB_IRQHandler
|
||||||
|
B USB_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
CAN_IRQHandler
|
||||||
|
B CAN_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
DMA_IRQHandler
|
||||||
|
B DMA_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2S_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
I2S_IRQHandler
|
||||||
|
B I2S_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ENET_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
ENET_IRQHandler
|
||||||
|
B ENET_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RIT_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
RIT_IRQHandler
|
||||||
|
B RIT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK MCPWM_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
MCPWM_IRQHandler
|
||||||
|
B MCPWM_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK QEI_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
QEI_IRQHandler
|
||||||
|
B QEI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK PLL1_IRQHandler
|
||||||
|
SECTION .text:CODE:REORDER(1)
|
||||||
|
PLL1_IRQHandler
|
||||||
|
B PLL1_IRQHandler
|
||||||
|
|
||||||
|
END
|
||||||
Loading…
Reference in New Issue