[bsp][zynqmp] 为 DFZU2EG MPSoC 开发板支持标准版和Smart版内核 (#8773)
zynqmp support RT-Thread and RT-smart
This commit is contained in:
liYangYang
Meco Man
parent
fcad5e16d7
commit
ea1ab21051
File diff suppressed because it is too large
Load Diff
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mainmenu "RT-Thread Project Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../../"
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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config SOC_ZYNQMP_AARCH64
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bool
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select ARCH_ARMV8
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select ARCH_CPU_64BIT
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select ARCH_ARM_MMU
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select RT_USING_CACHE
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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select RT_USING_GIC
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select BSP_USING_GIC
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select ARCH_MM_MMU
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default y
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source "$BSP_DIR/drivers/Kconfig"
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# DFZU2EG MPSoC 板级支持包说明
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## 1. 简介
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正点原子 DFZU2EG MPSoC 开发板采用Xilinx的Zynq UltraScale+ MPSoC芯片作为主控芯片。它主要分为PS和PL两部分，在PS部分中主要由Arm Cortex A53（APU 共4个核）、Arm Cortex R5F（RPU 共两个核）以及Arm Mali 400 MP2（GPU）三种内核处理器构成，并且还包括DDR 控制单元、平台管理单元、高速外设控制器以及普通外设控制器等外设组成。
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该板级支持包主要是针对APU做的一份移植，支持RT-Thread标准版和Smart版内核。
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DFZU2EG MPSoC 开发板的详细资源信息可以查阅正点原子此开发板的相关手册，也可以参考下图：
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## 2. 编译说明
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推荐使用ubuntu20的[env环境](https://github.com/RT-Thread/env)，当然也可以使用windows上的[env工具](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)进行编译。下面介绍**标准版**和**Smart版本**的编译流程。
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### 2.1 RT-Thread编译
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**1.menuconfig配置工程：**
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该BSP默认menuconfig支持的就是RT-Thread标准版，无需配置工程。
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**2.配置工具链相关环境：**
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依次执行下面命令进行环境变量的相关配置：
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```shell
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export RTT_CC=gcc
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export RTT_EXEC_PATH="/opt/tools/gnu_gcc/arm-gnu-toolchain-13.2.Rel1-x86_64-aarch64-none-elf/bin"
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export RTT_CC_PREFIX=aarch64-none-elf-
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export PATH=$PATH:$RTT_EXEC_PATH
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```
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**3.编译：**
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```shell
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scons -j12
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```
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### 2.2 RT-Smart编译
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**1.menuconfig配置工程：**
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```shell
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RT-Thread Kernel --->
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[*] Enable RT-Thread Smart (microkernel on kernel/userland)
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```
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**2.配置工具链相关环境：**
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依次执行下面命令进行环境变量的相关配置：
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```shell
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export RTT_CC=gcc
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export RTT_EXEC_PATH="/opt/tools/gnu_gcc/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin"
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export RTT_CC_PREFIX=aarch64-linux-musleabi-
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export PATH=$PATH:$RTT_EXEC_PATH
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```
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**3.编译：**
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```shell
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scons -j12
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```
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如果编译正确无误，会产生 `rtthread.elf`, `rtthread.bin` 文件。
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## 3. 环境搭建
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### 3.1 准备好串口线
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连线情况如下图所示：
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串口参数： 115200 8N1 ，硬件和软件流控为关。
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### 3.2 RTT固件放在SD卡运行
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暂时不支持，需要使用 u-boot 加载。
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### 3.3 RTT程序用uboot加载
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需要注意的以下问题：
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- 保证开发板和保存固件的PC机处于同一网段，互相可以ping通。
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- 保证PC机已经成功配置TFTP的相关服务。
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可以使用开发板出厂自带的uboot(EMMC)来加载RTT程序，将网线连接到开发板的PS网口，然后在uboot控制台输入下列命令：
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```shell
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setenv ipaddr 192.168.1.50
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setenv ethaddr b8:ae:1d:01:00:00
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setenv gatewayip 192.168.1.1
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setenv netmask 255.255.255.0
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setenv serverip 192.168.1.3
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tftpboot 0x00200000 rtthread.bin
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go 0x00200000
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```
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其中`192.168.1.3`为TFTP服务器的PC机的IP地址，大家可以根据自己的实际情况进行修改。
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执行完上述命令后，uboot就可以自动从tftp服务器上获取固件，然后开始执行了。
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完成后可以看到串口的输出信息：
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**标准版log信息：**
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```shell
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heap: [0x00299540 - 0x04000000]
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\ | /
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- RT - Thread Operating System
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/ | \ 5.1.0 build Apr 11 2024 11:43:19
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2006 - 2024 Copyright by RT-Thread team
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hello rt-thread
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msh />
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```
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**Smart版log信息：**
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```shell
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heap: [0x002fd030 - 0x04000000]
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\ | /
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- RT - Thread Smart Operating System
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/ | \ 5.1.0 build Apr 11 2024 11:47:02
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2006 - 2024 Copyright by RT-Thread team
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Press any key to stop init process startup ... 3
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Press any key to stop init process startup ... 2
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Press any key to stop init process startup ... 1
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Starting init ...
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[E/lwp] lwp_startup: init program not found
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Switching to legacy mode...
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hello rt-thread
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msh />
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```
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## 4. 支持情况
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| 驱动 | 支持情况 | 备注 |
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| ------ | ---- | :------: |
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| UART | 支持 | UART0 |
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| GPIO | 暂不支持 | - |
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| SPI | 暂不支持 | - |
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| SDIO | 暂不支持 | - |
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| ETH | 暂不支持 | - |
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目前BSP仅保证成功运行，驱动后续会慢慢支持！
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## 5. 注意事项
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对于ZYNQ的开发，需要使用Vivado软件对开发板的硬件进行一些配置，来生产相应的fsbl.elf文件，比如串口引脚的初始化等等，所以如果大家需要修改串口的输出引脚信息，需要更新fsbl.elf，而这些知识是需要具备一定的ZYNQ开发基础的。
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## 6. 联系人信息
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维护人：[liYony](https://github.com/liYony)
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# for module compiling
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import os
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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import os
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import sys
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import rtconfig
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import re
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.join(os.getcwd(), '..', '..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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TRACE_CONFIG = ""
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content = ""
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with open("rtconfig.h") as f:
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for line in f.readlines():
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if line.find("RT_BACKTRACE_FUNCTION_NAME") != -1:
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for token in line.split(" "):
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if re.match(r'RT_BACKTRACE_FUNCTION_NAME$', token, flags=0):
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TRACE_CONFIG = " "
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS + TRACE_CONFIG,
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CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS + TRACE_CONFIG,
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS + TRACE_CONFIG,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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env['ASCOM'] = env['ASPPCOM']
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env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT)
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# make a building
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DoBuilding(TARGET, objs)
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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CPPPATH = [cwd]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/10/7 bernard the first version
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*/
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#include <rtthread.h>
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int main(void)
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{
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rt_kprintf("hello rt-thread\n");
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return 0;
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}
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menu "Hardware Drivers Config"
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config BSP_SUPPORT_FPU
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bool "Using Float"
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default y
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menuconfig BSP_USING_UART
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bool "Using UART"
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select RT_USING_SERIAL
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default y
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if BSP_USING_UART
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config BSP_USING_UART0
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bool "Enabel UART 0"
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default y
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endif
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config BSP_USING_GIC
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bool
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default y
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choice
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prompt "GIC Version"
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default BSP_USING_GICV2
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config BSP_USING_GICV2
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bool "GICv2"
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config BSP_USING_GICV3
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bool "GICv3"
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endchoice
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endmenu
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# RT-Thread building script for component
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd , cwd + '/zynqmp']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-04-11 liYony the first version
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*/
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#include <mmu.h>
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#include <board.h>
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#include <mm_aspace.h>
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#include <mm_page.h>
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#include <drv_uart.h>
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#include <gtimer.h>
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extern size_t MMUTable[];
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#ifdef RT_USING_SMART
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struct mem_desc platform_mem_desc[] = {
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{KERNEL_VADDR_START, KERNEL_VADDR_START + 0x7FF00000 - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM}
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};
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#else
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struct mem_desc platform_mem_desc[] =
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{
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{0x00200000, 0x7FF00000 - 1, 0x00200000, NORMAL_MEM},
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{GIC400_DISTRIBUTOR_PPTR, GIC400_DISTRIBUTOR_PPTR + GIC400_SIZE - 1, GIC400_DISTRIBUTOR_PPTR, DEVICE_MEM},
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{GIC400_CONTROLLER_PPTR, GIC400_CONTROLLER_PPTR + GIC400_SIZE - 1, GIC400_CONTROLLER_PPTR, DEVICE_MEM},
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};
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#endif
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const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
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void idle_wfi(void)
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{
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asm volatile("wfi");
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}
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void rt_hw_board_init(void)
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{
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#ifdef RT_USING_SMART
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rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
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#else
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rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xffffd0000000, 0x10000000, MMUTable, 0);
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#endif
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rt_region_t init_page_region;
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init_page_region.start = PAGE_START;
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init_page_region.end = PAGE_END;
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rt_page_init(init_page_region);
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rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
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#ifdef RT_USING_HEAP
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/* initialize system heap */
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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/* initialize hardware interrupt */
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rt_hw_interrupt_init();
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/* initialize uart */
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rt_hw_uart_init();
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/* initialize timer for os tick */
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rt_hw_gtimer_init();
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rt_thread_idle_sethook(idle_wfi);
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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rt_kprintf("heap: [0x%08x - 0x%08x]\n", HEAP_BEGIN, HEAP_END);
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-04-11 liYony the first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <zynqmp.h>
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extern unsigned char __bss_end;
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#define HEAP_BEGIN ((void*)&__bss_end)
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#ifdef RT_USING_SMART
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#define HEAP_END ((size_t)KERNEL_VADDR_START + 64 * 1024 * 1024)
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#define PAGE_START HEAP_END
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#define PAGE_END ((size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
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#else
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#define KERNEL_VADDR_START 0x0
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#define HEAP_END (KERNEL_VADDR_START + 64 * 1024 * 1024)
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#define PAGE_START HEAP_END
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#define PAGE_END ((size_t)PAGE_START + 64 * 1024 * 1024)
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#endif
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void rt_hw_board_init(void);
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int rt_hw_uart_init(void);
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#endif /* __BOARD_H__ */
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-04-11 liYony the first version
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*/
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#include <rthw.h>
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#include <rtdevice.h>
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#include <drv_uart.h>
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#include "board.h"
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#include "zynqmp_uart.h"
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#define ZYNQMP_UART_DEVICE_DEFAULT(base, irq, clk) {{ \
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.ops = &_zynqmp_ops, \
|
||||
.config = RT_SERIAL_CONFIG_DEFAULT \
|
||||
}, \
|
||||
.hw_base = base, \
|
||||
.irqno = irq, \
|
||||
.in_clk = clk \
|
||||
}
|
||||
|
||||
struct zynqmp_uart_device
|
||||
{
|
||||
struct rt_serial_device device;
|
||||
rt_ubase_t hw_base;
|
||||
rt_uint32_t irqno;
|
||||
rt_uint32_t in_clk;
|
||||
};
|
||||
|
||||
static void _uart_set_fifo_threshold(rt_ubase_t base, rt_uint8_t trigger_level)
|
||||
{
|
||||
rt_uint32_t reg_triger;
|
||||
|
||||
/* Assert validates the input arguments */
|
||||
RT_ASSERT(base != RT_NULL);
|
||||
RT_ASSERT(trigger_level <= (rt_uint8_t)XUARTPS_RXWM_MASK);
|
||||
|
||||
reg_triger = ((rt_uint32_t)trigger_level) & (rt_uint32_t)XUARTPS_RXWM_MASK;
|
||||
|
||||
/*
|
||||
* Write the new value for the FIFO control register to it such that the
|
||||
* threshold is changed
|
||||
*/
|
||||
writel(reg_triger, base + XUARTPS_RXWM_OFFSET);
|
||||
}
|
||||
|
||||
static void _uart_set_interrupt_mask(rt_ubase_t base, rt_uint32_t mask)
|
||||
{
|
||||
rt_uint32_t temp_mask = mask;
|
||||
|
||||
RT_ASSERT(base != RT_NULL);
|
||||
|
||||
temp_mask &= (rt_uint32_t)XUARTPS_IXR_MASK;
|
||||
|
||||
writel(temp_mask, base + XUARTPS_IER_OFFSET);
|
||||
writel((~temp_mask), base + XUARTPS_IDR_OFFSET);
|
||||
}
|
||||
|
||||
static rt_err_t _uart_baudrate_init(rt_ubase_t base, struct serial_configure *cfg, rt_uint32_t in_clk)
|
||||
{
|
||||
rt_uint32_t iter_baud_div; /* Iterator for available baud divisor values */
|
||||
rt_uint32_t brgr_value; /* Calculated value for baud rate generator */
|
||||
rt_uint32_t calc_baudrate; /* Calculated baud rate */
|
||||
rt_uint32_t baud_error; /* Diff between calculated and requested baud rate */
|
||||
rt_uint32_t best_brgr = 0U; /* Best value for baud rate generator */
|
||||
rt_uint8_t best_baud_div = 0U; /* Best value for baud divisor */
|
||||
rt_uint32_t best_error = 0xFFFFFFFFU;
|
||||
rt_uint32_t percent_error;
|
||||
rt_uint32_t mode_reg;
|
||||
rt_uint32_t input_clk;
|
||||
rt_uint32_t temp_reg;
|
||||
|
||||
/* Asserts validate the input arguments */
|
||||
RT_ASSERT(base != RT_NULL);
|
||||
RT_ASSERT(cfg->baud_rate <= (rt_uint32_t)XUARTPS_MAX_RATE);
|
||||
RT_ASSERT(cfg->baud_rate >= (rt_uint32_t)XUARTPS_MIN_RATE);
|
||||
|
||||
/*
|
||||
* Make sure the baud rate is not impossilby large.
|
||||
* Fastest possible baud rate is Input Clock / 2.
|
||||
*/
|
||||
if ((cfg->baud_rate * 2) > in_clk)
|
||||
{
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
/* Check whether the input clock is divided by 8 */
|
||||
mode_reg = readl(base + XUARTPS_MR_OFFSET);
|
||||
|
||||
input_clk = in_clk;
|
||||
if (mode_reg & XUARTPS_MR_CLKSEL)
|
||||
{
|
||||
input_clk = in_clk / 8;
|
||||
}
|
||||
|
||||
/*
|
||||
* Determine the Baud divider. It can be 4to 254.
|
||||
* Loop through all possible combinations
|
||||
*/
|
||||
for (iter_baud_div = 4; iter_baud_div < 255; iter_baud_div++)
|
||||
{
|
||||
|
||||
/* Calculate the value for BRGR register */
|
||||
brgr_value = input_clk / (cfg->baud_rate * (iter_baud_div + 1));
|
||||
|
||||
/* Calculate the baud rate from the BRGR value */
|
||||
calc_baudrate = input_clk / (brgr_value * (iter_baud_div + 1));
|
||||
|
||||
/* Avoid unsigned integer underflow */
|
||||
if (cfg->baud_rate > calc_baudrate)
|
||||
{
|
||||
baud_error = cfg->baud_rate - calc_baudrate;
|
||||
}
|
||||
else
|
||||
{
|
||||
baud_error = calc_baudrate - cfg->baud_rate;
|
||||
}
|
||||
|
||||
/* Find the calculated baud rate closest to requested baud rate. */
|
||||
if (best_error > baud_error)
|
||||
{
|
||||
|
||||
best_brgr = brgr_value;
|
||||
best_baud_div = iter_baud_div;
|
||||
best_error = baud_error;
|
||||
}
|
||||
}
|
||||
|
||||
/* Make sure the best error is not too large. */
|
||||
percent_error = (best_error * 100) / cfg->baud_rate;
|
||||
if (XUARTPS_MAX_BAUD_ERROR_RATE < percent_error)
|
||||
{
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
/* Disable TX and RX to avoid glitches when setting the baud rate. */
|
||||
temp_reg = (((readl(base + XUARTPS_CR_OFFSET)) & ((rt_uint32_t)(~XUARTPS_CR_EN_DIS_MASK))) |
|
||||
((rt_uint32_t)XUARTPS_CR_RX_DIS | (rt_uint32_t)XUARTPS_CR_TX_DIS));
|
||||
writel(temp_reg, base + XUARTPS_CR_OFFSET);
|
||||
|
||||
/* Set the baud rate divisor */
|
||||
writel(best_brgr, base + XUARTPS_BAUDGEN_OFFSET);
|
||||
writel(best_baud_div, base + XUARTPS_BAUDDIV_OFFSET);
|
||||
|
||||
/* RX and TX SW reset */
|
||||
writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST, base + XUARTPS_CR_OFFSET);
|
||||
|
||||
/* Enable device */
|
||||
temp_reg = (((readl(base + XUARTPS_CR_OFFSET)) & ((rt_uint32_t)(~XUARTPS_CR_EN_DIS_MASK))) |
|
||||
((rt_uint32_t)XUARTPS_CR_RX_EN | (rt_uint32_t)XUARTPS_CR_TX_EN));
|
||||
writel(temp_reg, base + XUARTPS_CR_OFFSET);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t zynqmp_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)serial;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
if (_uart_baudrate_init(uart->hw_base, cfg, uart->in_clk) != RT_EOK)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
rt_uint32_t mode_reg = 0U;
|
||||
|
||||
/* Set the parity mode */
|
||||
mode_reg = readl(uart->hw_base + XUARTPS_MR_OFFSET);
|
||||
|
||||
/* Mask off what's already there */
|
||||
mode_reg &= (~((rt_uint32_t)XUARTPS_MR_CHARLEN_MASK |
|
||||
(rt_uint32_t)XUARTPS_MR_STOPMODE_MASK |
|
||||
(rt_uint32_t)XUARTPS_MR_PARITY_MASK));
|
||||
|
||||
switch (cfg->data_bits)
|
||||
{
|
||||
case DATA_BITS_6:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_CHARLEN_6_BIT;
|
||||
break;
|
||||
case DATA_BITS_7:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_CHARLEN_7_BIT;
|
||||
break;
|
||||
case DATA_BITS_8:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_CHARLEN_8_BIT;
|
||||
break;
|
||||
default:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_CHARLEN_8_BIT;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (cfg->stop_bits)
|
||||
{
|
||||
case STOP_BITS_1:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_STOPMODE_1_BIT;
|
||||
break;
|
||||
case STOP_BITS_2:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_STOPMODE_2_BIT;
|
||||
break;
|
||||
default:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_STOPMODE_1_BIT;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (cfg->parity)
|
||||
{
|
||||
case PARITY_NONE:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_PARITY_NONE;
|
||||
break;
|
||||
case PARITY_ODD:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_PARITY_ODD;
|
||||
break;
|
||||
case PARITY_EVEN:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_PARITY_EVEN;
|
||||
break;
|
||||
default:
|
||||
mode_reg |= (rt_uint32_t)XUARTPS_MR_PARITY_NONE;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Write the mode register out */
|
||||
writel(mode_reg, uart->hw_base + XUARTPS_MR_OFFSET);
|
||||
|
||||
/* Set the RX FIFO trigger at 8 data bytes. */
|
||||
writel(0x08U, uart->hw_base + XUARTPS_RXWM_OFFSET);
|
||||
|
||||
/* Set the RX timeout to 1, which will be 4 character time */
|
||||
writel(0x01U, uart->hw_base + XUARTPS_RXTOUT_OFFSET);
|
||||
|
||||
/* Disable all interrupts, polled mode is the default */
|
||||
writel(XUARTPS_IXR_MASK, uart->hw_base + XUARTPS_IDR_OFFSET);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t zynqmp_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)serial;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* Disable the UART Interrupt */
|
||||
rt_hw_interrupt_mask(uart->irqno);
|
||||
_uart_set_interrupt_mask(uart->hw_base, 0U);
|
||||
break;
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* Enable the UART Interrupt */
|
||||
_uart_set_fifo_threshold(uart->hw_base, 1);
|
||||
rt_hw_interrupt_umask(uart->irqno);
|
||||
_uart_set_interrupt_mask(uart->hw_base, XUARTPS_IXR_RXOVR);
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int zynqmp_uart_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)serial;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
/* Wait until there is space in TX FIFO */
|
||||
while ((readl(uart->hw_base + XUARTPS_SR_OFFSET) &
|
||||
XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL)
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
/* Write the byte into the TX FIFO */
|
||||
writel((rt_uint32_t)c, uart->hw_base + XUARTPS_FIFO_OFFSET);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int zynqmp_uart_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)serial;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
/* Wait until there is data */
|
||||
if ((readl(uart->hw_base + XUARTPS_SR_OFFSET) &
|
||||
XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int ch = readl(uart->hw_base + XUARTPS_FIFO_OFFSET);
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops _zynqmp_ops =
|
||||
{
|
||||
zynqmp_uart_configure,
|
||||
zynqmp_uart_control,
|
||||
zynqmp_uart_putc,
|
||||
zynqmp_uart_getc,
|
||||
};
|
||||
|
||||
#ifdef BSP_USING_UART0
|
||||
static struct zynqmp_uart_device _uart0_device =
|
||||
ZYNQMP_UART_DEVICE_DEFAULT(ZYNQMP_UART0_BASE, ZYNQMP_UART0_IRQNUM, ZYNQMP_UART0_CLK_FREQ_HZ);
|
||||
#endif
|
||||
|
||||
static void rt_hw_uart_isr(int irqno, void *param)
|
||||
{
|
||||
struct zynqmp_uart_device *uart = (struct zynqmp_uart_device *)param;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
struct rt_serial_device *serial = &(uart->device);
|
||||
rt_uint32_t isr_status;
|
||||
|
||||
isr_status = readl(uart->hw_base + XUARTPS_IMR_OFFSET);
|
||||
isr_status &= readl(uart->hw_base + XUARTPS_ISR_OFFSET);
|
||||
if (isr_status & (rt_uint32_t)XUARTPS_IXR_RXOVR)
|
||||
{
|
||||
writel(XUARTPS_IXR_RXOVR, uart->hw_base + XUARTPS_ISR_OFFSET);
|
||||
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
||||
}
|
||||
}
|
||||
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
struct zynqmp_uart_device *uart = RT_NULL;
|
||||
|
||||
#ifdef BSP_USING_UART0
|
||||
uart = &_uart0_device;
|
||||
_uart0_device.hw_base = (rt_size_t)rt_ioremap((void*)_uart0_device.hw_base, ZYNQMP_UART0_SIZE);
|
||||
/* register UART0 device */
|
||||
rt_hw_serial_register(&uart->device, "uart0",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
||||
uart);
|
||||
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, uart, "uart0");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-11 liYony the first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_UART_H__
|
||||
#define __DRV_UART_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
int rt_hw_uart_init(void);
|
||||
|
||||
#endif /* __DRV_UART_H__ */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-11 liYony the first version
|
||||
*/
|
||||
|
||||
#ifndef __ZYNQMP_H__
|
||||
#define __ZYNQMP_H__
|
||||
|
||||
#include <rtdef.h>
|
||||
#include <ioremap.h>
|
||||
|
||||
#ifdef RT_USING_SMART
|
||||
#include <mmu.h>
|
||||
#endif
|
||||
|
||||
#define __REG32(x) (*((volatile unsigned int *)(x)))
|
||||
#define __REG16(x) (*((volatile unsigned short *)(x)))
|
||||
|
||||
/* UART */
|
||||
#define ZYNQMP_UART0_BASE 0xFF000000
|
||||
#define ZYNQMP_UART0_SIZE 0x00010000
|
||||
#define ZYNQMP_UART0_IRQNUM (32 + 21)
|
||||
#define ZYNQMP_UART0_CLK_FREQ_HZ (99999001)
|
||||
|
||||
/* GIC */
|
||||
#define MAX_HANDLERS 195
|
||||
#define GIC_IRQ_START 0
|
||||
#define ARM_GIC_NR_IRQS 195
|
||||
#define ARM_GIC_MAX_NR 1
|
||||
|
||||
/* GICv2 */
|
||||
#define GIC400_DISTRIBUTOR_PPTR 0xF9010000U
|
||||
#define GIC400_CONTROLLER_PPTR 0xF9020000U
|
||||
#define GIC400_SIZE 0x00001000U
|
||||
|
||||
/* the basic constants and interfaces needed by gic */
|
||||
rt_inline rt_ubase_t platform_get_gic_dist_base(void)
|
||||
{
|
||||
return GIC400_DISTRIBUTOR_PPTR;
|
||||
}
|
||||
|
||||
rt_inline rt_ubase_t platform_get_gic_cpu_base(void)
|
||||
{
|
||||
return GIC400_CONTROLLER_PPTR;
|
||||
}
|
||||
|
||||
#endif /* __ZYNQMP_H__ */
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __ZYNQMP_REG_H__
|
||||
#define __ZYNQMP_REG_H__
|
||||
|
||||
/* bit field helpers. */
|
||||
#define __M(n) (~(~0<<(n)))
|
||||
#define __RBF(number, n) ((number)&__M(n))
|
||||
#define __BF(number, n, m) __RBF((number>>m), (n-m+1))
|
||||
#define REG_BF(number, n, m) (m<n ? __BF(number, n, m) : __BF(number, m, n))
|
||||
|
||||
#define readb(reg) (*((volatile unsigned char *)(reg)))
|
||||
#define readw(reg) (*((volatile unsigned short *)(reg)))
|
||||
#define readl(reg) (*((volatile unsigned int *)(reg)))
|
||||
#define readq(reg) (*((volatile unsigned long long *)(reg)))
|
||||
|
||||
#define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data))
|
||||
#define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data))
|
||||
#define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data))
|
||||
#define writeq(data, reg) ((*((volatile unsigned long long *)(reg))) = (unsigned long long)(data))
|
||||
|
||||
#define clrsetreg(addr, clr, set) writel(((clr) | (set)) << 16 | (set), addr)
|
||||
#define clrreg(addr, clr) writel((clr) << 16, addr)
|
||||
#define setreg(addr, set) writel((set) << 16 | (set), addr)
|
||||
|
||||
#define DUMP_REG(base, reg) \
|
||||
do { \
|
||||
rt_uint32_t status = 0x00000000; \
|
||||
status = readl(base + reg); \
|
||||
rt_kprintf(#reg ":\n"); \
|
||||
rt_kprintf("\t%p 0x%.8x\n", base + reg, status); \
|
||||
} while(0);
|
||||
|
||||
#endif /* __ZYNQMP_REG_H__ */
|
||||
|
|
@ -0,0 +1,300 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __ZYNQMP_UART_H__
|
||||
#define __ZYNQMP_UART_H__
|
||||
|
||||
#include <zynqmp_reg.h>
|
||||
|
||||
/* The following constant defines the amount of error that is allowed for
|
||||
* a specified baud rate. This error is the difference between the actual
|
||||
* baud rate that will be generated using the specified clock and the
|
||||
* desired baud rate.
|
||||
*/
|
||||
#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
|
||||
|
||||
/*
|
||||
* The following constants indicate the max and min baud rates and these
|
||||
* numbers are based only on the testing that has been done. The hardware
|
||||
* is capable of other baud rates.
|
||||
*/
|
||||
#define XUARTPS_MAX_RATE 6240000U
|
||||
#define XUARTPS_MIN_RATE 110U
|
||||
|
||||
/** @name Register Map
|
||||
*
|
||||
* Register offsets for the UART.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
|
||||
#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
|
||||
#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
|
||||
#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
|
||||
#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
|
||||
#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
|
||||
#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
|
||||
#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
|
||||
#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
|
||||
#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
|
||||
#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
|
||||
#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
|
||||
#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
|
||||
#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
|
||||
#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
|
||||
#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
|
||||
#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
|
||||
/* @} */
|
||||
|
||||
/** @name Control Register
|
||||
*
|
||||
* The Control register (CR) controls the major functions of the device.
|
||||
*
|
||||
* Control Register Bit Definition
|
||||
*/
|
||||
#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
|
||||
#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
|
||||
#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
|
||||
#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
|
||||
#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
|
||||
#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
|
||||
#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
|
||||
#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
|
||||
#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
|
||||
#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
|
||||
/* @}*/
|
||||
|
||||
/** @name Mode Register
|
||||
*
|
||||
* The mode register (MR) defines the mode of transfer as well as the data
|
||||
* format. If this register is modified during transmission or reception,
|
||||
* data validity cannot be guaranteed.
|
||||
*
|
||||
* Mode Register Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
|
||||
#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
|
||||
#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
|
||||
#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
|
||||
#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
|
||||
#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
|
||||
#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
|
||||
#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
|
||||
#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
|
||||
#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
|
||||
#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
|
||||
#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
|
||||
#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
|
||||
#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
|
||||
#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
|
||||
#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
|
||||
#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
|
||||
#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
|
||||
#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
|
||||
#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
|
||||
#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
|
||||
#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
|
||||
#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
|
||||
#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
|
||||
#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
|
||||
/* @} */
|
||||
|
||||
/** @name Interrupt Registers
|
||||
*
|
||||
* Interrupt control logic uses the interrupt enable register (IER) and the
|
||||
* interrupt disable register (IDR) to set the value of the bits in the
|
||||
* interrupt mask register (IMR). The IMR determines whether to pass an
|
||||
* interrupt to the interrupt status register (ISR).
|
||||
* Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
|
||||
* interrupt. IMR and ISR are read only, and IER and IDR are write only.
|
||||
* Reading either IER or IDR returns 0x00.
|
||||
*
|
||||
* All four registers have the same bit definitions.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
|
||||
#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
|
||||
#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
|
||||
#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
|
||||
#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
|
||||
#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
|
||||
#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
|
||||
#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
|
||||
#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
|
||||
#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
|
||||
#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
|
||||
#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
|
||||
#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
|
||||
#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
|
||||
#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
|
||||
/* @} */
|
||||
|
||||
/** @name Baud Rate Generator Register
|
||||
*
|
||||
* The baud rate generator control register (BRGR) is a 16 bit register that
|
||||
* controls the receiver bit sample clock and baud rate.
|
||||
* Valid values are 1 - 65535.
|
||||
*
|
||||
* Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
|
||||
* in the MR register.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
|
||||
#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
|
||||
#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
|
||||
|
||||
/** @name Baud Divisor Rate register
|
||||
*
|
||||
* The baud rate divider register (BDIV) controls how much the bit sample
|
||||
* rate is divided by. It sets the baud rate.
|
||||
* Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
|
||||
*
|
||||
* Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
|
||||
* the MR_CCLK bit in the MR register.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
|
||||
#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name Receiver Timeout Register
|
||||
*
|
||||
* Use the receiver timeout register (RTR) to detect an idle condition on
|
||||
* the receiver data line.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
|
||||
#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
|
||||
|
||||
/** @name Receiver FIFO Trigger Level Register
|
||||
*
|
||||
* Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
|
||||
* which the RX FIFO triggers an interrupt event.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
|
||||
#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
|
||||
#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name Transmit FIFO Trigger Level Register
|
||||
*
|
||||
* Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
|
||||
* which the TX FIFO triggers an interrupt event.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
|
||||
#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name Modem Control Register
|
||||
*
|
||||
* This register (MODEMCR) controls the interface with the modem or data set,
|
||||
* or a peripheral device emulating a modem.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
|
||||
#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
|
||||
#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
|
||||
/* @} */
|
||||
|
||||
/** @name Modem Status Register
|
||||
*
|
||||
* This register (MODEMSR) indicates the current state of the control lines
|
||||
* from a modem, or another peripheral device, to the CPU. In addition, four
|
||||
* bits of the modem status register provide change information. These bits
|
||||
* are set to a logic 1 whenever a control input from the modem changes state.
|
||||
*
|
||||
* Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
|
||||
* status interrupt is generated and this is reflected in the modem status
|
||||
* register.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
|
||||
#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
|
||||
#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
|
||||
#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
|
||||
#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
|
||||
#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
|
||||
#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
|
||||
#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
|
||||
#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
|
||||
/* @} */
|
||||
|
||||
/** @name Channel Status Register
|
||||
*
|
||||
* The channel status register (CSR) is provided to enable the control logic
|
||||
* to monitor the status of bits in the channel interrupt status register,
|
||||
* even if these are masked out by the interrupt mask register.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
|
||||
#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
|
||||
#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
|
||||
#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
|
||||
#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
|
||||
#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
|
||||
#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
|
||||
#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
|
||||
#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
|
||||
#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
|
||||
/* @} */
|
||||
|
||||
/** @name Flow Delay Register
|
||||
*
|
||||
* Operation of the flow delay register (FLOWDEL) is very similar to the
|
||||
* receive FIFO trigger register. An internal trigger signal activates when the
|
||||
* FIFO is filled to the level set by this register. This trigger will not
|
||||
* cause an interrupt, although it can be read through the channel status
|
||||
* register. In hardware flow control mode, RTS is deactivated when the trigger
|
||||
* becomes active. RTS only resets when the FIFO level is four less than the
|
||||
* level of the flow delay trigger and the flow delay trigger is not activated.
|
||||
* A value less than 4 disables the flow delay.
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
|
||||
/* @} */
|
||||
|
||||
/** @name Receiver FIFO Byte Status Register
|
||||
*
|
||||
* The Receiver FIFO Status register is used to have a continuous
|
||||
* monitoring of the raw unmasked byte status information. The register
|
||||
* contains frame, parity and break status information for the top
|
||||
* four bytes in the RX FIFO.
|
||||
*
|
||||
* Receiver FIFO Byte Status Register Bit Definition
|
||||
* @{
|
||||
*/
|
||||
#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
|
||||
#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
|
||||
#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
|
||||
#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
|
||||
#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
|
||||
#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
|
||||
#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
|
||||
#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
|
||||
#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
|
||||
#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
|
||||
#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
|
||||
#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
|
||||
#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
|
||||
/* @} */
|
||||
|
||||
/*
|
||||
* Defines for backwards compatibility, will be removed
|
||||
* in the next version of the driver
|
||||
*/
|
||||
#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
|
||||
#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
|
||||
#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
|
||||
#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
|
||||
|
||||
#endif /* __ZYNQMP_UART_H__ */
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 2.7 MiB |
Binary file not shown.
|
After Width: | Height: | Size: 752 KiB |
|
|
@ -0,0 +1,337 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Project Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 16
|
||||
#define RT_CPUS_NR 4
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 8192
|
||||
#define RT_USING_TIMER_SOFT
|
||||
#define RT_TIMER_THREAD_PRIO 4
|
||||
#define RT_TIMER_THREAD_STACK_SIZE 8192
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
#define RT_KSERVICE_USING_STDLIB
|
||||
#define RT_KPRINTF_USING_LONGLONG
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_PAGE_MAX_ORDER 11
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_MEMHEAP
|
||||
#define RT_MEMHEAP_FAST_MODE
|
||||
#define RT_USING_MEMHEAP_AS_HEAP
|
||||
#define RT_USING_MEMHEAP_AUTO_BINDING
|
||||
#define RT_USING_MEMTRACE
|
||||
#define RT_USING_HEAP
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_DEVICE_OPS
|
||||
#define RT_USING_INTERRUPT_INFO
|
||||
#define RT_USING_SCHED_THREAD_CTX
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 256
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart0"
|
||||
#define RT_VER_NUM 0x50100
|
||||
#define RT_USING_STDC_ATOMIC
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
|
||||
/* AArch64 Architecture Configuration */
|
||||
|
||||
#define ARCH_TEXT_OFFSET 0x200000
|
||||
#define ARCH_RAM_OFFSET 0x0
|
||||
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
|
||||
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
|
||||
#define ARCH_CPU_64BIT
|
||||
#define RT_USING_CACHE
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_MM_MMU
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_MMU
|
||||
#define ARCH_ARMV8
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 8192
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 10
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 256
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_POSIX
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FD_MAX 32
|
||||
#define RT_USING_DFS_V2
|
||||
#define RT_USING_DFS_ELMFAT
|
||||
|
||||
/* elm-chan's FatFs, Generic FAT Filesystem Module */
|
||||
|
||||
#define RT_DFS_ELM_CODE_PAGE 437
|
||||
#define RT_DFS_ELM_WORD_ACCESS
|
||||
#define RT_DFS_ELM_USE_LFN_3
|
||||
#define RT_DFS_ELM_USE_LFN 3
|
||||
#define RT_DFS_ELM_LFN_UNICODE_0
|
||||
#define RT_DFS_ELM_LFN_UNICODE 0
|
||||
#define RT_DFS_ELM_MAX_LFN 255
|
||||
#define RT_DFS_ELM_DRIVES 2
|
||||
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
|
||||
#define RT_DFS_ELM_REENTRANT
|
||||
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
|
||||
#define RT_USING_DFS_DEVFS
|
||||
#define RT_USING_DFS_ROMFS
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SYSTEM_WORKQUEUE
|
||||
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
|
||||
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 256
|
||||
#define RT_USING_NULL
|
||||
#define RT_USING_ZERO
|
||||
#define RT_USING_RANDOM
|
||||
#define RT_USING_PM
|
||||
#define PM_TICKLESS_THRESHOLD_TIME 2
|
||||
#define RT_USING_RTC
|
||||
#define RT_USING_SOFT_RTC
|
||||
#define RT_USING_DEV_BUS
|
||||
#define RT_USING_VIRTIO
|
||||
#define RT_USING_VIRTIO10
|
||||
#define RT_USING_VIRTIO_MMIO_ALIGN
|
||||
#define RT_USING_VIRTIO_BLK
|
||||
#define RT_USING_VIRTIO_CONSOLE
|
||||
#define RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR 4
|
||||
#define RT_USING_VIRTIO_GPU
|
||||
#define RT_USING_VIRTIO_INPUT
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_KTIME
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
#define RT_USING_POSIX_FS
|
||||
#define RT_USING_POSIX_DEVIO
|
||||
#define RT_USING_POSIX_STDIO
|
||||
#define RT_USING_POSIX_POLL
|
||||
#define RT_USING_POSIX_SELECT
|
||||
#define RT_USING_POSIX_TERMIOS
|
||||
#define RT_USING_POSIX_DELAY
|
||||
#define RT_USING_POSIX_CLOCK
|
||||
#define RT_USING_POSIX_TIMER
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
#define RT_USING_POSIX_PIPE
|
||||
#define RT_USING_POSIX_PIPE_SIZE 512
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
|
||||
/* Network */
|
||||
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
#define RT_USING_RESOURCE_ID
|
||||
#define RT_USING_ADT
|
||||
#define RT_USING_ADT_AVL
|
||||
#define RT_USING_ADT_BITMAP
|
||||
#define RT_USING_ADT_HASHMAP
|
||||
#define RT_USING_ADT_REF
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
|
||||
/* AI packages */
|
||||
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
|
||||
/* Sensors */
|
||||
|
||||
|
||||
/* Display */
|
||||
|
||||
|
||||
/* Timing */
|
||||
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
|
||||
/* Device Control */
|
||||
|
||||
|
||||
/* Other */
|
||||
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
#define SOC_ZYNQMP_AARCH64
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define BSP_SUPPORT_FPU
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART0
|
||||
#define BSP_USING_GIC
|
||||
#define BSP_USING_GICV2
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH ='aarch64'
|
||||
CPU ='cortex-a'
|
||||
CROSS_TOOL = 'gcc'
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin'
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
CPP = PREFIX + 'cpp'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
CFPFLAGS = ' '
|
||||
AFPFLAGS = ' '
|
||||
DEVICE = ' -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
|
||||
|
||||
CPPFLAGS= ' -E -P -x assembler-with-cpp'
|
||||
CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always'
|
||||
CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -fdiagnostics-color=always'
|
||||
AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static'
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2'
|
||||
CXXFLAGS += ' -O0 -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -Os'
|
||||
CXXFLAGS += ' -Os'
|
||||
CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
|
||||
|
||||
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
Loading…
Reference in New Issue