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Use astyle to format the drv_pin.c

This commit is contained in:
BalanceTWK 2019-01-27 21:36:07 +08:00
parent 70738c3711
commit e7c5fa13f5
1 changed files with 270 additions and 270 deletions
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96
bsp/imxrt/Libraries/imxrt1050/drivers/drv_pin.c
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@ -17,7 +17,7 @@
#ifdef RT_USING_PIN #ifdef RT_USING_PIN
#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
#endif #endif
struct rt1052_pin struct rt1052_pin
@ -218,9 +218,9 @@ static struct rt1052_irq rt1052_irq_map[] =
{PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} } {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }
}; };
void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin) void gpio_isr(GPIO_Type *base, rt_uint32_t gpio_pin)
{ {
if((GPIO_PortGetInterruptFlags(base) & (1 << gpio_pin)) != 0) if ((GPIO_PortGetInterruptFlags(base) & (1 << gpio_pin)) != 0)
{ {
GPIO_PortClearInterruptFlags(base, (1 << gpio_pin)); GPIO_PortClearInterruptFlags(base, (1 << gpio_pin));
@ -237,7 +237,7 @@ void GPIO1_Combined_0_15_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) for (gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
{ {
gpio_isr(GPIO1, gpio_pin); gpio_isr(GPIO1, gpio_pin);
} }
@ -251,7 +251,7 @@ void GPIO1_Combined_16_31_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) for (gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
{ {
gpio_isr(GPIO1, gpio_pin); gpio_isr(GPIO1, gpio_pin);
} }
@ -265,7 +265,7 @@ void GPIO2_Combined_0_15_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) for (gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
{ {
gpio_isr(GPIO2, gpio_pin); gpio_isr(GPIO2, gpio_pin);
} }
@ -279,7 +279,7 @@ void GPIO2_Combined_16_31_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) for (gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
{ {
gpio_isr(GPIO2, gpio_pin); gpio_isr(GPIO2, gpio_pin);
} }
@ -293,7 +293,7 @@ void GPIO3_Combined_0_15_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) for (gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
{ {
gpio_isr(GPIO3, gpio_pin); gpio_isr(GPIO3, gpio_pin);
} }
@ -307,7 +307,7 @@ void GPIO3_Combined_16_31_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) for (gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
{ {
gpio_isr(GPIO3, gpio_pin); gpio_isr(GPIO3, gpio_pin);
} }
@ -321,7 +321,7 @@ void GPIO4_Combined_0_15_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++) for (gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
{ {
gpio_isr(GPIO4, gpio_pin); gpio_isr(GPIO4, gpio_pin);
} }
@ -334,7 +334,7 @@ void GPIO4_Combined_16_31_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++) for (gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
{ {
gpio_isr(GPIO4, gpio_pin); gpio_isr(GPIO4, gpio_pin);
} }
@ -348,7 +348,7 @@ void GPIO5_Combined_0_15_IRQHandler(void)
rt_interrupt_enter(); rt_interrupt_enter();
for(gpio_pin = 0; gpio_pin <= 2; gpio_pin++) for (gpio_pin = 0; gpio_pin <= 2; gpio_pin++)
{ {
gpio_isr(GPIO5, gpio_pin); gpio_isr(GPIO5, gpio_pin);
} }
@ -360,9 +360,9 @@ static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
{ {
IRQn_Type irq_num = NotAvail_IRQn; /* Invalid interrupt number */ IRQn_Type irq_num = NotAvail_IRQn; /* Invalid interrupt number */
if(gpio == GPIO1) if (gpio == GPIO1)
{ {
if(gpio_pin <= 15) if (gpio_pin <= 15)
{ {
irq_num = GPIO1_Combined_0_15_IRQn; irq_num = GPIO1_Combined_0_15_IRQn;
} }
@ -371,9 +371,9 @@ static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
irq_num = GPIO1_Combined_16_31_IRQn; irq_num = GPIO1_Combined_16_31_IRQn;
} }
} }
else if(gpio == GPIO2) else if (gpio == GPIO2)
{ {
if(gpio_pin <= 15) if (gpio_pin <= 15)
{ {
irq_num = GPIO2_Combined_0_15_IRQn; irq_num = GPIO2_Combined_0_15_IRQn;
} }
@ -382,9 +382,9 @@ static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
irq_num = GPIO2_Combined_16_31_IRQn; irq_num = GPIO2_Combined_16_31_IRQn;
} }
} }
else if(gpio == GPIO3) else if (gpio == GPIO3)
{ {
if(gpio_pin <= 15) if (gpio_pin <= 15)
{ {
irq_num = GPIO3_Combined_0_15_IRQn; irq_num = GPIO3_Combined_0_15_IRQn;
} }
@ -393,9 +393,9 @@ static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
irq_num = GPIO3_Combined_16_31_IRQn; irq_num = GPIO3_Combined_16_31_IRQn;
} }
} }
else if(gpio == GPIO4) else if (gpio == GPIO4)
{ {
if(gpio_pin <= 15) if (gpio_pin <= 15)
{ {
irq_num = GPIO4_Combined_0_15_IRQn; irq_num = GPIO4_Combined_0_15_IRQn;
} }
@ -404,9 +404,9 @@ static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
irq_num = GPIO4_Combined_16_31_IRQn; irq_num = GPIO4_Combined_16_31_IRQn;
} }
} }
else if(gpio == GPIO5) else if (gpio == GPIO5)
{ {
if(gpio_pin <= 15) if (gpio_pin <= 15)
{ {
irq_num = GPIO5_Combined_0_15_IRQn; irq_num = GPIO5_Combined_0_15_IRQn;
} }
@ -424,26 +424,26 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
gpio_pin_config_t gpio; gpio_pin_config_t gpio;
rt_uint32_t config_value = 0; rt_uint32_t config_value = 0;
if((pin > __ARRAY_LEN(rt1052_pin_map)) || (pin == 0)) if ((pin > __ARRAY_LEN(rt1052_pin_map)) || (pin == 0))
{ {
return; return;
} }
if(rt1052_pin_map[pin].gpio != GPIO5) if (rt1052_pin_map[pin].gpio != GPIO5)
{ {
CLOCK_EnableClock(kCLOCK_Iomuxc); CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 1); IOMUXC_SetPinMux(0x401F8010U + pin * 4, 0x5U, 0, 0, 0, 1);
} }
else else
{ {
CLOCK_EnableClock(kCLOCK_IomuxcSnvs); CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 1); IOMUXC_SetPinMux(0x400A8000U + (pin - 125) * 4, 0x5U, 0, 0, 0, 1);
} }
gpio.outputLogic = 0; gpio.outputLogic = 0;
gpio.interruptMode = kGPIO_NoIntmode; gpio.interruptMode = kGPIO_NoIntmode;
switch(mode) switch (mode)
{ {
case PIN_MODE_OUTPUT: case PIN_MODE_OUTPUT:
{ {
@ -481,13 +481,13 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
break; break;
} }
if(rt1052_pin_map[pin].gpio != GPIO5) if (rt1052_pin_map[pin].gpio != GPIO5)
{ {
IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value); IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin * 4, config_value);
} }
else else
{ {
IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value); IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin - 125) * 4, config_value);
} }
GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio);
@ -506,18 +506,18 @@ static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
static rt_err_t rt1052_pin_attach_irq(struct rt_device *device, rt_int32_t pin, static rt_err_t rt1052_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args) rt_uint32_t mode, void (*hdr)(void *args), void *args)
{ {
struct rt1052_pin* pin_map = RT_NULL; struct rt1052_pin *pin_map = RT_NULL;
struct rt1052_irq* irq_map = RT_NULL; struct rt1052_irq *irq_map = RT_NULL;
pin_map = &rt1052_pin_map[pin]; pin_map = &rt1052_pin_map[pin];
irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
if(pin_map == RT_NULL || irq_map == RT_NULL) if (pin_map == RT_NULL || irq_map == RT_NULL)
{ {
return RT_ENOSYS; return RT_ENOSYS;
} }
if(irq_map->enable == PIN_IRQ_ENABLE) if (irq_map->enable == PIN_IRQ_ENABLE)
{ {
return RT_EBUSY; return RT_EBUSY;
} }
@ -532,18 +532,18 @@ static rt_err_t rt1052_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
static rt_err_t rt1052_pin_detach_irq(struct rt_device *device, rt_int32_t pin) static rt_err_t rt1052_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{ {
struct rt1052_pin* pin_map = RT_NULL; struct rt1052_pin *pin_map = RT_NULL;
struct rt1052_irq* irq_map = RT_NULL; struct rt1052_irq *irq_map = RT_NULL;
pin_map = &rt1052_pin_map[pin]; pin_map = &rt1052_pin_map[pin];
irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
if(pin_map == RT_NULL || irq_map == RT_NULL) if (pin_map == RT_NULL || irq_map == RT_NULL)
{ {
return RT_ENOSYS; return RT_ENOSYS;
} }
if(irq_map->enable == PIN_IRQ_DISABLE) if (irq_map->enable == PIN_IRQ_DISABLE)
{ {
return RT_EOK; return RT_EOK;
} }
@ -572,21 +572,21 @@ static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, r
return RT_ENOSYS; return RT_ENOSYS;
} }
if(enabled == PIN_IRQ_ENABLE) if (enabled == PIN_IRQ_ENABLE)
{ {
if(irq_map->enable == PIN_IRQ_ENABLE) if (irq_map->enable == PIN_IRQ_ENABLE)
{ {
return RT_EBUSY; return RT_EBUSY;
} }
if(irq_map->irq_info.pin != pin) if (irq_map->irq_info.pin != pin)
{ {
return RT_EIO; return RT_EIO;
} }
irq_map->enable = PIN_IRQ_ENABLE; irq_map->enable = PIN_IRQ_ENABLE;
if(rt1052_pin_map[pin].gpio != GPIO5) if (rt1052_pin_map[pin].gpio != GPIO5)
{ {
CLOCK_EnableClock(kCLOCK_Iomuxc); CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(0x401F8010U + pin * 4, 0x5U, 0, 0, 0, 1); IOMUXC_SetPinMux(0x401F8010U + pin * 4, 0x5U, 0, 0, 0, 1);
@ -600,7 +600,7 @@ static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, r
gpio.direction = kGPIO_DigitalInput; gpio.direction = kGPIO_DigitalInput;
gpio.outputLogic = 0; gpio.outputLogic = 0;
switch(irq_map->irq_info.mode) switch (irq_map->irq_info.mode)
{ {
case PIN_IRQ_MODE_RISING: case PIN_IRQ_MODE_RISING:
{ {
@ -638,13 +638,13 @@ static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, r
break; break;
} }
if(rt1052_pin_map[pin].gpio != GPIO5) if (rt1052_pin_map[pin].gpio != GPIO5)
{ {
IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value); IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin * 4, config_value);
} }
else else
{ {
IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value); IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin - 125) * 4, config_value);
} }
irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
@ -655,9 +655,9 @@ static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, r
GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio);
GPIO_PortEnableInterrupts(rt1052_pin_map[pin].gpio, 1U << rt1052_pin_map[pin].gpio_pin); GPIO_PortEnableInterrupts(rt1052_pin_map[pin].gpio, 1U << rt1052_pin_map[pin].gpio_pin);
} }
else if(enabled == PIN_IRQ_DISABLE) else if (enabled == PIN_IRQ_DISABLE)
{ {
if(irq_map->enable == PIN_IRQ_DISABLE) if (irq_map->enable == PIN_IRQ_DISABLE)
{ {
return RT_EOK; return RT_EOK;
} }