remove cortex-a53 from libcpu/arm
This commit is contained in:
bigmagic
parent
f6a13de08f
commit
e6600dbf10
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@ -1,168 +0,0 @@
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-09-15 Bernard first version
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*/
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#include "raspi.h"
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#ifndef __CP15_H__
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#define __CP15_H__
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#ifndef __STATIC_FORCEINLINE
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#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
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#endif
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#define __WFI() __asm__ volatile ("wfi":::"memory")
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#define __WFE() __asm__ volatile ("wfe":::"memory")
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#define __SEV() __asm__ volatile ("sev")
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__STATIC_FORCEINLINE void __ISB(void)
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{
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__asm__ volatile ("isb 0xF":::"memory");
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}
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/**
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\brief Data Synchronization Barrier
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\details Acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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__STATIC_FORCEINLINE void __DSB(void)
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{
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__asm__ volatile ("dsb 0xF":::"memory");
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}
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/**
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\brief Data Memory Barrier
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\details Ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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__STATIC_FORCEINLINE void __DMB(void)
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{
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__asm__ volatile ("dmb 0xF":::"memory");
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}
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#ifdef RT_USING_SMP
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static inline void send_ipi_msg(int cpu, int ipi_vector)
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{
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IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
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}
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static inline void setup_bootstrap_addr(int cpu, int addr)
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{
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CORE_MAILBOX3_SET(cpu) = addr;
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}
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static inline void enable_cpu_ipi_intr(int cpu)
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{
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COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
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}
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static inline void enable_cpu_timer_intr(int cpu)
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{
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CORETIMER_INTCTL(cpu) = 0x8;
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}
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static inline void enable_cntv(void)
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{
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rt_uint32_t cntv_ctl;
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cntv_ctl = 1;
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asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
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}
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static inline void disable_cntv(void)
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{
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rt_uint32_t cntv_ctl;
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cntv_ctl = 0;
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asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
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}
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static inline void mask_cntv(void)
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{
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rt_uint32_t cntv_ctl;
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cntv_ctl = 2;
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asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
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}
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static inline void unmask_cntv(void)
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{
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rt_uint32_t cntv_ctl;
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cntv_ctl = 1;
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asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
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}
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static inline rt_uint64_t read_cntvct(void)
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{
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rt_uint32_t val,val1;
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asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
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return (val);
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}
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static inline rt_uint64_t read_cntvoff(void)
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{
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rt_uint64_t val;
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asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
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return (val);
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}
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static inline rt_uint32_t read_cntv_tval(void)
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{
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rt_uint32_t val;
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asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val));
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return val;
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}
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static inline void write_cntv_tval(rt_uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val));
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return;
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}
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static inline rt_uint32_t read_cntfrq(void)
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{
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rt_uint32_t val;
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asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val));
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return val;
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}
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static inline rt_uint32_t read_cntctrl(void)
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{
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rt_uint32_t val;
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asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val));
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return val;
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}
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static inline uint32_t write_cntctrl(uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
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return val;
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}
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#endif
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unsigned long rt_cpu_get_smp_id(void);
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void rt_cpu_mmu_disable(void);
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void rt_cpu_mmu_enable(void);
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void rt_cpu_tlb_set(volatile unsigned long*);
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void rt_cpu_dcache_clean_flush(void);
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void rt_cpu_icache_flush(void);
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void rt_cpu_vector_set_base(unsigned int addr);
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void rt_hw_mmu_init(void);
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void rt_hw_vector_init(void);
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void set_timer_counter(unsigned int counter);
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void set_timer_control(unsigned int control);
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#endif
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@ -1,91 +0,0 @@
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-09-15 Bernard first version
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* 2019-07-28 zdzn add smp support
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <board.h>
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#include "cp15.h"
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int rt_hw_cpu_id(void)
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{
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int cpu_id;
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__asm__ volatile (
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"mrc p15, 0, %0, c0, c0, 5"
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:"=r"(cpu_id)
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);
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cpu_id &= 0xf;
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return cpu_id;
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};
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#ifdef RT_USING_SMP
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void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
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{
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lock->slock = 0;
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}
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void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
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{
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unsigned long tmp;
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unsigned long newval;
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rt_hw_spinlock_t lockval;
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__asm__ __volatile__(
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"pld [%0]"
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::"r"(&lock->slock)
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);
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__asm__ __volatile__(
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"1: ldrex %0, [%3]\n"
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" add %1, %0, %4\n"
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" strex %2, %1, [%3]\n"
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" teq %2, #0\n"
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" bne 1b"
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: "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
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: "r" (&lock->slock), "I" (1 << 16)
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: "cc");
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while (lockval.tickets.next != lockval.tickets.owner)
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{
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__WFE();
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lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
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}
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__DMB();
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}
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void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
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{
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__DMB();
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lock->tickets.owner++;
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__DSB();
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__SEV();
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}
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#endif /*RT_USING_SMP*/
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/**
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* @addtogroup ARM CPU
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*/
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/*@{*/
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/** shutdown CPU */
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void rt_hw_cpu_shutdown()
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{
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rt_uint32_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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/*@}*/
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@ -1,186 +0,0 @@
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/5/3 Bernard first version
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* 2019-07-28 zdzn add smp support
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* 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues,
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* write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "cp15.h"
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#include <board.h>
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#define MAX_HANDLERS 72
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#ifdef RT_USING_SMP
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#define rt_interrupt_nest rt_cpu_self()->irq_nest
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#else
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extern volatile rt_uint8_t rt_interrupt_nest;
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#endif
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const unsigned int VECTOR_BASE = 0x00;
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extern void rt_cpu_vector_set_base(unsigned int addr);
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extern int system_vectors;
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void rt_hw_vector_init(void)
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{
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rt_cpu_vector_set_base((unsigned int)&system_vectors);
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}
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/* exception and interrupt handler table */
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struct rt_irq_desc isr_table[MAX_HANDLERS];
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rt_uint32_t rt_interrupt_from_thread;
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rt_uint32_t rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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extern int system_vectors;
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static void default_isr_handler(int vector, void *param)
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{
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#ifdef RT_USING_SMP
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rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
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#else
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rt_kprintf("unhandled irq: %d\n",vector);
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#endif
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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rt_uint32_t index;
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/* mask all of interrupts */
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IRQ_DISABLE_BASIC = 0x000000ff;
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IRQ_DISABLE1 = 0xffffffff;
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IRQ_DISABLE2 = 0xffffffff;
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for (index = 0; index < MAX_HANDLERS; index ++)
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{
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isr_table[index].handler = default_isr_handler;
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isr_table[index].param = NULL;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
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isr_table[index].counter = 0;
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#endif
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}
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int vector)
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{
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if (vector < 32)
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{
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IRQ_DISABLE1 = (1 << vector);
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}
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else if (vector < 64)
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{
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vector = vector % 32;
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IRQ_DISABLE2 = (1 << vector);
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}
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else
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{
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vector = vector - 64;
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IRQ_DISABLE_BASIC = (1 << vector);
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}
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int vector)
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{
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if (vector < 32)
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{
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IRQ_ENABLE1 = (1 << vector);
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}
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else if (vector < 64)
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{
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vector = vector % 32;
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IRQ_ENABLE2 = (1 << vector);
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}
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else
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{
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vector = vector - 64;
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IRQ_ENABLE_BASIC = (1 << vector);
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}
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if (vector < MAX_HANDLERS)
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{
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old_handler = isr_table[vector].handler;
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if (handler != RT_NULL)
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{
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#ifdef RT_USING_INTERRUPT_INFO
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rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
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#endif /* RT_USING_INTERRUPT_INFO */
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isr_table[vector].handler = handler;
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isr_table[vector].param = param;
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}
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}
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return old_handler;
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}
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#ifdef RT_USING_SMP
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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{
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__DSB();
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if (cpu_mask & 0x1)
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{
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send_ipi_msg(0, ipi_vector);
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}
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if (cpu_mask & 0x2)
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{
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send_ipi_msg(1, ipi_vector);
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}
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if (cpu_mask & 0x4)
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{
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send_ipi_msg(2, ipi_vector);
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}
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if (cpu_mask & 0x8)
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{
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send_ipi_msg(3, ipi_vector);
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}
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__DSB();
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}
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#endif
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#ifdef RT_USING_SMP
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void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
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{
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/* note: ipi_vector maybe different with irq_vector */
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rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
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}
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#endif
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@ -1,18 +0,0 @@
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#ifndef __INTERRUPT_H__
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#define __INTERRUPT_H__
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#include <rthw.h>
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#include <board.h>
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#define INT_IRQ 0x00
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#define INT_FIQ 0x01
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void rt_hw_interrupt_init(void);
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void rt_hw_interrupt_mask(int vector);
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void rt_hw_interrupt_umask(int vector);
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, const char *name);
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#endif
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@ -1,188 +0,0 @@
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/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
|
||||
*
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||||
* Change Logs:
|
||||
* Date Author Notes
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||||
* 2012-01-10 bernard porting to AM1808
|
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* 2019-07-28 zdzn add smp support
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*/
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#include "mmu.h"
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/* dump 2nd level page table */
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void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
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{
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int i;
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int fcnt = 0;
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for (i = 0; i < 256; i++)
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{
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rt_uint32_t pte2 = ptb[i];
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if ((pte2 & 0x3) == 0)
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{
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if (fcnt == 0)
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rt_kprintf(" ");
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rt_kprintf("%04x: ", i);
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fcnt++;
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if (fcnt == 16)
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{
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rt_kprintf("fault\n");
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fcnt = 0;
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}
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continue;
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}
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if (fcnt != 0)
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{
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rt_kprintf("fault\n");
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fcnt = 0;
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}
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rt_kprintf(" %04x: %x: ", i, pte2);
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if ((pte2 & 0x3) == 0x1)
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{
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rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
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((pte2 >> 7) | (pte2 >> 4))& 0xf,
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(pte2 >> 15) & 0x1,
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((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
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}
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else
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{
|
||||
rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
|
||||
((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
|
||||
((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
|
||||
{
|
||||
int i;
|
||||
int fcnt = 0;
|
||||
|
||||
rt_kprintf("page table@%p\n", ptb);
|
||||
for (i = 0; i < 1024*4; i++)
|
||||
{
|
||||
rt_uint32_t pte1 = ptb[i];
|
||||
if ((pte1 & 0x3) == 0)
|
||||
{
|
||||
rt_kprintf("%03x: ", i);
|
||||
fcnt++;
|
||||
if (fcnt == 16)
|
||||
{
|
||||
rt_kprintf("fault\n");
|
||||
fcnt = 0;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
if (fcnt != 0)
|
||||
{
|
||||
rt_kprintf("fault\n");
|
||||
fcnt = 0;
|
||||
}
|
||||
|
||||
rt_kprintf("%03x: %08x: ", i, pte1);
|
||||
if ((pte1 & 0x3) == 0x3)
|
||||
{
|
||||
rt_kprintf("LPAE\n");
|
||||
}
|
||||
else if ((pte1 & 0x3) == 0x1)
|
||||
{
|
||||
rt_kprintf("pte,ns:%d,domain:%d\n",
|
||||
(pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
|
||||
/*
|
||||
*rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
|
||||
* - 0x80000000 + 0xC0000000));
|
||||
*/
|
||||
}
|
||||
else if (pte1 & (1 << 18))
|
||||
{
|
||||
rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
|
||||
(pte1 >> 19) & 0x1,
|
||||
((pte1 >> 13) | (pte1 >> 10))& 0xf,
|
||||
(pte1 >> 4) & 0x1,
|
||||
((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("section,ns:%d,ap:%x,"
|
||||
"xn:%d,texcb:%02x,domain:%d\n",
|
||||
(pte1 >> 19) & 0x1,
|
||||
((pte1 >> 13) | (pte1 >> 10))& 0xf,
|
||||
(pte1 >> 4) & 0x1,
|
||||
(((pte1 & (0x7 << 12)) >> 10) |
|
||||
((pte1 & 0x0c) >> 2)) & 0x1f,
|
||||
(pte1 >> 5) & 0xf);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* level1 page table, each entry for 1MB memory. */
|
||||
volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
|
||||
void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
|
||||
rt_uint32_t vaddrEnd,
|
||||
rt_uint32_t paddrStart,
|
||||
rt_uint32_t attr)
|
||||
{
|
||||
volatile rt_uint32_t *pTT;
|
||||
volatile int i, nSec;
|
||||
pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
|
||||
nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
|
||||
for (i = 0; i <= nSec; i++)
|
||||
{
|
||||
*pTT = attr | (((paddrStart >> 20) + i) << 20);
|
||||
pTT++;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned long rt_hw_set_domain_register(unsigned long domain_val)
|
||||
{
|
||||
unsigned long old_domain;
|
||||
|
||||
asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
|
||||
asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
|
||||
|
||||
return old_domain;
|
||||
}
|
||||
|
||||
void rt_hw_init_mmu_table()
|
||||
{
|
||||
/* set page table */
|
||||
/* 4G 1:1 memory */
|
||||
rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
|
||||
/* IO memory region */
|
||||
rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
|
||||
}
|
||||
|
||||
void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
|
||||
rt_uint32_t size,
|
||||
rt_uint32_t paddrStart, rt_uint32_t attr)
|
||||
{
|
||||
rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
|
||||
#ifndef RT_USING_SMP
|
||||
rt_cpu_dcache_clean_flush();
|
||||
rt_cpu_icache_flush();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void rt_hw_mmu_init(void)
|
||||
{
|
||||
rt_cpu_dcache_clean_flush();
|
||||
rt_cpu_icache_flush();
|
||||
rt_hw_cpu_dcache_disable();
|
||||
rt_hw_cpu_icache_disable();
|
||||
rt_cpu_mmu_disable();
|
||||
|
||||
/*rt_hw_cpu_dump_page_table(MMUTable);*/
|
||||
rt_hw_set_domain_register(0x55555555);
|
||||
|
||||
rt_cpu_tlb_set(MMUTable);
|
||||
|
||||
rt_cpu_mmu_enable();
|
||||
|
||||
rt_hw_cpu_icache_enable();
|
||||
rt_hw_cpu_dcache_enable();
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue