Add mb9bf568r to bsp

bsp/mb9bf568r/CMSIS/DeviceSupport/base_types.h

@@ -0,0 +1,160 @@
+/*******************************************************************************
+* Copyright (C) 2013 Spansion LLC. All Rights Reserved. 
+*
+* This software is owned and published by: 
+* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with Spansion 
+* components. This software is licensed by Spansion to be adapted only 
+* for use in systems utilizing Spansion components. Spansion shall not be 
+* responsible for misuse or illegal use of this software for devices not 
+* supported herein.  Spansion is providing this software "AS IS" and will 
+* not be responsible for issues arising from incorrect user implementation 
+* of the software.  
+*
+* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 
+* WARRANTY OF NONINFRINGEMENT.  
+* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 
+* SAVINGS OR PROFITS, 
+* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 
+* FROM, THE SOFTWARE.  
+*
+* This software may be replicated in part or whole for the licensed use, 
+* with the restriction that this Disclaimer and Copyright notice must be 
+* included with each copy of this software, whether used in part or whole, 
+* at all times.  
+*/
+
+/*****************************************************************************/
+/** \file base_types.h
+ **
+ ** Additional base type definitions to stddef.h and stdint.h
+ **
+ ** History:
+ **   - 2013-03-21  1.0  MWi  First version.
+ **
+ *****************************************************************************/
+
+#ifndef __BASE_TYPES_H__
+#define __BASE_TYPES_H__
+
+/*****************************************************************************/
+/* Include files                                                             */
+/*****************************************************************************/
+#include <stddef.h>
+#include "stdint.h"
+  
+/*****************************************************************************/
+/* Global pre-processor symbols/macros ('#define')                           */
+/*****************************************************************************/
+#ifndef TRUE
+  /** Value is true (boolean_t type) */
+  #define TRUE        ((boolean_t) 1)
+#endif
+
+#ifndef FALSE
+  /** Value is false (boolean_t type) */
+  #define FALSE       ((boolean_t) 0)
+#endif  
+
+/** Returns the minimum value out of two values */
+#define MIN( X, Y )  ((X) < (Y) ? (X) : (Y))
+
+/** Returns the maximum value out of two values */
+#define MAX( X, Y )  ((X) > (Y) ? (X) : (Y))
+
+/** Returns the dimension of an array */
+#define DIM( X )  (sizeof(X) / sizeof(X[0]))
+
+/******************************************************************************
+ * Global type definitions
+ ******************************************************************************/
+
+/** logical datatype (only values are TRUE and FALSE) */
+typedef uint8_t      boolean_t;
+  
+/** single precision floating point number (4 byte) */
+typedef float        float32_t;
+
+/** double precision floating point number (8 byte) */
+typedef double       float64_t;
+
+/** ASCCI character for string generation (8 bit) */
+typedef char         char_t;
+
+/** function pointer type to void/void function */
+typedef void         (*func_ptr_t)(void);
+
+/** function pointer type to void/uint8_t function */
+typedef void         (*func_ptr_arg1_t)(uint8_t);
+
+/** generic error codes */
+typedef enum en_result
+{
+    Ok                          = 0,  ///< No error
+    Error                       = 1,  ///< Non-specific error code
+    ErrorAddressAlignment       = 2,  ///< Address alignment does not match
+    ErrorAccessRights           = 3,  ///< Wrong mode (e.g. user/system) mode is set
+    ErrorInvalidParameter       = 4,  ///< Provided parameter is not valid
+    ErrorOperationInProgress    = 5,  ///< A conflicting or requested operation is still in progress
+    ErrorInvalidMode            = 6,  ///< Operation not allowed in current mode
+    ErrorUninitialized          = 7,  ///< Module (or part of it) was not initialized properly
+    ErrorBufferFull             = 8,  ///< Circular buffer can not be written because the buffer is full
+    ErrorTimeout                = 9,  ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.)
+    ErrorNotReady               = 10, ///< A requested final state is not reached
+    OperationInProgress         = 11  ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.)
+} en_result_t;
+
+/**
+ ******************************************************************************
+ ** \brief Level
+ ** 
+ ** Specifies levels.
+ **
+ ******************************************************************************/
+typedef enum en_level
+{
+    PDLLow      = 0,  ///< Low level '0'
+    PDLHigh     = 1   ///< High level '1'
+} en_level_t;
+
+/**
+ ******************************************************************************
+ ** \brief Generic Flag Code
+ ** 
+ ** Specifies flags.
+ **
+ ******************************************************************************/
+typedef enum en_flag
+{
+    PdlClr = 0,       ///< Flag clr '0'
+    PdlSet = 1        ///< Flag set '1' 
+} en_stat_flag_t, en_int_flag_t;      
+
+/*****************************************************************************/
+/* Global variable declarations ('extern', definition in C source)           */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* Global function prototypes ('extern', definition in C source)             */
+/*****************************************************************************/
+
+#endif /* __BASE_TYPES_H__ */
+
+/******************************************************************************/
+/* EOF (not truncated)                                                        */
+/******************************************************************************/

bsp/mb9bf568r/CMSIS/DeviceSupport/startup_mb9bf56xr.s

@@ -0,0 +1,584 @@
+;*******************************************************************************
+; Copyright (C) 2013 Spansion LLC. All Rights Reserved. 
+;
+; This software is owned and published by: 
+; Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
+;
+; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
+; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+;
+; This software contains source code for use with Spansion 
+; components. This software is licensed by Spansion to be adapted only 
+; for use in systems utilizing Spansion components. Spansion shall not be 
+; responsible for misuse or illegal use of this software for devices not 
+; supported herein.  Spansion is providing this software "AS IS" and will 
+; not be responsible for issues arising from incorrect user implementation 
+; of the software.  
+;
+; SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+; REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 
+; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 
+; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 
+; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 
+; WARRANTY OF NONINFRINGEMENT.  
+; SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 
+; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 
+; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 
+; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 
+; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 
+; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 
+; SAVINGS OR PROFITS, 
+; EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
+; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 
+; FROM, THE SOFTWARE.  
+;
+; This software may be replicated in part or whole for the licensed use, 
+; with the restriction that this Disclaimer and Copyright notice must be 
+; included with each copy of this software, whether used in part or whole, 
+; at all times.  
+;
+
+; Stack Configuration
+;  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+;  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+; Numbered IRQ handler vectors				
+				
+; Note: renaming to device dependent ISR function names are done in
+;       pdl.h (section "IRQ name definition for all type MCUs"
+
+                DCD     CSV_IRQHandler
+                DCD     SWDT_IRQHandler
+                DCD     LVD_IRQHandler
+                DCD     IRQ003SEL_IRQHandler
+                DCD     IRQ004SEL_IRQHandler
+                DCD     IRQ005SEL_IRQHandler
+                DCD     IRQ006SEL_IRQHandler
+                DCD     IRQ007SEL_IRQHandler
+                DCD     IRQ008SEL_IRQHandler
+                DCD     IRQ009SEL_IRQHandler
+                DCD     IRQ010SEL_IRQHandler
+                DCD     EXINT0_IRQHandler
+                DCD     EXINT1_IRQHandler
+                DCD     EXINT2_IRQHandler
+                DCD     EXINT3_IRQHandler
+                DCD     EXINT4_IRQHandler
+                DCD     EXINT5_IRQHandler
+                DCD     EXINT6_IRQHandler
+                DCD     EXINT7_IRQHandler
+                DCD     QPRC0_IRQHandler
+                DCD     QPRC1_IRQHandler
+                DCD     WFG0_DTIF0_IRQHandler
+                DCD     WFG1_DTIF1_IRQHandler
+                DCD     WFG2_DTIF2_IRQHandler
+                DCD     FRT0_PEAK_IRQHandler
+                DCD     FRT0_ZERO_IRQHandler
+                DCD     ICU0_IRQHandler
+                DCD     OCU0_IRQHandler
+                DCD     FRT1_PEAK_IRQHandler
+                DCD     FRT1_ZERO_IRQHandler
+                DCD     ICU1_IRQHandler
+                DCD     OCU1_IRQHandler
+                DCD     FRT2_PEAK_IRQHandler
+                DCD     FRT2_ZERO_IRQHandler
+                DCD     ICU2_IRQHandler
+                DCD     OCU2_IRQHandler
+                DCD     PPG00_02_04_IRQHandler
+                DCD     PPG08_10_12_IRQHandler
+                DCD     PPG16_18_20_IRQHandler
+                DCD     BT0_IRQHandler
+                DCD     BT1_IRQHandler
+                DCD     BT2_IRQHandler
+                DCD     BT3_IRQHandler
+                DCD     BT4_IRQHandler
+                DCD     BT5_IRQHandler
+                DCD     BT6_IRQHandler
+                DCD     BT7_IRQHandler
+                DCD     DT1_2_IRAHandler
+                DCD     WC_IRQHandler
+                DCD     EXTBUS_ERR_Handler
+                DCD     RTC_IRQHandler
+                DCD     EXTINT8_IRQHandler
+                DCD     EXTINT9_IRQHandler
+                DCD     EXTINT10_IRQHandler
+                DCD     EXTINT11_IRQHandler
+                DCD     EXTINT12_IRQHandler
+                DCD     EXTINT13_IRQHandler
+                DCD     EXTINT14_IRQHandler
+                DCD     EXTINT15_IRQHandler
+                DCD     TIM_IRQHandler
+                DCD     MFS0_RX_IRQHandler
+                DCD     MFS0_TX_IRQHandler
+                DCD     MFS1_RX_IRQHandler
+                DCD     MFS1_TX_IRQHandler
+                DCD     MFS2_RX_IRQHandler
+                DCD     MFS2_TX_IRQHandler
+                DCD     MFS3_RX_IRQHandler
+                DCD     MFS3_TX_IRQHandler
+                DCD     MFS4_RX_IRQHandler
+                DCD     MFS4_TX_IRQHandler
+                DCD     MFS5_RX_IRQHandler
+                DCD     MFS5_TX_IRQHandler
+                DCD     MFS6_RX_IRQHandler
+                DCD     MFS6_TX_IRQHandler
+                DCD     MFS7_RX_IRQHandler
+                DCD     MFS7_TX_IRQHandler
+                DCD     ADC0_IRQHandler
+                DCD     ADC1_IRQHandler
+                DCD     USB0_IRQHandler
+                DCD     USB0_HOST_IRQHandler
+                DCD     CAN0_IRQHandler
+                DCD     CAN1_IRQHandler
+                DCD     ETHER0_IRQHandler
+                DCD     DMAC0_IRQHandler
+                DCD     DMAC1_IRQHandler
+                DCD     DMAC2_IRQHandler
+                DCD     DMAC3_IRQHandler
+                DCD     DMAC4_IRQHandler
+                DCD     DMAC5_IRQHandler
+                DCD     DMAC6_IRQHandler
+                DCD     DMAC7_IRQHandler
+                DCD     DSTC_IRQHandler
+                DCD     EXINT16_17_18_19_IRQHandler
+                DCD     EXINT20_21_22_23_IRQHandler
+                DCD     EXINT24_25_26_27_IRQHandler
+                DCD     EXINT28_29_30_31_IRQHandler
+                DCD     QPRC2_IRQHandler
+                DCD     QPRC3_IRQHandler
+                DCD     BT8_IRQHandler
+                DCD     BT9_IRQHandler
+                DCD     BT10_IRQHandler
+                DCD     BT11_IRQHandler
+                DCD     BT12_15_IRQHandler
+                DCD     MFS8_RX_IRQHandler
+                DCD     MFS8_TX_IRQHandler
+                DCD     MFS9_RX_IRQHandler
+                DCD     MFS9_TX_IRQHandler
+                DCD     MFS10_RX_IRQHandler
+                DCD     MFS10_TX_IRQHandler
+                DCD     MFS11_RX_IRQHandler
+                DCD     MFS11_TX_IRQHandler
+                DCD     ADC2_IRQHandler
+                DCD     Dummy
+                DCD     USB1_IRQHandler
+                DCD     USB1_HOST_IRQHandler
+                DCD     Dummy
+                DCD     Dummy
+                DCD     Dummy
+                DCD     SD_IRQHandler
+                DCD     FLASHIF_IRQHandler
+                DCD     MFS12_RX_IRQHandler
+                DCD     MFS12_TX_IRQHandler
+                DCD     MFS13_RX_IRQHandler
+                DCD     MFS13_TX_IRQHandler
+                DCD     MFS14_RX_IRQHandler
+                DCD     MFS14_TX_IRQHandler
+                DCD     MFS15_RX_IRQHandler
+                DCD     MFS15_TX_IRQHandler
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+
+                LDR.W R0, =0xE000ED88            ; CPACR is located at address 0xE000ED88
+                LDR R1, [R0]                     ; Read CPACR
+                ORR R1, R1, #(0xF << 20)         ; Set bits 20-23 to enable CP10 and CP11 coprocessors
+                STR R1, [R0]                     ; Write back the modified value to the CPACR
+
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  CSV_IRQHandler	          [WEAK]
+                EXPORT  SWDT_IRQHandler	          [WEAK]
+                EXPORT  LVD_IRQHandler	          [WEAK]
+                EXPORT  IRQ003SEL_IRQHandler	          [WEAK]
+                EXPORT  IRQ004SEL_IRQHandler	          [WEAK]
+                EXPORT  IRQ005SEL_IRQHandler	          [WEAK]
+                EXPORT  IRQ006SEL_IRQHandler	          [WEAK]
+                EXPORT  IRQ007SEL_IRQHandler	          [WEAK]
+                EXPORT  IRQ008SEL_IRQHandler	          [WEAK]
+                EXPORT  IRQ009SEL_IRQHandler	          [WEAK]
+                EXPORT  IRQ010SEL_IRQHandler	          [WEAK]
+                EXPORT  EXINT0_IRQHandler	          [WEAK]
+                EXPORT  EXINT1_IRQHandler	          [WEAK]
+                EXPORT  EXINT2_IRQHandler	          [WEAK]
+                EXPORT  EXINT3_IRQHandler	          [WEAK]
+                EXPORT  EXINT4_IRQHandler	          [WEAK]
+                EXPORT  EXINT5_IRQHandler	          [WEAK]
+                EXPORT  EXINT6_IRQHandler	          [WEAK]
+                EXPORT  EXINT7_IRQHandler	          [WEAK]
+                EXPORT  QPRC0_IRQHandler	          [WEAK]
+                EXPORT  QPRC1_IRQHandler	          [WEAK]
+                EXPORT  WFG0_DTIF0_IRQHandler	          [WEAK]
+                EXPORT  WFG1_DTIF1_IRQHandler	          [WEAK]
+                EXPORT  WFG2_DTIF2_IRQHandler	          [WEAK]
+                EXPORT  FRT0_PEAK_IRQHandler	          [WEAK]
+                EXPORT  FRT0_ZERO_IRQHandler	          [WEAK]
+                EXPORT  ICU0_IRQHandler	          [WEAK]
+                EXPORT  OCU0_IRQHandler	          [WEAK]
+                EXPORT  FRT1_PEAK_IRQHandler	          [WEAK]
+                EXPORT  FRT1_ZERO_IRQHandler	          [WEAK]
+                EXPORT  ICU1_IRQHandler	          [WEAK]
+                EXPORT  OCU1_IRQHandler	          [WEAK]
+                EXPORT  FRT2_PEAK_IRQHandler	          [WEAK]
+                EXPORT  FRT2_ZERO_IRQHandler	          [WEAK]
+                EXPORT  ICU2_IRQHandler	          [WEAK]
+                EXPORT  OCU2_IRQHandler	          [WEAK]
+                EXPORT  PPG00_02_04_IRQHandler	          [WEAK]
+                EXPORT  PPG08_10_12_IRQHandler	          [WEAK]
+                EXPORT  PPG16_18_20_IRQHandler	          [WEAK]
+                EXPORT  BT0_IRQHandler	          [WEAK]
+                EXPORT  BT1_IRQHandler	          [WEAK]
+                EXPORT  BT2_IRQHandler	          [WEAK]
+                EXPORT  BT3_IRQHandler	          [WEAK]
+                EXPORT  BT4_IRQHandler	          [WEAK]
+                EXPORT  BT5_IRQHandler	          [WEAK]
+                EXPORT  BT6_IRQHandler	          [WEAK]
+                EXPORT  BT7_IRQHandler	          [WEAK]
+                EXPORT  DT1_2_IRAHandler	          [WEAK]
+                EXPORT  WC_IRQHandler	          [WEAK]
+                EXPORT  EXTBUS_ERR_Handler	          [WEAK]
+                EXPORT  RTC_IRQHandler	          [WEAK]
+                EXPORT  EXTINT8_IRQHandler	          [WEAK]
+                EXPORT  EXTINT9_IRQHandler	          [WEAK]
+                EXPORT  EXTINT10_IRQHandler	          [WEAK]
+                EXPORT  EXTINT11_IRQHandler	          [WEAK]
+                EXPORT  EXTINT12_IRQHandler	          [WEAK]
+                EXPORT  EXTINT13_IRQHandler	          [WEAK]
+                EXPORT  EXTINT14_IRQHandler	          [WEAK]
+                EXPORT  EXTINT15_IRQHandler	          [WEAK]
+                EXPORT  TIM_IRQHandler	          [WEAK]
+                EXPORT  MFS0_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS0_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS1_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS1_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS2_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS2_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS3_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS3_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS4_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS4_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS5_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS5_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS6_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS6_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS7_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS7_TX_IRQHandler	          [WEAK]
+                EXPORT  ADC0_IRQHandler	          [WEAK]
+                EXPORT  ADC1_IRQHandler	          [WEAK]
+                EXPORT  USB0_IRQHandler	          [WEAK]
+                EXPORT  USB0_HOST_IRQHandler	          [WEAK]
+                EXPORT  CAN0_IRQHandler	          [WEAK]
+                EXPORT  CAN1_IRQHandler	          [WEAK]
+                EXPORT  ETHER0_IRQHandler	          [WEAK]
+                EXPORT  DMAC0_IRQHandler	          [WEAK]
+                EXPORT  DMAC1_IRQHandler	          [WEAK]
+                EXPORT  DMAC2_IRQHandler	          [WEAK]
+                EXPORT  DMAC3_IRQHandler	          [WEAK]
+                EXPORT  DMAC4_IRQHandler	          [WEAK]
+                EXPORT  DMAC5_IRQHandler	          [WEAK]
+                EXPORT  DMAC6_IRQHandler	          [WEAK]
+                EXPORT  DMAC7_IRQHandler	          [WEAK]
+                EXPORT  DSTC_IRQHandler	          [WEAK]
+                EXPORT  EXINT16_17_18_19_IRQHandler	          [WEAK]
+                EXPORT  EXINT20_21_22_23_IRQHandler	          [WEAK]
+                EXPORT  EXINT24_25_26_27_IRQHandler	          [WEAK]
+                EXPORT  EXINT28_29_30_31_IRQHandler	          [WEAK]
+                EXPORT  QPRC2_IRQHandler	          [WEAK]
+                EXPORT  QPRC3_IRQHandler	          [WEAK]
+                EXPORT  BT8_IRQHandler	          [WEAK]
+                EXPORT  BT9_IRQHandler	          [WEAK]
+                EXPORT  BT10_IRQHandler	          [WEAK]
+                EXPORT  BT11_IRQHandler	          [WEAK]
+                EXPORT  BT12_15_IRQHandler	          [WEAK]
+                EXPORT  MFS8_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS8_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS9_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS9_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS10_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS10_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS11_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS11_TX_IRQHandler	          [WEAK]
+                EXPORT  ADC2_IRQHandler	          [WEAK]
+                EXPORT  USB1_IRQHandler	          [WEAK]
+                EXPORT  USB1_HOST_IRQHandler	          [WEAK]
+                EXPORT  SD_IRQHandler	          [WEAK]
+                EXPORT  FLASHIF_IRQHandler	          [WEAK]
+                EXPORT  MFS12_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS12_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS13_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS13_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS14_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS14_TX_IRQHandler	          [WEAK]
+                EXPORT  MFS15_RX_IRQHandler	          [WEAK]
+                EXPORT  MFS15_TX_IRQHandler	          [WEAK]
+                EXPORT  Dummy	          [WEAK]
+
+
+
+CSV_IRQHandler
+SWDT_IRQHandler
+LVD_IRQHandler
+IRQ003SEL_IRQHandler
+IRQ004SEL_IRQHandler
+IRQ005SEL_IRQHandler
+IRQ006SEL_IRQHandler
+IRQ007SEL_IRQHandler
+IRQ008SEL_IRQHandler
+IRQ009SEL_IRQHandler
+IRQ010SEL_IRQHandler
+EXINT0_IRQHandler
+EXINT1_IRQHandler
+EXINT2_IRQHandler
+EXINT3_IRQHandler
+EXINT4_IRQHandler
+EXINT5_IRQHandler
+EXINT6_IRQHandler
+EXINT7_IRQHandler
+QPRC0_IRQHandler
+QPRC1_IRQHandler
+WFG0_DTIF0_IRQHandler
+WFG1_DTIF1_IRQHandler
+WFG2_DTIF2_IRQHandler
+FRT0_PEAK_IRQHandler
+FRT0_ZERO_IRQHandler
+ICU0_IRQHandler
+OCU0_IRQHandler
+FRT1_PEAK_IRQHandler
+FRT1_ZERO_IRQHandler
+ICU1_IRQHandler
+OCU1_IRQHandler
+FRT2_PEAK_IRQHandler
+FRT2_ZERO_IRQHandler
+ICU2_IRQHandler
+OCU2_IRQHandler
+PPG00_02_04_IRQHandler
+PPG08_10_12_IRQHandler
+PPG16_18_20_IRQHandler
+BT0_IRQHandler
+BT1_IRQHandler
+BT2_IRQHandler
+BT3_IRQHandler
+BT4_IRQHandler
+BT5_IRQHandler
+BT6_IRQHandler
+BT7_IRQHandler
+DT1_2_IRAHandler
+WC_IRQHandler
+EXTBUS_ERR_Handler
+RTC_IRQHandler
+EXTINT8_IRQHandler
+EXTINT9_IRQHandler
+EXTINT10_IRQHandler
+EXTINT11_IRQHandler
+EXTINT12_IRQHandler
+EXTINT13_IRQHandler
+EXTINT14_IRQHandler
+EXTINT15_IRQHandler
+TIM_IRQHandler
+MFS0_RX_IRQHandler
+MFS0_TX_IRQHandler
+MFS1_RX_IRQHandler
+MFS1_TX_IRQHandler
+MFS2_RX_IRQHandler
+MFS2_TX_IRQHandler
+MFS3_RX_IRQHandler
+MFS3_TX_IRQHandler
+MFS4_RX_IRQHandler
+MFS4_TX_IRQHandler
+MFS5_RX_IRQHandler
+MFS5_TX_IRQHandler
+MFS6_RX_IRQHandler
+MFS6_TX_IRQHandler
+MFS7_RX_IRQHandler
+MFS7_TX_IRQHandler
+ADC0_IRQHandler
+ADC1_IRQHandler
+USB0_IRQHandler
+USB0_HOST_IRQHandler
+CAN0_IRQHandler
+CAN1_IRQHandler
+ETHER0_IRQHandler
+DMAC0_IRQHandler
+DMAC1_IRQHandler
+DMAC2_IRQHandler
+DMAC3_IRQHandler
+DMAC4_IRQHandler
+DMAC5_IRQHandler
+DMAC6_IRQHandler
+DMAC7_IRQHandler
+DSTC_IRQHandler
+EXINT16_17_18_19_IRQHandler
+EXINT20_21_22_23_IRQHandler
+EXINT24_25_26_27_IRQHandler
+EXINT28_29_30_31_IRQHandler
+QPRC2_IRQHandler
+QPRC3_IRQHandler
+BT8_IRQHandler
+BT9_IRQHandler
+BT10_IRQHandler
+BT11_IRQHandler
+BT12_15_IRQHandler
+MFS8_RX_IRQHandler
+MFS8_TX_IRQHandler
+MFS9_RX_IRQHandler
+MFS9_TX_IRQHandler
+MFS10_RX_IRQHandler
+MFS10_TX_IRQHandler
+MFS11_RX_IRQHandler
+MFS11_TX_IRQHandler
+ADC2_IRQHandler
+USB1_IRQHandler
+USB1_HOST_IRQHandler
+SD_IRQHandler
+FLASHIF_IRQHandler
+MFS12_RX_IRQHandler
+MFS12_TX_IRQHandler
+MFS13_RX_IRQHandler
+MFS13_TX_IRQHandler
+MFS14_RX_IRQHandler
+MFS14_TX_IRQHandler
+MFS15_RX_IRQHandler
+MFS15_TX_IRQHandler
+Dummy
+
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, = Heap_Mem
+                LDR     R1, = (Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem + Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

bsp/mb9bf568r/CMSIS/DeviceSupport/system_mb9abxxx.c

@@ -0,0 +1,240 @@
+/*******************************************************************************
+* Copyright (C) 2013 Spansion LLC. All Rights Reserved. 
+*
+* This software is owned and published by: 
+* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with Spansion 
+* components. This software is licensed by Spansion to be adapted only 
+* for use in systems utilizing Spansion components. Spansion shall not be 
+* responsible for misuse or illegal use of this software for devices not 
+* supported herein.  Spansion is providing this software "AS IS" and will 
+* not be responsible for issues arising from incorrect user implementation 
+* of the software.  
+*
+* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 
+* WARRANTY OF NONINFRINGEMENT.  
+* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 
+* SAVINGS OR PROFITS, 
+* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 
+* FROM, THE SOFTWARE.  
+*
+* This software may be replicated in part or whole for the licensed use, 
+* with the restriction that this Disclaimer and Copyright notice must be 
+* included with each copy of this software, whether used in part or whole, 
+* at all times.  
+*/
+/**
+ ******************************************************************************
+ ** \file system_mb9abxxx.c
+ **
+ ** FM3 system initialization functions
+ ** All adjustments can be done in belonging header file.
+ **
+ ** History:
+ ** 2013-01-21  0.1  MWi  AI: Unification to be done
+ ** 2013-01-23  0.2  MWi  mcu.h inclusion changed to pdl.h
+ ** 2013-06-28  0.3  EH   Added Trace Buffer enable
+ ******************************************************************************/
+
+#include "mcu.h"
+
+/**
+ ******************************************************************************
+ ** System Clock Frequency (Core Clock) Variable according CMSIS
+ ******************************************************************************/
+uint32_t SystemCoreClock = __HCLK;
+
+/**
+ ******************************************************************************
+ ** \brief  Update the System Core Clock with current core Clock retrieved from
+ ** cpu registers.
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemCoreClockUpdate (void) {
+  uint32_t masterClk;
+  uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
+
+  switch ((FM4_CRG->SCM_CTL >> 5U) & 0x07U) {
+    case 0u:                                 /* internal High-speed Cr osc.    */
+      masterClk = __CLKHC;
+      break;
+
+    case 1u:                                 /* external main osc.             */
+      masterClk = __CLKMO;
+      break;
+
+    case 2u:                                 /* PLL clock                      */
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violation:
+  //   "Unordered accesses to a volatile location"
+      u32RegisterRead = (__CLKMO  * (((uint32_t)(FM4_CRG->PLL_CTL2) & 0x3Fu) + 1u));
+      masterClk = (u32RegisterRead / ((((uint32_t)(FM4_CRG->PLL_CTL1) >> 4ul) & 0x0Fu) + 1u));
+      break;
+
+    case 4u:                                 /* internal Low-speed CR osc.     */
+      masterClk = __CLKLC;
+      break;
+
+    case 5u:                                 /* external Sub osc.              */
+      masterClk = __CLKSO;
+      break;
+
+    default:
+      masterClk = 0ul;
+      break;
+  }
+
+  switch (FM4_CRG->BSC_PSR & 0x07u) {
+    case 0u:
+      SystemCoreClock = masterClk;
+      break;
+
+    case 1u:
+      SystemCoreClock = masterClk / 2u;
+      break;
+
+    case 2u:
+      SystemCoreClock = masterClk / 3u;
+      break;
+
+    case 3u:
+      SystemCoreClock = masterClk / 4u;
+      break;
+
+    case 4u:
+      SystemCoreClock = masterClk / 6u;
+      break;
+
+    case 5u:
+      SystemCoreClock = masterClk /8u;
+      break;
+
+    case 6u:
+      SystemCoreClock = masterClk /16u;
+      break;
+
+    default:
+      SystemCoreClock = 0ul;
+      break;
+  }
+
+}
+
+/**
+ ******************************************************************************
+ ** \brief  Setup the microcontroller system. Initialize the System and update
+ ** the SystemCoreClock variable.
+ **
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemInit (void) {
+
+  static uint8_t u8IoRegisterRead;  // Workaround variable for MISRA C rule conformance
+  
+#if (HWWD_DISABLE)                                 /* HW Watchdog Disable */
+  FM4_HWWDT->WDG_LCK = 0x1ACCE551u;                /* HW Watchdog Unlock */
+  FM4_HWWDT->WDG_LCK = 0xE5331AAEu;
+  FM4_HWWDT->WDG_CTL = 0u;                         /* HW Watchdog stop */
+#endif
+
+#if (TRACE_BUFFER_ENABLE)
+  FM4_FLASH_IF->FBFCR = 0x01;                      /* Trace Buffer enable */
+#endif
+
+#if (CLOCK_SETUP)                                  /* Clock Setup */
+  FM4_CRG->BSC_PSR   = (uint8_t)BSC_PSR_Val;                 /* set System Clock presacaler */
+  FM4_CRG->APBC0_PSR = (uint8_t)APBC0_PSR_Val;               /* set APB0 presacaler */
+  FM4_CRG->APBC1_PSR = (uint8_t)APBC1_PSR_Val;               /* set APB1 presacaler */
+  FM4_CRG->APBC2_PSR = (uint8_t)APBC2_PSR_Val;               /* set APB2 presacaler */
+  FM4_CRG->SWC_PSR   = (uint8_t)(SWC_PSR_Val | (1ul << 7u)); /* set SW Watchdog presacaler */
+  FM4_CRG->TTC_PSR   = (uint8_t)TTC_PSR_Val;                 /* set Trace Clock presacaler */
+
+  FM4_CRG->CSW_TMR   = (uint8_t)CSW_TMR_Val;                 /* set oscillation stabilization wait time */
+  
+  if (SCM_CTL_Val & (1ul << 1u)) {                 /* Main clock oscillator enabled ? */
+    FM4_CRG->SCM_CTL |= (uint8_t)(1ul << 1u);            /* enable main oscillator */ 
+    
+    while (!((FM4_CRG->SCM_STR) & (uint8_t)(1ul << 1u))) /* wait for Main clock oscillation stable */ 
+    {}
+  }
+  
+  if (SCM_CTL_Val & (1UL << 3)) {                    /* Sub clock oscillator enabled ? */
+    // Initialize VBAT (Temporary process)
+    FM4_RTC->VDET = 0x00;
+    FM4_RTC->VBPFR = 0x1C;
+    FM4_RTC->CCB = 0x10;
+    FM4_RTC->CCS = 0x08;
+
+    // VB_CLK is less or equal to 1MHz (Temporary process)
+    FM4_RTC->VB_CLKDIV = 0x4E;
+    FM4_RTC->BOOST = 0x03;
+
+    // Enable SUB CLK oscilation (Temporary process)
+    FM4_RTC->WTOSCCNT_f.SOSCEX  = 0;
+    FM4_RTC->WTOSCCNT_f.SOSCNTL = 1;
+
+    // Transmit to VBAT domain (Temporary process)
+    FM4_RTC->WTCR20_f.PWRITE = 1;
+
+    // Wait to complete transmission
+    while(0 != FM4_RTC->WTCR10_f.TRANS)
+
+    FM4_CRG->SCM_CTL |= (1UL << 3);                /* enable sub oscillator */ 
+    while (!(FM4_CRG->SCM_STR & (1UL << 3)));      /* wait for Sub clock oscillation stable */
+  }
+
+  FM4_CRG->PSW_TMR   =  (uint8_t)PSW_TMR_Val;                /* set PLL stabilization wait time */
+  FM4_CRG->PLL_CTL1  = (uint8_t) PLL_CTL1_Val;               /* set PLLM and PLLK */
+  FM4_CRG->PLL_CTL2  =  (uint8_t)PLL_CTL2_Val;               /* set PLLN          */
+  
+  if (SCM_CTL_Val &  (uint8_t)(1ul << 4u)) {                    /* PLL enabled ? */
+    FM4_CRG->SCM_CTL  |=  (uint8_t)(1ul << 4u);               /* enable PLL */ 
+    while (!(FM4_CRG->SCM_STR &  (uint8_t)(1ul << 4u)))      /* wait for PLL stable */
+    {}
+  }
+
+  FM4_CRG->SCM_CTL  |=  (uint8_t)(SCM_CTL_Val & 0xE0u);       /* Set Master Clock switch */ 
+  
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violations:
+  //   "Unordered reads and writes to or from same location" and
+  //   "Unordered accesses to a volatile location"
+  do                                              
+  {                                               
+    u8IoRegisterRead = (FM4_CRG->SCM_CTL & 0xE0u); 
+  }while ((FM4_CRG->SCM_STR & 0xE0u) != u8IoRegisterRead);
+#endif // (CLOCK_SETUP)
+  
+#if (CR_TRIM_SETUP)
+  /* CR Trimming Data  */
+  if( 0x000003FFu != (FM4_FLASH_IF->CRTRMM & 0x000003FFu) )
+  {
+    /* UnLock (MCR_FTRM) */
+    FM4_CRTRIM->MCR_RLR =  (uint32_t)0x1ACCE554u;
+    /* Set MCR_FTRM */
+    FM4_CRTRIM->MCR_FTRM = (uint16_t)FM4_FLASH_IF->CRTRMM;
+    /* Lock (MCR_FTRM) */
+    FM4_CRTRIM->MCR_RLR =  (uint32_t)0x00000000u;
+  }
+#endif // (CR_TRIM_SETUP)
+}
+
+
+

bsp/mb9bf568r/CMSIS/DeviceSupport/system_mb9bf56xr.h

@@ -0,0 +1,674 @@
+/*******************************************************************************
+* Copyright (C) 2013 Spansion LLC. All Rights Reserved. 
+*
+* This software is owned and published by: 
+* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with Spansion 
+* components. This software is licensed by Spansion to be adapted only 
+* for use in systems utilizing Spansion components. Spansion shall not be 
+* responsible for misuse or illegal use of this software for devices not 
+* supported herein.  Spansion is providing this software "AS IS" and will 
+* not be responsible for issues arising from incorrect user implementation 
+* of the software.  
+*
+* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 
+* WARRANTY OF NONINFRINGEMENT.  
+* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 
+* SAVINGS OR PROFITS, 
+* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 
+* FROM, THE SOFTWARE.  
+*
+* This software may be replicated in part or whole for the licensed use, 
+* with the restriction that this Disclaimer and Copyright notice must be 
+* included with each copy of this software, whether used in part or whole, 
+* at all times.  
+*/
+
+/******************************************************************************/
+/** \file system_mb9bf56xr.h
+ **
+ ** Headerfile for FM4 system parameters
+ **
+ ** History: 
+ ** 2013-01-21  0.1  MWi  AI: Unification to be done
+ ** 2013-02-06  0.2  MWi  CMSIS coding restored; unifying still to be done
+ ** 2013-06-28  0.3  EH   Added Trace Buffer enable definition
+ ** 2013-08-15  0.4  EH   Changed APB1 Prescaler value
+ ******************************************************************************/
+
+#ifndef _SYSTEM_MB9ABXXX_H_
+#define _SYSTEM_MB9ABXXX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/******************************************************************************/
+/* Include files                                                              */
+/******************************************************************************/
+#include <stdint.h>
+
+/******************************************************************************/
+/* Global pre-processor symbols/macros ('define')                             */
+/******************************************************************************/
+   
+/******************************************************************************/
+/*                                                                            */
+/*                      START OF USER SETTINGS HERE                           */
+/*                      ===========================                           */   
+/*                                                                            */
+/*                 All lines with '<<<' can be set by user.                   */
+/*                                                                            */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Clock Setup Enable
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = No clock setup done by system_mb9xfxxx.c
+ ** - 1 = Clock setup done by system_mb9xfxxx.c
+ ******************************************************************************/ 
+#define CLOCK_SETUP               1   // <<< Define clock setup here
+
+/**
+ ******************************************************************************
+ ** \brief External Main Clock Frequency (in Hz, [value]ul)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/    
+#define __CLKMO        ( 4000000ul)   // <<< External   4MHz Crystal
+
+/**
+ ******************************************************************************
+ ** \brief External Sub Clock Frequency (in Hz, [value]ul)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/  
+#define __CLKSO        (   32768ul)   // <<<  External  32KHz Crystal
+
+/**
+ ******************************************************************************
+ ** \brief System Clock Mode Control Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** SCM_CTL
+ **
+ ** Bit#7-5 : RCS[2:0]
+ ** - 0 = Internal high-speed CR oscillation (default)
+ ** - 1 = Main oscillation clock
+ ** - 2 = PLL oscillation clock
+ ** - 3 = (not allowed)
+ ** - 4 = Internal low-speed CR oscillation
+ ** - 5 = Sub clock oscillation
+ ** - 6 = (not allowed)
+ ** - 7 = (not allowed)
+ **
+ ** Bit#4 : PLLE
+ ** - 0 = Disable PLL (default)
+ ** - 1 = Enable PLL
+ **
+ ** Bit#3 : SOSCE
+ ** - 0 = Disable sub oscillation (default)
+ ** - 1 = Enable sub oscillation
+ **
+ ** Bit#2 : (reserved)
+ **
+ ** Bit#1 : MOSCE
+ ** - 0 = Disable main oscillation (default)
+ ** - 1 = Enable main oscillation  
+ **
+ ** Bit#0 : (reserved)  
+ ******************************************************************************/ 
+#define SCM_CTL_Val           0x00000052ul    // <<< Define SCM_CTL here
+
+/**
+ ******************************************************************************
+ ** \brief Base Clock Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ **
+ ** BSC_PSR
+ **
+ ** Bit#7-3 : (reserved)
+ **
+ ** Bit#2-0 : BSR[2:0]
+ ** - 0 = HCLK = Master Clock
+ ** - 1 = HCLK = Master Clock / 2
+ ** - 2 = HCLK = Master Clock / 3
+ ** - 3 = HCLK = Master Clock / 4
+ ** - 4 = HCLK = Master Clock / 6
+ ** - 5 = HCLK = Master Clock / 8
+ ** - 6 = HCLK = Master Clock / 16
+ ** - 7 = (reserved)
+ ******************************************************************************/    
+#define BSC_PSR_Val           0x00000000ul    // <<< Define BSC_PSR here
+ 
+/**
+ ******************************************************************************
+ ** \brief APB0 Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** APBC0_PSR
+ **
+ ** Bit#7-2 : (reserved)
+ **
+ ** Bit#1-0 : BSR[2:0] 
+ ** - 0 = PCLK0 = HCLK
+ ** - 1 = PCLK0 = HCLK / 2
+ ** - 2 = PCLK0 = HCLK / 4
+ ** - 3 = PCLK0 = HCLK / 8
+ ******************************************************************************/    
+#define APBC0_PSR_Val         0x00000001UL     // <<< Define APBC0_PSR here
+   
+/**
+ ******************************************************************************
+ ** \brief APB1 Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** APBC1_PSR
+ **
+ ** Bit#7 : APBC1EN
+ ** - 0 = Disable PCLK1 output
+ ** - 1 = Enables PCLK1 (default)
+ **
+ ** Bit#6-5 : (reserved)
+ **
+ ** Bit#4 : APBC1RST
+ ** - 0 = APB1 bus reset, inactive (default)
+ ** - 1 = APB1 bus reset, active  
+ **
+ ** Bit#3-2 : (reserved)
+ **
+ ** Bit#1-0 : APBC1[2:0]
+ ** - 0 = PCLK1 = HCLK
+ ** - 1 = PCLK1 = HCLK / 2
+ ** - 2 = PCLK1 = HCLK / 4
+ ** - 3 = PCLK1 = HCLK / 8
+ ******************************************************************************/     
+#define APBC1_PSR_Val         0x00000080ul    // <<< Define APBC1_PSR here
+   
+/**
+ ******************************************************************************
+ ** \brief APB2 Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** APBC2_PSR
+ **
+ ** Bit#7 : APBC2EN
+ ** - 0 = Disable PCLK2 output
+ ** - 1 = Enables PCLK2 (default)
+ **
+ ** Bit#6-5 : (reserved)
+ ** 
+ ** Bit#4 : APBC2RST
+ ** - 0 = APB2 bus reset, inactive (default)
+ ** - 1 = APB2 bus reset, active  
+ **
+ ** Bit#3-2 : (reserved)
+ **
+ ** Bit#1-0 : APBC2[1:0]
+ ** - 0 = PCLK2 = HCLK
+ ** - 1 = PCLK2 = HCLK / 2
+ ** - 2 = PCLK2 = HCLK / 4
+ ** - 3 = PCLK2 = HCLK / 8
+ ******************************************************************************/    
+#define APBC2_PSR_Val         0x00000081ul    // <<< Define APBC2_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief Software Watchdog Clock Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** SWC_PSR
+ **
+ ** Bit#7 : TESTB
+ ** - 0 = (not allowed)
+ ** - 1 = (always write "1" to this bit)
+ **
+ ** Bit#6-2 : (reserved)
+ **
+ ** Bit#1-0 : SWDS[2:0]
+ ** - 0 = SWDGOGCLK = PCLK0
+ ** - 1 = SWDGOGCLK = PCLK0 / 2
+ ** - 2 = SWDGOGCLK = PCLK0 / 4
+ ** - 3 = SWDGOGCLK = PCLK0 / 8
+ ******************************************************************************/  
+#define SWC_PSR_Val           0x00000003ul    // <<< Define SWC_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief Trace Clock Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** TTC_PSR
+ **
+ ** Bit#7-1 : (reserved)
+ **
+ ** Bit#0 : TTC
+ ** - 0 = TPIUCLK = HCLK
+ ** - 1 = TPIUCLK = HCLK / 2
+ ******************************************************************************/  
+#define TTC_PSR_Val           0x00000000ul    // <<< Define TTC_PSR here
+ 
+/**
+ ******************************************************************************
+ ** \brief Clock Stabilization Wait Time Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** CSW_TMR
+ **
+ ** Bit#7 : (reserved)
+ **
+ ** Bit#6-4 : SOWT[2:0]
+ ** - 0 = ~10.3 ms (default)
+ ** - 1 = ~20.5 ms
+ ** - 2 = ~41 ms
+ ** - 3 = ~82 ms
+ ** - 4 = ~164 ms
+ ** - 5 = ~327 ms
+ ** - 6 = ~655 ms
+ ** - 7 = ~1.31 s 
+ **
+ ** Bit#3-0 : MOWT[3:0]
+ ** - 0 = ~500 ns (default)
+ ** - 1 = ~8 us
+ ** - 2 = ~16 us
+ ** - 3 = ~32 us
+ ** - 4 = ~64 us
+ ** - 5 = ~128 us
+ ** - 6 = ~256 us
+ ** - 7 = ~512 us
+ ** - 8 = ~1.0 ms
+ ** - 9 = ~2.0 ms
+ ** - 10 = ~4.0 ms
+ ** - 11 = ~8.0 ms
+ ** - 12 = ~33.0 ms
+ ** - 13 = ~131 ms
+ ** - 14 = ~524 ms
+ ** - 15 = ~2.0 s
+ ******************************************************************************/     
+#define CSW_TMR_Val           0x0000005Cul    // <<< Define CSW_TMR here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Clock Stabilization Wait Time Setup Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** PSW_TMR
+ **
+ ** Bit#7-5 : (reserved)
+ **
+ ** Bit#4 : PINC
+ ** - 0 = Selects CLKMO (main oscillation) (default)
+ ** - 1 = (setting diabled)
+ **
+ ** Bit#3 : (reserved)
+ **
+ ** Bit#2-0 : POWT[2:0]
+ ** - 0 = ~128 us (default) 
+ ** - 1 = ~256 us
+ ** - 2 = ~512 us
+ ** - 3 = ~1.02 ms
+ ** - 4 = ~2.05 ms
+ ** - 5 = ~4.10 ms
+ ** - 6 = ~8.20 ms
+ ** - 7 = ~16.40 ms
+ ******************************************************************************/    
+#define PSW_TMR_Val           0x00000000ul    // <<< Define PSW_TMR here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Control Register 1 value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** PLL_CTL1
+ **
+ ** Bit#7-4 : PLLK[3:0]
+ ** - 0 = Division(PLLK) = 1/1 (default)
+ ** - 1 = Division(PLLK) = 1/2
+ ** - 2 = Division(PLLK) = 1/3
+ ** - . . .
+ ** - 15 = Division(PLLK) = 1/16
+ **
+ ** Bit#3-0 : PLLM[3:0]
+ ** - 0 = Division(PLLM) = 1/1 (default)
+ ** - 1 = Division(PLLM) = 1/2
+ ** - 2 = Division(PLLM) = 1/3
+ ** - . . .
+ ** - 15 = Division(PLLM) = 1/16
+ ******************************************************************************/    
+#define PLL_CTL1_Val          0x00000001ul    // <<< Define PLL_CTL1 here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Control Register 2 value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** PLL_CTL2
+ **
+ ** Bit#7-6 : (reserved)
+ **
+ ** Bit#5-0 : PLLN[5:0]
+ ** - 0 = Division(PLLN) = 1/1 (default)
+ ** - 1 = Division(PLLN) = 1/2
+ ** - 2 = Division(PLLN) = 1/3
+ ** - . . .
+ ** - 63 = Division(PLLN) = 1/64
+ ******************************************************************************/    
+#define PLL_CTL2_Val          0x00000027ul    // <<< Define PLL_CTL2 here
+   
+/**
+ ******************************************************************************
+ ** \brief Hardware Watchdog disable definition
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = Hardware Watchdog enable
+ ** - 1 = Hardware Watchdog disable
+ ******************************************************************************/  
+#define HWWD_DISABLE          1   // <<< Define HW Watach dog enable here
+
+/**
+ ******************************************************************************
+ ** \brief Trimming CR
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = CR is not trimmed at startup
+ ** - 1 = CR is trimmed at startup
+ ******************************************************************************/  
+#define CR_TRIM_SETUP         1   // <<< Define CR trimming at startup enable here
+
+/**
+ ******************************************************************************
+ ** brief Trace Buffer enable definition
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = Trace Buffer disable
+ ** - 1 = Trace Buffer enable
+ ******************************************************************************/  
+#define TRACE_BUFFER_ENABLE   1   // <<< Define Trace Buffer enable here
+
+   
+/******************************************************************************/
+/*                                                                            */
+/*                         END OF USER SETTINGS HERE                          */
+/*                         =========================                          */ 
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Device dependent System Clock absolute maximum ranges                      */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]ul)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/    
+#define __CLKHC        ( 4000000ul)         /* Internal   4MHz CR Oscillator  */
+   
+/**
+ ******************************************************************************
+ ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]ul)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKLC        (  100000ul)         /* Internal 100KHz CR Oscillator  */  
+
+/**
+ ******************************************************************************
+ ** \brief Any case minimum Main Clock frequency (in Hz, [value]ul)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKMOMIN    (  4000000ul)
+   
+/**
+ ******************************************************************************
+ ** \brief Maximum Main Clock frequency using external clock (in Hz, [value]ul)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKMOMAX    ( 48000000ul)
+
+/**
+ ******************************************************************************
+ ** \brief Any case minimum Sub Clock frequency (in Hz, [value]ul)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKSOMIN    (    32000ul)
+   
+/**
+ ******************************************************************************
+ ** \brief Maximum Sub Clock frequency using external clock (in Hz, [value]ul)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKSOMAX    (   100000ul)
+   
+/**
+ ******************************************************************************
+ ** \brief Absolute minimum PLL input frequency (in Hz, [value]ul)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKINMIN (  4000000ul)
+   
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum PLL input frequency (in Hz, [value]ul)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKINMAX ( 16000000ul)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute minimum PLL oscillation frequency (in Hz, [value]ul)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKMIN   (200000000ul)
+   
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum PLL oscillation  frequency (in Hz, [value]ul)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKMAX   (320000000ul)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum System Clock frequency (HCLK) (in Hz, [value]ul)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __HCLKMAX     (160000000ul)
+
+/**
+ ******************************************************************************
+ ** \brief Preprocessor macro for checking range (clock settings).
+ **
+ ** \return 0    Within range
+ ** \return 1    Out of range
+ ******************************************************************************/ 
+#define CHECK_RANGE(val, min, max)          (((val) < (min)) || ((val) > (max)))
+   
+/**
+ ******************************************************************************
+ ** \brief Preprocessor macro for checking bits with mask (clock settings).
+ **        Prevents from setting reserved bits by mistake.
+ **
+ ** \return 0    All bits within mask
+ ** \return 1    One or more bits out of mask
+ ******************************************************************************/ 
+#define CHECK_RSVD(val, mask)                ((val) & (mask))
+
+
+/******************************************************************************/
+/* Check register settings                                                    */
+/******************************************************************************/
+#if (CHECK_RSVD((SCM_CTL_Val),    ~0x000000FAul))
+   #error "SCM_CTL: Invalid values of reserved bits!"
+#endif
+
+#if ((SCM_CTL_Val & 0xE0ul) == 0x40ul) && ((SCM_CTL_Val & 0x10ul) != 0x10ul)
+   #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
+#endif
+
+#if (CHECK_RSVD((CSW_TMR_Val),    ~0x0000007Ful))
+   #error "CSW_TMR: Invalid values of reserved bits!"
+#endif
+
+#if ((SCM_CTL_Val & 0x10ul))       /* if PLL is used */
+  #if (CHECK_RSVD((PSW_TMR_Val),  ~0x00000017ul))
+     #error "PSW_TMR: Invalid values of reserved bits!"
+  #endif
+
+  #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FFul))
+     #error "PLL_CTL1: Invalid values of reserved bits!"
+  #endif
+
+  #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003Ful))
+    #error "PLL_CTL2: Invalid values of reserved bits!"
+  #endif
+#endif
+
+#if (CHECK_RSVD((BSC_PSR_Val),    ~0x00000007ul))
+  #error "BSC_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC0_PSR_Val),  ~0x00000003ul))
+  #error "APBC0_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC1_PSR_Val),  ~0x00000093ul))
+  #error "APBC1_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC2_PSR_Val),  ~0x00000093ul))
+  #error "APBC2_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((SWC_PSR_Val),    ~0x00000003ul))
+  #error "SWC_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((TTC_PSR_Val),    ~0x00000003ul))
+  #error "TTC_PSR: Invalid values of reserved bits!"
+#endif
+
+/******************************************************************************/
+/* Define clocks with checking settings                                       */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL K factor from settings
+ ******************************************************************************/
+#define __PLLK         (((PLL_CTL1_Val >> 4ul) & 0x0Ful) + 1ul)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL N factor from settings
+ ******************************************************************************/
+#define __PLLN         (((PLL_CTL2_Val     ) & 0x3Ful) + 1ul)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL M factor from settings
+ ******************************************************************************/
+#define __PLLM         (((PLL_CTL1_Val     ) & 0x0Ful) + 1ul)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL output frequency from settings
+ ******************************************************************************/
+#define __PLLCLK       ((__CLKMO  * __PLLN) / __PLLK)
+
+/******************************************************************************/
+/* Determine core clock frequency according to settings                       */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Define Master Clock from settings
+ ******************************************************************************/
+#if   (((SCM_CTL_Val >> 5ul) & 0x07UL) == 0ul)
+  #define __MASTERCLK     (__CLKHC)
+#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 1ul)
+  #define __MASTERCLK     (__CLKMO)
+#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 2ul)
+  #define __MASTERCLK     (__PLLCLK)
+#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 4ul)
+  #define __MASTERCLK     (__CLKLC)
+#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 5ul)
+  #define __MASTERCLK     (__CLKSO)
+#else
+  #define __MASTERCLK     (0UL)
+#endif
+
+/**
+ ******************************************************************************
+ ** \brief Define System Clock Frequency (Core Clock) from settings
+ ******************************************************************************/
+#if   ((BSC_PSR_Val & 0x07UL) == 0ul)
+  #define __HCLK         (__MASTERCLK / 1ul)
+#elif ((BSC_PSR_Val & 0x07UL) == 1ul)
+  #define __HCLK         (__MASTERCLK / 2ul)
+#elif ((BSC_PSR_Val & 0x07UL) == 2ul)
+  #define __HCLK         (__MASTERCLK / 3ul)
+#elif ((BSC_PSR_Val & 0x07UL) == 3ul)
+  #define __HCLK         (__MASTERCLK / 4ul)
+#elif ((BSC_PSR_Val & 0x07UL) == 4ul)
+  #define __HCLK         (__MASTERCLK / 6ul)
+#elif ((BSC_PSR_Val & 0x07UL) == 5ul)
+  #define __HCLK         (__MASTERCLK / 8ul)
+#elif ((BSC_PSR_Val & 0x07UL) == 6ul)
+  #define __HCLK         (__MASTERCLK /16ul)
+#else
+  #define __HCLK         (0ul)
+#endif
+
+/******************************************************************************/
+/* HCLK range check                                                           */
+/******************************************************************************/
+#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX))
+  #error "Main Oscillator Clock (CLKMO) out of range!"
+#endif   
+
+#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX))
+  #error "Sub Oscillator Clock (CLKMO) out of range!"
+#endif   
+
+#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX))
+  #error "PLL input frequency out of range!"
+#endif  
+
+#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX))
+  #error "PLL oscillation frequency out of range!"
+#endif  
+   
+#if (CHECK_RANGE(__HCLK, 0UL, __HCLKMAX))
+  #error "System Clock (HCLK) out of range!"
+#endif
+   
+/******************************************************************************/
+/* Global function prototypes ('extern', definition in C source)              */
+/******************************************************************************/
+
+extern uint32_t SystemCoreClock;          // System Clock Frequency (Core Clock)
+   
+extern void SystemInit (void);            // Initialize the system
+
+extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MB9ABXXX_H_ */

bsp/mb9bf568r/CMSIS/Include/arm_common_tables.h

@@ -0,0 +1,35 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved. 
+* 
+* $Date:        11. November 2010  
+* $Revision: 	V1.0.2  
+* 
+* Project: 	    CMSIS DSP Library 
+* Title:	    arm_common_tables.h 
+* 
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.2 2010/11/11 
+*    Documentation updated.  
+* 
+* Version 1.0.1 2010/10/05  
+*    Production release and review comments incorporated. 
+* 
+* Version 1.0.0 2010/09/20  
+*    Production release and review comments incorporated. 
+* -------------------------------------------------------------------- */ 
+ 
+#ifndef _ARM_COMMON_TABLES_H 
+#define _ARM_COMMON_TABLES_H 
+ 
+#include "arm_math.h" 
+ 
+extern uint16_t armBitRevTable[256]; 
+extern q15_t armRecipTableQ15[64]; 
+extern q31_t armRecipTableQ31[64]; 
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+ 
+#endif /*  ARM_COMMON_TABLES_H */ 

bsp/mb9bf568r/CMSIS/Include/core_cm0.h

@@ -0,0 +1,665 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M0
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+
+  The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include <stdint.h>                      /*!< standard types definitions                      */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
+#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
+  and not via processor. Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mb9bf568r/CMSIS/Include/core_cm4_simd.h

@@ -0,0 +1,701 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
+/* intrinsic __SADD8      see intrinsics.h */
+/* intrinsic __QADD8      see intrinsics.h */
+/* intrinsic __SHADD8     see intrinsics.h */
+/* intrinsic __UADD8      see intrinsics.h */
+/* intrinsic __UQADD8     see intrinsics.h */
+/* intrinsic __UHADD8     see intrinsics.h */
+/* intrinsic __SSUB8      see intrinsics.h */
+/* intrinsic __QSUB8      see intrinsics.h */
+/* intrinsic __SHSUB8     see intrinsics.h */
+/* intrinsic __USUB8      see intrinsics.h */
+/* intrinsic __UQSUB8     see intrinsics.h */
+/* intrinsic __UHSUB8     see intrinsics.h */
+/* intrinsic __SADD16     see intrinsics.h */
+/* intrinsic __QADD16     see intrinsics.h */
+/* intrinsic __SHADD16    see intrinsics.h */
+/* intrinsic __UADD16     see intrinsics.h */
+/* intrinsic __UQADD16    see intrinsics.h */
+/* intrinsic __UHADD16    see intrinsics.h */
+/* intrinsic __SSUB16     see intrinsics.h */
+/* intrinsic __QSUB16     see intrinsics.h */
+/* intrinsic __SHSUB16    see intrinsics.h */
+/* intrinsic __USUB16     see intrinsics.h */
+/* intrinsic __UQSUB16    see intrinsics.h */
+/* intrinsic __UHSUB16    see intrinsics.h */
+/* intrinsic __SASX       see intrinsics.h */
+/* intrinsic __QASX       see intrinsics.h */
+/* intrinsic __SHASX      see intrinsics.h */
+/* intrinsic __UASX       see intrinsics.h */
+/* intrinsic __UQASX      see intrinsics.h */
+/* intrinsic __UHASX      see intrinsics.h */
+/* intrinsic __SSAX       see intrinsics.h */
+/* intrinsic __QSAX       see intrinsics.h */
+/* intrinsic __SHSAX      see intrinsics.h */
+/* intrinsic __USAX       see intrinsics.h */
+/* intrinsic __UQSAX      see intrinsics.h */
+/* intrinsic __UHSAX      see intrinsics.h */
+/* intrinsic __USAD8      see intrinsics.h */
+/* intrinsic __USADA8     see intrinsics.h */
+/* intrinsic __SSAT16     see intrinsics.h */
+/* intrinsic __USAT16     see intrinsics.h */
+/* intrinsic __UXTB16     see intrinsics.h */
+/* intrinsic __SXTB16     see intrinsics.h */
+/* intrinsic __UXTAB16    see intrinsics.h */
+/* intrinsic __SXTAB16    see intrinsics.h */
+/* intrinsic __SMUAD      see intrinsics.h */
+/* intrinsic __SMUADX     see intrinsics.h */
+/* intrinsic __SMLAD      see intrinsics.h */
+/* intrinsic __SMLADX     see intrinsics.h */
+/* intrinsic __SMLALD     see intrinsics.h */
+/* intrinsic __SMLALDX    see intrinsics.h */
+/* intrinsic __SMUSD      see intrinsics.h */
+/* intrinsic __SMUSDX     see intrinsics.h */
+/* intrinsic __SMLSD      see intrinsics.h */
+/* intrinsic __SMLSDX     see intrinsics.h */
+/* intrinsic __SMLSLD     see intrinsics.h */
+/* intrinsic __SMLSLDX    see intrinsics.h */
+/* intrinsic __SEL        see intrinsics.h */
+/* intrinsic __QADD       see intrinsics.h */
+/* intrinsic __QSUB       see intrinsics.h */
+/* intrinsic __PKHBT      see intrinsics.h */
+/* intrinsic __PKHTB      see intrinsics.h */
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+  
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else	\
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mb9bf568r/CMSIS/Include/core_cmFunc.h

@@ -0,0 +1,609 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V2.10
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+static __INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+static __INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+static __INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

bsp/mb9bf568r/CMSIS/Include/core_cmInstr.h

@@ -0,0 +1,585 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+  
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/mb9bf568r/CMSIS/SConscript

@@ -0,0 +1,18 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('DeviceSupport/*.c')
+
+CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport']
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'keil':
+	src += ['DeviceSupport/startup_mb9bf56xr.s']
+
+
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf568r/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/mb9bf568r/SConstruct

@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-stm32f4xx.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/mb9bf568r/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf568r/applications/application.c

@@ -0,0 +1,63 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-05-24     Bernard      the first version
+ */
+
+/**
+ * @addtogroup FM4
+ */
+/*@{*/
+
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+void rt_init_thread_entry(void *parameter)
+{
+#ifdef RT_USING_COMPONENTS_INIT
+    /* initialization RT-Thread Components */
+    rt_components_init();
+#endif
+
+
+		//finsh_system_init();
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+
+
+    /**< init led device */
+    {
+        extern void rt_led_hw_init(void);
+        rt_led_hw_init();
+    }
+		{
+        extern int demo_init(void);
+        demo_init();
+    }
+
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init",
+                           rt_init_thread_entry, RT_NULL,
+                           2048, 8, 20);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+
+    return 0;
+}
+
+/*@}*/

bsp/mb9bf568r/applications/demo.c

@@ -0,0 +1,69 @@
+/*
+	此demo用于演示动态线程创建
+ */
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+
+static	rt_thread_t tid1 = RT_NULL;
+static	rt_thread_t tid2 = RT_NULL;
+
+
+static void thread1_entry(void* parameter)
+{
+    rt_uint32_t count = 0;
+
+    rt_kprintf("thread1 dynamicly created ok\n");
+    while (1)
+    {
+        rt_kprintf("thread1 count: %d\n",count++);
+        rt_thread_delay(RT_TICK_PER_SECOND); 
+    }
+}
+						
+static void thread2_entry(void* parameter)
+{		
+		rt_uint32_t count = 0;
+    rt_kprintf("thread2 dynamicly created ok\n");
+	  
+		while(1)
+    {
+				if(count == 3)
+					break;
+        rt_kprintf("thread2 count: %d\n",count++);
+        rt_thread_delay(RT_TICK_PER_SECOND);   
+			
+    }
+    rt_thread_delay(RT_TICK_PER_SECOND * 4);  
+    
+    rt_thread_delete(tid1);							
+    rt_kprintf("thread1 deleted ok\n");
+}
+
+
+int demo_init(void)
+{
+				
+    tid1 = rt_thread_create("thread1",
+				thread1_entry,
+				RT_NULL,
+				512, 6, 10);
+	
+    if (tid1 != RT_NULL)
+        rt_thread_startup(tid1);        
+
+    tid2 = rt_thread_create("thread2",
+        thread2_entry, 
+				RT_NULL,
+        512, 6, 10);
+		
+    if (tid2 != RT_NULL)
+        rt_thread_startup(tid2);
+
+    return 0;
+}

bsp/mb9bf568r/applications/startup.c

@@ -0,0 +1,91 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-02-24     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+/**
+ * @addtogroup FM4
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+	
+    /* init timer system */
+    rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM4_SRAM_END);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void*)FM4_SRAM_END);
+#else
+    /* init memory system */
+    rt_system_heap_init((void*)&__bss_end, (void*)FM4_SRAM_END);
+#endif
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/

bsp/mb9bf568r/drivers/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf568r/drivers/board.c

@@ -0,0 +1,100 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-02-24     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#include "serial.h"
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+/**
+ * @addtogroup FM4
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This fucntion returns milliseconds since system passed
+ */
+rt_uint32_t rt_hw_tick_get_millisecond(void)
+{
+    rt_tick_t tick;
+    rt_uint32_t value;
+
+#define TICK_MS (1000/RT_TICK_PER_SECOND)
+
+    tick = rt_tick_get();
+    value = tick * TICK_MS + (SysTick->LOAD - SysTick->VAL) * TICK_MS / SysTick->LOAD;
+
+    return value;
+}
+
+/**
+ * This fucntion returns microseconds since system passed
+ */
+rt_uint32_t rt_hw_tick_get_microsecond(void)
+{
+    rt_tick_t tick;
+    rt_uint32_t value;
+
+#define TICK_US	(1000000/RT_TICK_PER_SECOND)
+
+    tick = rt_tick_get();
+    value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD;
+
+    return value;
+}
+
+/**
+* This function will initial FM3 Easy Kit board.
+ */
+void rt_hw_board_init(void)
+{
+    /* disable all analog input. */
+    FM4_GPIO->ADE = 0x00u;
+
+    /* init systick */
+    SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND);
+
+    /* initialize UART device */
+    rt_hw_serial_init();
+    /* set console as UART device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/*@}*/

bsp/mb9bf568r/drivers/board.h

@@ -0,0 +1,39 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2011-03-04     lgnq         add board.h to FM3 bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+
+#include <system_mb9bf56xr.h>
+#include <mb9b560r.h>
+#include <base_types.h>
+
+#include "serial.h"
+
+
+#define FM4_SRAM_SIZE         128
+#define FM4_SRAM_END          (0x1FFF0000 + FM4_SRAM_SIZE * 1024)
+
+/* RT_USING_UART */
+#define RT_USING_UART0
+
+#define RT_UART_RX_BUFFER_SIZE        128
+
+void rt_hw_board_init(void);
+rt_uint32_t rt_hw_tick_get_millisecond(void);
+rt_uint32_t rt_hw_tick_get_microsecond(void);
+
+#endif

bsp/mb9bf568r/drivers/led.c

@@ -0,0 +1,155 @@
+#include <rtthread.h>
+#include "board.h"
+
+#define RT_DEVICE_CTRL_RTC_GET_COUNT        0x81        /**< get count                                   */
+
+#define LED_NUM                             3
+struct fm4_gpio_ctrl
+{
+    uint32_t led_num;
+    volatile uint32_t * PDOR;
+    volatile uint32_t * PDIR;
+};
+
+struct fm4_led
+{
+    /* inherit from rt_device */
+    struct rt_device parent;
+
+    struct fm4_gpio_ctrl fm4_gpio_ctrl[LED_NUM];
+};
+
+static struct fm4_led fm4_led;
+
+static rt_err_t rt_led_init (rt_device_t dev)
+{
+    uint32_t i;
+
+    /* led0-1-2 : P27-P38-PE0 */
+    FM4_GPIO->PFR2 &= ~((1<<7) );  /* set P27 fuction is GPIO. */
+    FM4_GPIO->DDR2 |=  (1<<7) ;    /* set P27 output. */
+		FM4_GPIO->PFR3 &= ~((1<<8) );  /* set P38 fuction is GPIO. */
+    FM4_GPIO->DDR3 |=  (1<<8) ;    /* set P38 output. */
+		FM4_GPIO->PFRE &= ~((1<<0) );  /* set PE0 fuction is GPIO. */
+    FM4_GPIO->DDRE |=  (1<<0) ;    /* set PE0 output. */
+
+    /* LED0 */
+    i = 0;
+    fm4_led.fm4_gpio_ctrl[i].led_num = 7;
+    fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDOR2;
+    fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIR2;
+
+    /* LED1 */
+    i++;
+    fm4_led.fm4_gpio_ctrl[i].led_num = 8;
+    fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDOR3;
+    fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIR3;
+
+    /* LED2 */
+    i++;
+    fm4_led.fm4_gpio_ctrl[i].led_num = 0;
+    fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDORE;
+    fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIRE;
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t rt_led_read (rt_device_t dev, rt_off_t pos, void* buffer,
+                              rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nr = size;
+    rt_uint8_t * value = buffer;
+
+    RT_ASSERT(dev == &fm4_led.parent);
+    RT_ASSERT((pos+size) <= LED_NUM );
+
+    for(index=0; index<nr; index++)
+    {
+        if(*fm4_led.fm4_gpio_ctrl[pos+index].PDIR & 1<<fm4_led.fm4_gpio_ctrl[pos+index].led_num)
+        {
+            *value = 0;
+        }
+        else
+        {
+            *value = 1;
+        }
+        value++;
+    }
+    return index;
+}
+
+static rt_size_t rt_led_write (rt_device_t dev, rt_off_t pos,
+                               const void* buffer, rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nw = size;
+    const rt_uint8_t * value = buffer;
+
+    RT_ASSERT(dev == &fm4_led.parent);
+    RT_ASSERT((pos+size) <= LED_NUM );
+
+    for(index=0; index<nw; index++)
+    {
+        if(*value++)
+        {
+            *fm4_led.fm4_gpio_ctrl[pos+index].PDOR &= ~(1<<fm4_led.fm4_gpio_ctrl[pos+index].led_num);
+        }
+        else
+        {
+            *fm4_led.fm4_gpio_ctrl[pos+index].PDOR |= (1<<fm4_led.fm4_gpio_ctrl[pos+index].led_num);
+        }
+    }
+    return index;
+}
+
+static rt_err_t rt_led_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev == &fm4_led.parent);
+
+    if(cmd == RT_DEVICE_CTRL_RTC_GET_COUNT)
+    {
+        rt_uint32_t * led_num = args;
+        *led_num = LED_NUM;
+    }
+    return RT_EOK;
+}
+
+void rt_led_hw_init(void)
+{
+    fm4_led.parent.type 		= RT_Device_Class_Char;
+    fm4_led.parent.rx_indicate  = RT_NULL;
+    fm4_led.parent.tx_complete  = RT_NULL;
+    fm4_led.parent.init 		= rt_led_init;
+    fm4_led.parent.open		    = rt_led_open;
+    fm4_led.parent.close		= rt_led_close;
+    fm4_led.parent.read         = rt_led_read;
+    fm4_led.parent.write 		= rt_led_write;
+    fm4_led.parent.control 	    = rt_led_control;
+    fm4_led.parent.user_data	= RT_NULL;
+
+    /* register a character device */
+    rt_device_register(&fm4_led.parent, "led", RT_DEVICE_FLAG_RDWR);
+    /* init led device */
+    rt_led_init(&fm4_led.parent);
+}
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+void led(rt_uint32_t led, rt_uint32_t value)
+{
+    rt_uint8_t led_value = value;
+    rt_led_write(&fm4_led.parent, led, &led_value, 1);
+}
+FINSH_FUNCTION_EXPORT(led, e.g:led(0,0)/led(0,1).)
+#endif

bsp/mb9bf568r/drivers/mcu.h

@@ -0,0 +1,65 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+/**
+ ******************************************************************************
+ ** \file   mcu.h
+ **
+ ** Header File for device dependent includes
+ **
+ ** History:
+ ** 2011-05-19 V1.00 MWi first version
+ **
+ ******************************************************************************/
+
+#define  PDL_INT_TYPE_C		1
+#define  PDL_INT_TYPE_A		2
+
+#define PDL_MCU_INT_TYPE  PDL_INT_TYPE_A
+
+/**
+ ******************************************************************************
+ ** \brief MCU header file include
+ **
+ ******************************************************************************/ 
+#ifndef _MB9B560R_H_
+  #include "mb9b560r.h"
+#endif
+
+/**
+ ******************************************************************************
+ ** \brief MCU system start-up header file include
+ **
+ ******************************************************************************/ 
+#ifndef _SYSTEM_MB9ABXXX_H_
+  #include "system_mb9bf56xr.h"
+#endif

bsp/mb9bf568r/drivers/serial.c

@@ -0,0 +1,359 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ * 2011-05-15     lgnq         modified according bernard's implementaion.
+ */
+
+#include <rtthread.h>
+
+#include "serial.h"
+
+/**
+ * @addtogroup FM4 MB9BF568R
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+/**
+ * This function initializes serial
+ */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+    struct serial_device* uart = (struct serial_device*) dev->user_data;
+
+    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+    {
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            rt_memset(uart->int_rx->rx_buffer, 0,
+                      sizeof(uart->int_rx->rx_buffer));
+            uart->int_rx->read_index = uart->int_rx->save_index = 0;
+        }
+
+        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            rt_memset(uart->int_tx->tx_buffer, 0,
+                      sizeof(uart->int_tx->tx_buffer));
+            uart->int_tx->write_index = uart->int_tx->save_index = 0;
+        }
+
+        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    }
+
+    return RT_EOK;
+}
+
+/* save a char to serial buffer */
+static void rt_serial_savechar(struct serial_device* uart, char ch)
+{
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
+    uart->int_rx->save_index ++;
+    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+        uart->int_rx->save_index = 0;
+
+    /* if the next position is read index, discard this 'read char' */
+    if (uart->int_rx->save_index == uart->int_rx->read_index)
+    {
+        uart->int_rx->read_index ++;
+        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+            uart->int_rx->read_index = 0;
+    }
+
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    struct serial_device* uart;
+
+    RT_ASSERT(dev != RT_NULL);
+    uart = (struct serial_device*) dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* enable interrupt */
+        UART_ENABLE_IRQ(uart->rx_irq);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+    struct serial_device* uart;
+
+    RT_ASSERT(dev != RT_NULL);
+    uart = (struct serial_device*) dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* disable interrupt */
+        UART_DISABLE_IRQ(uart->rx_irq);
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer,
+                                 rt_size_t size)
+{
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
+
+    ptr = buffer;
+    err_code = RT_EOK;
+    uart = (struct serial_device*)dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        rt_base_t level;
+
+        /* interrupt mode Rx */
+        while (size)
+        {
+            if (uart->int_rx->read_index != uart->int_rx->save_index)
+            {
+                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+                size --;
+
+                /* disable interrupt */
+                level = rt_hw_interrupt_disable();
+
+                uart->int_rx->read_index ++;
+                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+                    uart->int_rx->read_index = 0;
+
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+            }
+            else
+            {
+                /* set error code */
+                err_code = -RT_EEMPTY;
+                break;
+            }
+        }
+    }
+    else
+    {
+        /* polling mode */
+        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+        {
+            while (uart->uart_device->SSR & SSR_RDRF)
+            {
+                *ptr = uart->uart_device->RDR & 0xff;
+                ptr ++;
+            }
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos,
+                                  const void* buffer, rt_size_t size)
+{
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
+
+    err_code = RT_EOK;
+    ptr = (rt_uint8_t*)buffer;
+    uart = (struct serial_device*)dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* interrupt mode Tx */
+        while (uart->int_tx->save_index != uart->int_tx->write_index)
+        {
+            /* save on tx buffer */
+            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
+
+            -- size;
+
+            /* move to next position */
+            uart->int_tx->save_index ++;
+
+            /* wrap save index */
+            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+                uart->int_tx->save_index = 0;
+        }
+
+        /* set error code */
+        if (size > 0)
+            err_code = -RT_EFULL;
+    }
+    else
+    {
+        /* polling mode */
+        while (size)
+        {
+            /*
+             * to be polite with serial console add a line feed
+             * to the carriage return character
+             */
+            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
+            {
+                while (!(uart->uart_device->SSR & SSR_TDRE));
+                uart->uart_device->TDR = '\r';
+            }
+
+            while (!(uart->uart_device->SSR & SSR_TDRE));
+            uart->uart_device->TDR = (*ptr & 0x1FF);
+
+            ++ptr;
+            --size;
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        break;
+
+    case RT_DEVICE_CTRL_RESUME:
+        /* resume device */
+        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+        break;
+    }
+
+    return RT_EOK;
+}
+
+/*
+ * serial register
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name,
+                               rt_uint32_t flag, struct serial_device *serial)
+{
+    RT_ASSERT(device != RT_NULL);
+
+    device->type 		= RT_Device_Class_Char;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init 		= rt_serial_init;
+    device->open		= rt_serial_open;
+    device->close		= rt_serial_close;
+    device->read 		= rt_serial_read;
+    device->write 		= rt_serial_write;
+    device->control 	= rt_serial_control;
+    device->user_data	= serial;
+
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+    struct serial_device* uart = (struct serial_device*) device->user_data;
+
+    /* interrupt mode receive */
+    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+    /* save on rx buffer */
+    while (uart->uart_device->SSR & SSR_RDRF)
+    {
+        rt_serial_savechar(uart, uart->uart_device->RDR & 0xff);
+    }
+
+    /* invoke callback */
+    if (device->rx_indicate != RT_NULL)
+    {
+        rt_size_t rx_length;
+
+        /* get rx length */
+        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+                    UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+                    uart->int_rx->save_index - uart->int_rx->read_index;
+
+        device->rx_indicate(device, rx_length);
+    }
+}
+
+#ifdef RT_USING_UART0
+/* UART0 device driver structure */
+#define UART0	FM4_MFS0
+struct serial_int_rx uart0_int_rx;
+struct serial_device uart0 =
+{
+    UART0,
+    MFS0_RX_IRQn,
+    MFS0_TX_IRQn,
+    &uart0_int_rx,
+    RT_NULL
+};
+struct rt_device uart0_device;
+
+void MFS0_RX_IRQHandler(void)
+{	 
+		/* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&uart0_device);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+
+#endif /**< #ifdef RT_USING_UART0 */
+
+
+void rt_hw_serial_init(void)
+{
+		uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03));
+	
+#ifdef RT_USING_UART0
+     // Initialize ports for MFS0
+		FM4_GPIO->PFR2   = 0x06u;   // P21>SIN0_0, P22>SOT0_0
+		FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful;
+		FM4_GPIO->EPFR07 |= 0x00000040ul;
+		
+		// Initialize MFS to UART asynchronous mode
+		
+		uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
+    uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
+    uart0.uart_device->ESCR = ESCR_DATABITS_8;
+    uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+		
+    /* register UART0 device */
+    rt_hw_serial_register(&uart0_device,
+                          "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart0);
+													
+		
+#endif /**< #ifdef RT_USING_UART0 */
+
+}
+
+/*@}*/

bsp/mb9bf568r/drivers/serial.h

@@ -0,0 +1,100 @@
+/*
+ * File      : serial.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ * 2011-05-15     lgnq         modified according bernard's implementaion.      	  	
+ */
+
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#define SMR_SOE          0x01U
+#define SMR_BDS          0x04U
+#define SMR_SBL          0x08U
+#define SMR_WUCR         0x10U
+#define SMR_MD_UART      0x00U
+#define SMR_MD_UART_MP   0x20U
+#define SMR_MD_SIO       0x40U
+#define SMR_MD_LIN       0x60U
+#define SMR_MD_I2C       0x80U
+
+#define SCR_TXE          0x01U
+#define SCR_RXE          0x02U
+#define SCR_TBIE         0x04U
+#define SCR_TIE          0x08U
+#define SCR_RIE          0x10U
+#define SCR_UPGL         0x80U
+
+#define SSR_TBI          0x01U
+#define SSR_TDRE         0x02U
+#define SSR_RDRF         0x04U
+#define SSR_ORE          0x08U
+#define SSR_FRE          0x10U
+#define SSR_PE           0x20U
+#define SSR_REC          0x80U
+
+#define ESCR_P           0x08U
+#define ESCR_PEN         0x10U
+#define ESCR_INV         0x20U
+#define ESCR_ESBL        0x40U
+#define ESCR_FLWEN       0x80U
+#define ESCR_DATABITS_8  0x00U
+#define ESCR_DATABITS_5  0x01U
+#define ESCR_DATABITS_6  0x02U
+#define ESCR_DATABITS_7  0x03U
+#define ESCR_DATABITS_9  0x04U
+
+#define BPS					115200	/* serial baudrate */
+
+#define UART_RX_BUFFER_SIZE		128
+#define UART_TX_BUFFER_SIZE		128
+
+struct serial_int_rx
+{
+	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+	rt_uint32_t read_index, save_index;
+};
+
+struct serial_int_tx
+{
+	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
+	rt_uint32_t write_index, save_index;
+};
+
+/*
+ *  Enable/DISABLE Interrupt Controller
+ */
+/* deviation from MISRA-C:2004 Rule 19.7 */
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+struct serial_device
+{
+	FM4_MFS_TypeDef* uart_device;
+	/* irq number */
+	IRQn_Type rx_irq;
+	IRQn_Type tx_irq;
+
+	/* rx structure */
+	struct serial_int_rx* int_rx;
+	/* tx structure */
+	struct serial_int_tx* int_tx;
+};
+
+void rt_hw_serial_isr(rt_device_t device);
+void rt_hw_serial_init(void);
+
+#endif

bsp/mb9bf568r/project.uvopt

@@ -0,0 +1,844 @@
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+
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+  <Header>### uVision Project, (C) Keil Software</Header>
+
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+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
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+      <ListingPage>
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+      <Tracepoint>
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+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IRAM>
+              <IROM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x200c0000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20038000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>applications;.;CMSIS\Include;CMSIS\DeviceSupport;drivers;E:/work/xiaoyang/rt-thread/include;E:/work/xiaoyang/rt-thread/libcpu/arm/cortex-m4;E:/work/xiaoyang/rt-thread/libcpu/arm/common;E:/work/xiaoyang/rt-thread/components/finsh;E:/work/xiaoyang/rt-thread/components/init</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x00000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc> --keep __fsym_* --keep __vsym_*   --keep __rt_init* </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>application.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\application.c</FilePath>
+            </File>
+            <File>
+              <FileName>demo.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\demo.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\startup.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
+          <Files>
+            <File>
+              <FileName>system_mb9abxxx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>CMSIS\DeviceSupport\system_mb9abxxx.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_mb9bf56xr.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>CMSIS\DeviceSupport\startup_mb9bf56xr.s</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>led.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\led.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\serial.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CORTEX-M4</GroupName>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/libcpu/arm/cortex-m4\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/libcpu/arm/cortex-m4\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/libcpu/arm/common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/libcpu/arm/common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/libcpu/arm/common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\symbol.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_compiler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_compiler.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_error.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_heap.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_init.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_node.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_node.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_ops.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_parser.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_parser.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_var.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_var.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_vm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_vm.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_token.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/finsh\finsh_token.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Components</GroupName>
+          <Files>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>E:/work/xiaoyang/rt-thread/components/init\components.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>

bsp/mb9bf568r/rtconfig.h

@@ -0,0 +1,74 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX				        8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE			        4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	        64
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND		        100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore */
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+
+/* SECTION: Console options */
+/* #define RT_TINY_SIZE */
+#define RT_USING_CONSOLE
+/* the buffer size of console */
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME	        "uart0"
+
+/* SECTION: finsh, a C-Express shell */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_STACK_SIZE         1024
+
+#endif

bsp/mb9bf568r/rtconfig.py

@@ -0,0 +1,82 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+BOARD_NAME = 'lpc408x'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= r'D:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'D:/Keil'
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-' + BOARD_NAME + '.map,-cref,-u,Reset_Handler -T rtthread-' + BOARD_NAME + '.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread_' + \
+        BOARD_NAME + '.map --scatter rtthread-' + BOARD_NAME + '.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'

bsp/mb9bf568r/template.uvopt

@@ -0,0 +1,172 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread-fm4</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>4000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>14</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"CMSIS-DAP" -U	 -O175 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(0) -FO15 -FD20000000 -FC8000 -FN2 -FF0MB9B560_1024 -FS00 -FL0100000 -FF1MB9B560_WORK32 -FS1200C0000 -FL18000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Source Group 1</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+  </Group>
+
+</ProjectOpt>

bsp/mb9bf568r/template.uvproj

@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread-fm4</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>Cortex-M4 FPU</Device>
+          <Vendor>ARM</Vendor>
+          <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId>5237</DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>template_mb9b56xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>14</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\CMSIS_AGDI.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4105</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\CMSIS_AGDI.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>0</AdsALst>
+            <AdsACrf>0</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>0</AdsLcgr>
+            <AdsLsym>0</AdsLsym>
+            <AdsLszi>0</AdsLszi>
+            <AdsLtoi>0</AdsLtoi>
+            <AdsLsun>0</AdsLsun>
+            <AdsLven>0</AdsLven>
+            <AdsLsxf>0</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>0</hadIROM>
+            <hadIRAM>0</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>0</RoSelD>
+            <RwSelD>5</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>1</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IRAM>
+              <IROM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x200c0000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20038000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x00000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Group 1</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>