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STM32H7系列无需DMA_CHANNEL_X

This commit is contained in:
qinge 2021-11-11 19:05:24 +08:00
parent 31f0a9c2ac
commit e1c281c95d
2 changed files with 0 additions and 23 deletions
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13
bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h
View File

@ -42,7 +42,6 @@ extern "C" {
#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler #define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_RX_DMA_INSTANCE DMA1_Stream2 #define SPI3_RX_DMA_INSTANCE DMA1_Stream2
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn #define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
#endif #endif
@ -51,7 +50,6 @@ extern "C" {
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler #define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI2_RX_DMA_INSTANCE DMA1_Stream3 #define SPI2_RX_DMA_INSTANCE DMA1_Stream3
#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn #define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
#endif #endif
@ -60,7 +58,6 @@ extern "C" {
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler #define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI2_TX_DMA_INSTANCE DMA1_Stream4 #define SPI2_TX_DMA_INSTANCE DMA1_Stream4
#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn #define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
#endif #endif
@ -70,7 +67,6 @@ extern "C" {
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler #define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_TX_DMA_INSTANCE DMA1_Stream5 #define SPI3_TX_DMA_INSTANCE DMA1_Stream5
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn #define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
#endif #endif
@ -81,7 +77,6 @@ extern "C" {
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler #define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN #define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_TX_DMA_INSTANCE DMA1_Stream7 #define SPI3_TX_DMA_INSTANCE DMA1_Stream7
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn #define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
#endif #endif
@ -90,7 +85,6 @@ extern "C" {
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler #define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0 #define SPI1_RX_DMA_INSTANCE DMA2_Stream0
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn #define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
#endif #endif
@ -99,7 +93,6 @@ extern "C" {
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler #define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream1 #define SPI4_TX_DMA_INSTANCE DMA2_Stream1
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4
#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn #define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
#endif #endif
@ -108,7 +101,6 @@ extern "C" {
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler #define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2 #define SPI1_RX_DMA_INSTANCE DMA2_Stream2
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn #define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
#endif #endif
@ -117,7 +109,6 @@ extern "C" {
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler #define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3 #define SPI5_RX_DMA_INSTANCE DMA2_Stream3
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn #define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
#endif #endif
@ -126,7 +117,6 @@ extern "C" {
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler #define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_TX_DMA_INSTANCE DMA2_Stream4 #define SPI5_TX_DMA_INSTANCE DMA2_Stream4
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn #define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
#endif #endif
@ -135,7 +125,6 @@ extern "C" {
#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler #define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Stream5 #define SPI1_TX_DMA_INSTANCE DMA2_Stream5
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn #define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
#endif #endif
@ -144,7 +133,6 @@ extern "C" {
#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler #define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN #define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6 #define SPI5_TX_DMA_INSTANCE DMA2_Stream6
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn #define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
#endif #endif
@ -153,7 +141,6 @@ extern "C" {
#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler #define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN #define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
#define QSPI_DMA_INSTANCE DMA2_Stream7 #define QSPI_DMA_INSTANCE DMA2_Stream7
#define QSPI_DMA_CHANNEL DMA_CHANNEL_3
#define QSPI_DMA_IRQ DMA2_Stream7_IRQn #define QSPI_DMA_IRQ DMA2_Stream7_IRQn
#endif #endif

10
bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h
View File

@ -34,7 +34,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI1_TX_DMA_RCC, \ .dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \ .Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.dma_irq = SPI1_TX_DMA_IRQ, \ .dma_irq = SPI1_TX_DMA_IRQ, \
} }
#endif /* SPI1_TX_DMA_CONFIG */ #endif /* SPI1_TX_DMA_CONFIG */
@ -46,7 +45,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI1_RX_DMA_RCC, \ .dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \ .Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.dma_irq = SPI1_RX_DMA_IRQ, \ .dma_irq = SPI1_RX_DMA_IRQ, \
} }
#endif /* SPI1_RX_DMA_CONFIG */ #endif /* SPI1_RX_DMA_CONFIG */
@ -69,7 +67,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI2_TX_DMA_RCC, \ .dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \ .Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.dma_irq = SPI2_TX_DMA_IRQ, \ .dma_irq = SPI2_TX_DMA_IRQ, \
} }
#endif /* SPI2_TX_DMA_CONFIG */ #endif /* SPI2_TX_DMA_CONFIG */
@ -81,7 +78,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI2_RX_DMA_RCC, \ .dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \ .Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.dma_irq = SPI2_RX_DMA_IRQ, \ .dma_irq = SPI2_RX_DMA_IRQ, \
} }
#endif /* SPI2_RX_DMA_CONFIG */ #endif /* SPI2_RX_DMA_CONFIG */
@ -104,7 +100,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI3_TX_DMA_RCC, \ .dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \ .Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.dma_irq = SPI3_TX_DMA_IRQ, \ .dma_irq = SPI3_TX_DMA_IRQ, \
} }
#endif /* SPI3_TX_DMA_CONFIG */ #endif /* SPI3_TX_DMA_CONFIG */
@ -116,7 +111,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI3_RX_DMA_RCC, \ .dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \ .Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.dma_irq = SPI3_RX_DMA_IRQ, \ .dma_irq = SPI3_RX_DMA_IRQ, \
} }
#endif /* SPI3_RX_DMA_CONFIG */ #endif /* SPI3_RX_DMA_CONFIG */
@ -139,7 +133,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI4_TX_DMA_RCC, \ .dma_rcc = SPI4_TX_DMA_RCC, \
.Instance = SPI4_TX_DMA_INSTANCE, \ .Instance = SPI4_TX_DMA_INSTANCE, \
.channel = SPI4_TX_DMA_CHANNEL, \
.dma_irq = SPI4_TX_DMA_IRQ, \ .dma_irq = SPI4_TX_DMA_IRQ, \
} }
#endif /* SPI4_TX_DMA_CONFIG */ #endif /* SPI4_TX_DMA_CONFIG */
@ -151,7 +144,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI4_RX_DMA_RCC, \ .dma_rcc = SPI4_RX_DMA_RCC, \
.Instance = SPI4_RX_DMA_INSTANCE, \ .Instance = SPI4_RX_DMA_INSTANCE, \
.channel = SPI4_RX_DMA_CHANNEL, \
.dma_irq = SPI4_RX_DMA_IRQ, \ .dma_irq = SPI4_RX_DMA_IRQ, \
} }
#endif /* SPI4_RX_DMA_CONFIG */ #endif /* SPI4_RX_DMA_CONFIG */
@ -174,7 +166,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI5_TX_DMA_RCC, \ .dma_rcc = SPI5_TX_DMA_RCC, \
.Instance = SPI5_TX_DMA_INSTANCE, \ .Instance = SPI5_TX_DMA_INSTANCE, \
.channel = SPI5_TX_DMA_CHANNEL, \
.dma_irq = SPI5_TX_DMA_IRQ, \ .dma_irq = SPI5_TX_DMA_IRQ, \
} }
#endif /* SPI5_TX_DMA_CONFIG */ #endif /* SPI5_TX_DMA_CONFIG */
@ -186,7 +177,6 @@ extern "C" {
{ \ { \
.dma_rcc = SPI5_RX_DMA_RCC, \ .dma_rcc = SPI5_RX_DMA_RCC, \
.Instance = SPI5_RX_DMA_INSTANCE, \ .Instance = SPI5_RX_DMA_INSTANCE, \
.channel = SPI5_RX_DMA_CHANNEL, \
.dma_irq = SPI5_RX_DMA_IRQ, \ .dma_irq = SPI5_RX_DMA_IRQ, \
} }
#endif /* SPI5_RX_DMA_CONFIG */ #endif /* SPI5_RX_DMA_CONFIG */