From df715100f2239d2ee12be486e1fa1b1c6fa361c1 Mon Sep 17 00:00:00 2001 From: yuanzihao Date: Fri, 28 Jun 2024 23:41:31 +0800 Subject: [PATCH] [BSP][HC32]add lckfb-hc32f4a0-lqfp100 (#9119) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * -以ev_hc32f4a0_lqfp176为模板进行修改 * -修改对应引脚 * -更新readme * -update readme * -添加 lckfb-hc32f4a0-lqfp100 --- .github/workflows/bsp_buildings.yml | 1 + bsp/hc32/README.md | 1 + bsp/hc32/lckfb-hc32f4a0-lqfp100/.config | 1226 +++++++ bsp/hc32/lckfb-hc32f4a0-lqfp100/.cproject | 216 ++ bsp/hc32/lckfb-hc32f4a0-lqfp100/.gitignore | 42 + bsp/hc32/lckfb-hc32f4a0-lqfp100/.project | 68 + bsp/hc32/lckfb-hc32f4a0-lqfp100/Kconfig | 12 + bsp/hc32/lckfb-hc32f4a0-lqfp100/README.md | 97 + bsp/hc32/lckfb-hc32f4a0-lqfp100/SConscript | 15 + bsp/hc32/lckfb-hc32f4a0-lqfp100/SConstruct | 62 + .../applications/SConscript | 15 + .../applications/main.c | 33 + .../applications/xtal32_fcm.c | 98 + bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig | 936 ++++++ .../lckfb-hc32f4a0-lqfp100/board/SConscript | 38 + bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c | 165 + bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h | 53 + .../board/board_config.c | 701 ++++ .../board/board_config.h | 678 ++++ .../board/config/adc_config.h | 94 + .../board/config/can_config.h | 136 + .../board/config/dac_config.h | 42 + .../board/config/dma_config.h | 372 +++ .../board/config/eth_config.h | 40 + .../board/config/gpio_config.h | 175 + .../board/config/i2c_config.h | 331 ++ .../board/config/irq_config.h | 479 +++ .../board/config/pm_config.h | 99 + .../board/config/pulse_encoder_config.h | 544 +++ .../board/config/pwm_tmr_config.h | 881 +++++ .../board/config/qspi_config.h | 74 + .../board/config/sdio_config.h | 92 + .../board/config/spi_config.h | 376 +++ .../board/config/timer_config.h | 247 ++ .../board/config/uart_config.h | 728 ++++ .../board/config/usb_config/usb_app_conf.h | 164 + .../board/config/usb_config/usb_bsp.h | 42 + .../lckfb-hc32f4a0-lqfp100/board/drv_config.h | 40 + .../board/hc32f4xx_conf.h | 204 ++ .../board/linker_scripts/link.icf | 115 + .../board/linker_scripts/link.ld | 270 ++ .../board/linker_scripts/link.sct | 22 + .../board/ports/SConscript | 12 + .../board/ports/drv_spi_flash.c | 122 + .../board/ports/fal/SConscript | 20 + .../board/ports/fal/fal_cfg.h | 42 + .../board/ports/fal/fal_flash_sfud_port.c | 84 + .../board/ports/nand_port.h | 83 + .../board/ports/sdram_port.h | 88 + .../board/ports/tca9539.c | 319 ++ .../board/ports/tca9539.h | 135 + .../lckfb-hc32f4a0-lqfp100/figures/board.png | Bin 0 -> 871042 bytes bsp/hc32/lckfb-hc32f4a0-lqfp100/project.ewd | 2974 +++++++++++++++++ bsp/hc32/lckfb-hc32f4a0-lqfp100/project.ewp | 2239 +++++++++++++ bsp/hc32/lckfb-hc32f4a0-lqfp100/project.eww | 10 + .../lckfb-hc32f4a0-lqfp100/project.uvoptx | 1100 ++++++ .../lckfb-hc32f4a0-lqfp100/project.uvprojx | 2217 ++++++++++++ bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h | 354 ++ bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py | 150 + bsp/hc32/lckfb-hc32f4a0-lqfp100/template.ewp | 1927 +++++++++++ bsp/hc32/lckfb-hc32f4a0-lqfp100/template.eww | 10 + .../lckfb-hc32f4a0-lqfp100/template.uvoptx | 184 + .../lckfb-hc32f4a0-lqfp100/template.uvprojx | 392 +++ 63 files changed, 22486 insertions(+) create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/.config create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/.cproject create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/.gitignore create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/.project create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/Kconfig create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/README.md create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/SConscript create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/SConstruct create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/SConscript create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/main.c create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/SConscript create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/drv_config.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.ld create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.sct create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/SConscript create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/drv_spi_flash.c create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/SConscript create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_cfg.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_flash_sfud_port.c create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.c create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/figures/board.png create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/project.ewd create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/project.ewp create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/project.eww create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/project.uvoptx create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/project.uvprojx create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/template.ewp create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/template.eww create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvoptx create mode 100644 bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvprojx diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 5383c7bcac..b5c3eab558 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -87,6 +87,7 @@ jobs: - "hc32/ev_hc32f448_lqfp80" - "hc32/ev_hc32f460_lqfp100_v2" - "hc32/ev_hc32f472_lqfp100" + - "hc32/lckfb-hc32f4a0-lqfp100" - "hc32l196" - "mm32/mm32f3270-100ask-pitaya" - "mm32f327x" diff --git a/bsp/hc32/README.md b/bsp/hc32/README.md index 5ab5ea2643..57f03240a5 100644 --- a/bsp/hc32/README.md +++ b/bsp/hc32/README.md @@ -11,6 +11,7 @@ HC32 系列 BSP 目前支持情况如下表所示： | [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 | | [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 | | [ev_hc32f472_lqfp100](ev_hc32f472_lqfp100) | 小华 官方 EV_F472_LQ100 开发板 | +| [lckfb-hc32f4a0-lqfp100](lckfb-hc32f4a0-lqfp100) | 立创开发板 天空星-HC32F4A0PITB | | **M1 系列** | | | **M4 系列** | | diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.config b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.config new file mode 100644 index 0000000000..5909e96105 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.config @@ -0,0 +1,1226 @@ + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice optimization + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# end of klibc optimization + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_HC32=y +CONFIG_SOC_SERIES_HC32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HC32F4A0SI=y + +# +# On-chip Drivers +# +CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_DCODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH=y +# end of On-chip Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_EXMC is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +# CONFIG_BSP_USING_TCA9539 is not set +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_UART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_WDT_TMR is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_PM is not set +# CONFIG_BSP_USING_HWCRYPTO is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set +# CONFIG_BSP_USING_HWTIMER is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.cproject b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.cproject new file mode 100644 index 0000000000..fc9c48d312 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.cproject @@ -0,0 +1,216 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.gitignore b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.project b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.project new file mode 100644 index 0000000000..d8904aee72 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.project @@ -0,0 +1,68 @@ + + + project + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/bsp + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-3-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-3-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-3-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-3-PROJECT_LOC%7D/src + + + rt-thread/bsp/hc32 + 2 + virtual:/virtual + + + rt-thread/bsp/hc32/libraries + 2 + $%7BPARENT-1-PROJECT_LOC%7D/libraries + + + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/Kconfig b/bsp/hc32/lckfb-hc32f4a0-lqfp100/Kconfig new file mode 100644 index 0000000000..73238d3a13 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/README.md b/bsp/hc32/lckfb-hc32f4a0-lqfp100/README.md new file mode 100644 index 0000000000..eff1c0be86 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/README.md @@ -0,0 +1,97 @@ +# lckfb-hc32f4a0-lqfp100立创天空星开发板BSP说明 + +## 简介 + +该开发板是由立创开发板精心打造的一款高性价比的开发工具，**软硬件全开源**。设计上充分考虑了与多种100脚封装的单片机的兼容性。这种设计使得它不仅适用于特定的芯片，还能够适配市场上多种不同厂家生产的100脚微控制器，极大地提高了适用范围和灵活性。该BSP适配立创梁山派·天空星开发板的主控芯片为**HC32F4A0PITB**。 + +为了最大限度的方便开发者和爱好者，该核心板通过排针将所有可用的IO（输入/输出）引脚都引出，这样大家就可以轻松地连接各种外部模块和设备，无需进行复杂的焊接工作。这一特点特别适合那些需要快速原型制作和迭代的场合，如学生电子竞赛、创客活动以及个人DIY项目。 + +此外，这款核心板的设计考虑到了大家在电子竞赛中对于稳定性和可靠性的需求，以及在小型项目开发中对低成本的追求。具体请看硬件设计手册。 + +![[(lckfb.com)](https://lckfb.com/project/detail/lckfb-lspi-skystar-stm32f407vet6-lite?param=baseInfo)](figures/board.png) + +## 资料罗列： + +* [硬件开源地址](https://oshwhub.com/li-chuang-kai-fa-ban/li-chuang-liang-shan-pai-tian-kong-xing-kai-fa-ban) +* [硬件文档](https://lceda001.feishu.cn/wiki/D4cqwUkiTi6723knO2cczSThnYb) +* [入门手册](https://lceda001.feishu.cn/wiki/MqcKwTiJ2isvASk5xQzcdeUJnOb) +* [模块移植手册](https://lceda001.feishu.cn/wiki/RvtIwNuQ6iVhqvk4cELcr1vPncQ) +* [购买地址](https://lckfb.com/project/detail/lckfb-lspi-skystar-hc32f4a0pitb-lite?param=baseInfo) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------- | :----------: | :------------------------------ | +| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...81 | +| UART | 支持 | UART0 - UART6 | +| I2C | 支持 | I2C1 | +| SPI | 支持 | SPI0 -  SPI2 | +| ADC | 支持 | ADC0 - ADC2 | +| TF CARD | 支持 | SDIO1 | +| SPI FLASH | 暂不支持 | | +| **扩展模块** | **支持情况** | **备注** | +| 暂无 | 暂不支持 | 暂不支持 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)，上电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.2.0 build Jun 28 2024 16:55:59 + 2006 - 2024 Copyright by RT-Thread team + +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口0的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [yuanzihao](https://github.com/zihao-yuan/), 邮箱：[y@yzh.email](mailto:y@yzh.email) \ No newline at end of file diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConscript b/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConstruct b/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConstruct new file mode 100644 index 0000000000..a0beabc624 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConstruct @@ -0,0 +1,62 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hc32_library = 'hc32f4a0_ddl' +rtconfig.BSP_LIBRARY_TYPE = hc32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript'))) + +objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/SConscript b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/SConscript new file mode 100644 index 0000000000..9bb9abae89 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/main.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/main.c new file mode 100644 index 0000000000..f68d3e69e8 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/main.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + * 2024-06-28 yuanzihao adaptation for SkyStar HC32F4A0PITB version + */ + +#include +#include +#include + +/* defined the LED_GREEN pin: PB2 */ +#define LED_GREEN_PIN GET_PIN(B, 2) + + +int main(void) +{ + /* set LED_GREEN_PIN pin mode to output */ + rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_GREEN_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_GREEN_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c new file mode 100644 index 0000000000..f89e5656dc --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-10-27 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include +#include +#include + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) + +/** + * @brief This thread is used to monitor whether XTAL32 is stable. + * This thread only runs once after the system starts. + * When stability is detected or 2s times out, the thread will end. + * (When a timeout occurs it will be prompted via rt_kprintf) + */ +void xtal32_fcm_thread_entry(void *parameter) +{ + stc_fcm_init_t stcFcmInit; + uint32_t u32TimeOut = 0UL; + uint32_t u32Time = 200UL; /* 200*10ms = 2s */ + + /* FCM config */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); + (void)FCM_StructInit(&stcFcmInit); + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + (void)FCM_Init(&stcFcmInit); + /* Enable FCM, to ensure xtal32 stable */ + FCM_Cmd(ENABLE); + + while (1) + { + if (SET == FCM_GetStatus(FCM_FLAG_END)) + { + FCM_ClearStatus(FCM_FLAG_END); + if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF))) + { + FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF); + } + else + { + (void)FCM_DeInit(); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + /* XTAL32 stabled */ + break; + } + } + u32TimeOut++; + if (u32TimeOut > u32Time) + { + (void)FCM_DeInit(); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + rt_kprintf("Error: XTAL32 still unstable, timeout.\n"); + break; + } + rt_thread_mdelay(10); + } +} + +int xtal32_fcm_thread_create(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL, + XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + rt_kprintf("create xtal32_fcm thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(xtal32_fcm_thread_create); + +#endif + + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig new file mode 100644 index 0000000000..bc1d72d5c1 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig @@ -0,0 +1,936 @@ +menu "Hardware Drivers Config" + +config SOC_HC32F4A0SI + bool + select SOC_SERIES_HC32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Drivers" + menuconfig BSP_USING_ON_CHIP_FLASH_CACHE + bool "Enable on-chip Flash Cache" + default y + if BSP_USING_ON_CHIP_FLASH_CACHE + config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE + bool "Enable on-chip Flash ICODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE + bool "Enable on-chip Flash DCODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH + bool "Enable on-chip Flash ICODE Prefetch" + default y + endif +endmenu + +menu "Onboard Peripheral Drivers" + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + select RT_LWIP_USING_HW_CHECKSUM + + if BSP_USING_ETH + choice + prompt "Select ETH PHY type" + default ETH_PHY_USING_RTL8201F + + config ETH_PHY_USING_RTL8201F + bool "ETH PHY USING RTL8201F" + select BSP_USING_I2C + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + + choice + prompt "Select ETH Communication Interface" + default ETH_INTERFACE_USING_MII + + config ETH_INTERFACE_USING_MII + bool "ETH Communication USING MII" + config ETH_INTERFACE_USING_RMII + bool "ETH Communication USING RMII" + endchoice + + menuconfig ETH_PHY_USING_INTERRUPT_MODE + bool "Enable ETH PHY interrupt mode" + default n + if ETH_PHY_USING_INTERRUPT_MODE + config ETH_PHY_INTERRUPT_PIN + int "ETH PHY Interrupt pin number" + range 1 176 + default 16 + endif + endif + + config BSP_USING_EXMC + bool "Enable EXMC" + default n + if BSP_USING_EXMC + choice + prompt "Using SDRAM or NAND" + default BSP_USING_NAND + + config BSP_USING_NAND + bool "Using NAND (MT29F2G08AB)" + select RT_USING_MTD_NAND + + config BSP_USING_SDRAM + bool "Using SDRAM (IS42S16400J7TLI)" + endchoice + endif + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (w25q64 spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select BSP_USING_ON_CHIP_FLASH + select RT_USING_SFUD + select RT_USING_DFS + select RT_USING_FAL + select RT_USING_MTD_NOR + default n + + config BSP_USING_TCA9539 + bool "Enable TCA9539" + select BSP_USING_I2C + select BSP_USING_I2C1 + default n + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + endif + + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + endif + + + menuconfig BSP_USING_UART8 + bool "Enable UART8" + default n + if BSP_USING_UART8 + config BSP_UART8_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART8_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART9 + bool "Enable UART9" + default n + if BSP_USING_UART9 + config BSP_UART9_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART9_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART10 + bool "Enable UART10" + default n + if BSP_USING_UART10 + config BSP_UART10_RX_BUFSIZE + int "Set UART10 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART10_TX_BUFSIZE + int "Set UART10 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + + if BSP_USING_I2C + menuconfig BSP_USING_I2C1_SW + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1_SW + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 51 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 90 + endif + endif + + if BSP_USING_I2C + config BSP_I2C_USING_DMA + bool + default n + config BSP_USING_I2C_HW + bool + default n + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool + default n + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool + default n + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + endif + + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool + default n + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + endif + + menuconfig BSP_USING_I2C4 + bool "Enable I2C4 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C4 + config BSP_I2C4_USING_DMA + bool + default n + config BSP_I2C4_TX_USING_DMA + bool "Enable I2C4 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C4_USING_DMA + config BSP_I2C4_RX_USING_DMA + bool "Enable I2C4 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C4_USING_DMA + endif + + menuconfig BSP_USING_I2C5 + bool "Enable I2C5 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C5 + config BSP_I2C5_USING_DMA + bool + default n + config BSP_I2C5_TX_USING_DMA + bool "Enable I2C5 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C5_USING_DMA + config BSP_I2C5_RX_USING_DMA + bool "Enable I2C5 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C5_USING_DMA + endif + + menuconfig BSP_USING_I2C6 + bool "Enable I2C6 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C6 + config BSP_I2C6_USING_DMA + bool + default n + config BSP_I2C6_TX_USING_DMA + bool "Enable I2C6 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C6_USING_DMA + config BSP_I2C6_RX_USING_DMA + bool "Enable I2C6 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C6_USING_DMA + endif + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_SPI_USING_DMA + bool + default n + + menuconfig BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + if BSP_USING_SPI1 + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + if BSP_USING_SPI2 + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + if BSP_USING_SPI3 + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI4 + bool "Enable SPI4 BUS" + default n + if BSP_USING_SPI4 + config BSP_SPI4_TX_USING_DMA + bool "Enable SPI4 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI4_RX_USING_DMA + bool "Enable SPI4 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI4_TX_USING_DMA + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "using adc1" + default n + config BSP_USING_ADC2 + bool "using adc2" + default n + config BSP_USING_ADC3 + bool "using adc3" + default n + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "using dac1" + default n + config BSP_USING_DAC2 + bool "using dac2" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_TCA9539 + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using can1" + default n + config BSP_USING_CAN2 + bool "using can2" + default n + endif + + menuconfig BSP_USING_WDT_TMR + bool "Enable Watchdog Timer" + default n + select RT_USING_WDT + if BSP_USING_WDT_TMR + choice + prompt "Select SWDT/WDT" + default BSP_USING_SWDT + + config BSP_USING_SWDT + bool "SWDT(3.72hour(max))" + config BSP_USING_WDT + bool "WDT(10.7s(max))" + endchoice + + config BSP_WDT_CONTINUE_COUNT + bool "Low Power Mode Keeps Counting" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_XTAL32 + + config BSP_RTC_USING_XTAL32 + bool "RTC USING XTAL32" + + config BSP_RTC_USING_LRC + bool "RTC USING LRC" + endchoice + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default n + select RT_USING_SDIO + if BSP_USING_SDIO + config BSP_USING_SDIO1 + bool "Enable SDIO1" + default n + config BSP_USING_SDIO2 + bool "Enable SDIO2" + default n + endif + + menuconfig BSP_USING_PM + bool "Enable PM" + default n + select RT_USING_PM + if BSP_USING_PM + choice + prompt "Select WKTM Clock Src" + default BSP_USING_WKTM_LRC + + config BSP_USING_WKTM_XTAL32 + bool "Using Xtal32" + config BSP_USING_WKTM_LRC + bool "Using LRC" + if BSP_RTC_USING_XTAL32 + config BSP_USING_WKTM_64HZ + bool "Using 64HZ(Note:must use XTAL32 and run RTC)" + endif + endchoice + endif + + menuconfig BSP_USING_HWCRYPTO + bool "Using Hardware Crypto drivers" + default n + select RT_USING_HWCRYPTO + if BSP_USING_HWCRYPTO + config BSP_USING_UQID + bool "Enable UQID (unique id)" + default n + + config BSP_USING_RNG + bool "Using Hardware RNG" + default n + select RT_HWCRYPTO_USING_RNG + + config BSP_USING_CRC + bool "Using Hardware CRC" + default n + select RT_HWCRYPTO_USING_CRC + + config BSP_USING_AES + bool "Using Hardware AES" + default n + select RT_HWCRYPTO_USING_AES + if BSP_USING_AES + choice + prompt "Select AES Mode" + default BSP_USING_AES_ECB + + config BSP_USING_AES_ECB + bool "ECB mode" + select RT_HWCRYPTO_USING_AES_ECB + endchoice + endif + + config BSP_USING_HASH + bool "Using Hardware Hash" + default n + select RT_HWCRYPTO_USING_SHA2 + if BSP_USING_HASH + choice + prompt "Select Hash Mode" + default BSP_USING_SHA2_256 + + config BSP_USING_SHA2_256 + bool "SHA2_256 Mode" + select RT_HWCRYPTO_USING_SHA2_256 + endchoice + endif + + endif + + menuconfig BSP_USING_PWM + bool "Enable output PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM_TMRA + bool "Enable timerA output PWM" + default n + if BSP_USING_PWM_TMRA + menuconfig BSP_USING_PWM_TMRA_1 + bool "Enable timerA-1 output PWM" + default n + if BSP_USING_PWM_TMRA_1 + config BSP_USING_PWM_TMRA_1_CH1 + bool "Enable timerA-1 channel1" + default n + config BSP_USING_PWM_TMRA_1_CH2 + bool "Enable timerA-1 channel2" + default n + config BSP_USING_PWM_TMRA_1_CH3 + bool "Enable timerA-1 channel3" + default n + config BSP_USING_PWM_TMRA_1_CH4 + bool "Enable timerA-1 channel4" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR4 + bool "Enable timer4 output PWM" + default n + if BSP_USING_PWM_TMR4 + menuconfig BSP_USING_PWM_TMR4_1 + bool "Enable timer4-1 output PWM" + default n + if BSP_USING_PWM_TMR4_1 + config BSP_USING_PWM_TMR4_1_OUH + bool "Enable TMR4_1_OUH channel1" + default n + config BSP_USING_PWM_TMR4_1_OUL + bool "Enable TMR4_1_OUL channel2" + default n + config BSP_USING_PWM_TMR4_1_OVH + bool "Enable TMR4_1_OVH channel3" + default n + config BSP_USING_PWM_TMR4_1_OVL + bool "Enable TMR4_1_OVL channel4" + default n + config BSP_USING_PWM_TMR4_1_OWH + bool "Enable TMR4_1_OWH channel5" + default n + config BSP_USING_PWM_TMR4_1_OWL + bool "Enable TMR4_1_OWL channel6" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR6 + bool "Enable timer6 output PWM" + default n + if BSP_USING_PWM_TMR6 + menuconfig BSP_USING_PWM_TMR6_1 + bool "Enable timer6-1 output PWM" + default n + if BSP_USING_PWM_TMR6_1 + config BSP_USING_PWM_TMR6_1_A + bool "Enable TMR6_1_A channel1" + default n + config BSP_USING_PWM_TMR6_1_B + bool "Enable TMR6_1_B channel2" + default n + endif + endif + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + select RT_USING_USB_DEVICE if BSP_USING_USBD + select RT_USING_USB_HOST if BSP_USING_USBH + if BSP_USING_USB + choice + prompt "Select USB FS/HS Core" + default BSP_USING_USBFS + + config BSP_USING_USBFS + bool "Use USBFS Core" + + config BSP_USING_USBHS + bool "Use USBHS Core" + endchoice + + choice + depends on BSP_USING_USBHS + prompt "Select USB PHY" + default BSP_USING_USBHS_PHY_EMBED + + config BSP_USING_USBHS_PHY_EMBED + bool "Use USBHS Embedded PHY" + + config BSP_USING_USBHS_PHY_EXTERN + bool "Use USBHS External PHY" + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + + choice + prompt "Select USB Mode" + default BSP_USING_USBD + + config BSP_USING_USBD + bool "USB Device Mode" + + config BSP_USING_USBH + bool "USB Host Mode" + endchoice + + if BSP_USING_USBD + config BSP_USING_USBD_VBUS_SENSING + bool "Enable VBUS Sensing" + default y + endif + + if BSP_USING_USBH + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + endif + + menuconfig BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + if BSP_USING_QSPI + config BSP_QSPI_USING_DMA + bool "Enable QSPI DMA support" + default n + config BSP_QSPI_USING_SOFT_CS + bool "Enable QSPI Soft CS Pin" + default n + endif + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + menuconfig BSP_USING_TMRA_PULSE_ENCODER + bool "Use TIMERA As The Pulse Encoder" + default n + if BSP_USING_TMRA_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMRA_1 + bool "Use TIMERA_1 As The Pulse Encoder" + default n + endif + menuconfig BSP_USING_TMR6_PULSE_ENCODER + bool "Use TIMER6 As The Pulse Encoder" + default n + if BSP_USING_TMR6_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMR6_1 + bool "Use TIMER6_1 As The Pulse Encoder" + default n + endif + endif + + menuconfig BSP_USING_HWTIMER + bool "Enable Hw Timer" + default n + select RT_USING_HWTIMER + if BSP_USING_HWTIMER + config BSP_USING_TMRA_1 + bool "Use Timer_a1 As The Hw Timer" + default n + config BSP_USING_TMRA_2 + bool "Use Timer_a2 As The Hw Timer" + default n + config BSP_USING_TMRA_3 + bool "Use Timer_a3 As The Hw Timer" + default n + config BSP_USING_TMRA_4 + bool "Use Timer_a4 As The Hw Timer" + default n + config BSP_USING_TMRA_5 + bool "Use Timer_a5 As The Hw Timer" + default n + config BSP_USING_TMRA_6 + bool "Use Timer_a6 As The Hw Timer" + default n + config BSP_USING_TMRA_7 + bool "Use Timer_a7 As The Hw Timer" + default n + config BSP_USING_TMRA_8 + bool "Use Timer_a8 As The Hw Timer" + default n + config BSP_USING_TMRA_9 + bool "Use Timer_a9 As The Hw Timer" + default n + config BSP_USING_TMRA_10 + bool "Use Timer_a10 As The Hw Timer" + default n + config BSP_USING_TMRA_11 + bool "Use Timer_a11 As The Hw Timer" + default n + config BSP_USING_TMRA_12 + bool "Use Timer_a12 As The Hw Timer" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/SConscript b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/SConscript new file mode 100644 index 0000000000..266b108094 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/SConscript @@ -0,0 +1,38 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +if GetDepend(['BSP_USING_TCA9539']): + src += Glob('ports/tca9539.c') + +if GetDepend(['BSP_USING_SPI_FLASH']): + src += Glob('ports/drv_spi_flash.c') + +path = [cwd] +path += [cwd + '/ports'] +path += [cwd + '/config'] +path += [cwd + '/config/usb_config'] + +startup_path_prefix = SDK_LIB + +if rtconfig.PLATFORM in ['gcc']: + src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s'] + +CPPDEFINES = ['HC32F4A0', '__DEBUG'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c new file mode 100644 index 0000000000..9f23f247f3 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include "board.h" +#include "board_config.h" + +/* unlock/lock peripheral */ +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +/** + * @brief Switch clock stable time + * @note Approx. 30us + */ +#define CLK_SYSCLK_SW_STB (HCLK_VALUE / 50000UL) +/** + * @brief Clk delay function + * @param [in] u32Delay count + * @retval when switch clock source, should be delay some time to wait stable. + */ +static void CLK_Delay(uint32_t u32Delay) +{ + __IO uint32_t u32Timeout = 0UL; + + while (u32Timeout < u32Delay) + { + u32Timeout++; + } +} +#endif + +/** System Base Configuration +*/ +void SystemBase_Config(void) +{ +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE) + EFM_ICacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE) + EFM_DCacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH) + EFM_PrefetchCmd(ENABLE); +#endif + /* Reset the VBAT area */ + PWC_VBAT_Reset(); +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcPLLHInit; +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) + stc_clock_pllx_init_t stcPLLAInit; +#endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + stc_clock_xtal32_init_t stcXtal32Init; +#endif + + /* PCLK0, HCLK Max 240MHz */ + /* PCLK1, PCLK4 Max 120MHz */ + /* PCLK2, PCLK3 Max 60MHz */ + /* EX BUS Max 120MHz */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, \ + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \ + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \ + CLK_HCLK_DIV1)); + + GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); + (void)CLK_XtalStructInit(&stcXtalInit); + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + (void)CLK_PLLStructInit(&stcPLLHInit); + /* VCO = (8/1)*120 = 960MHz*/ + stcPLLHInit.u8PLLState = CLK_PLL_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcPLLHInit); + + /* Highspeed SRAM set to 0 Read/Write wait cycle */ + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0); + /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */ + SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1); + /* 0-wait @ 40MHz */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5); + /* 4 cycles for 200 ~ 250MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT4); + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) + /* PLLX for USB */ + (void)CLK_PLLxStructInit(&stcPLLAInit); + /* VCO = (8/2)*120 = 480MHz*/ + stcPLLAInit.u8PLLState = CLK_PLL_ON; + stcPLLAInit.PLLCFGR = 0UL; + stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL; + (void)CLK_PLLxInit(&stcPLLAInit); +#endif + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + /* Xtal32 config */ + GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); + (void)CLK_Xtal32StructInit(&stcXtal32Init); + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; + (void)CLK_Xtal32Init(&stcXtal32Init); +#endif +} + +/** Peripheral Clock Configuration +*/ +void PeripheralClock_Config(void) +{ +#if defined(BSP_USING_CAN1) + CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); +#endif +#if defined(BSP_USING_CAN2) + CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6); +#endif + +#if defined(RT_USING_ADC) + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) + CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP); + /* Wait stable here, since the current DDL API does not include this */ + CLK_Delay(CLK_SYSCLK_SW_STB); +#endif +} + +/** Peripheral Registers Unlock +*/ +void PeripheralRegister_Unlock(void) +{ + LL_PERIPH_WE(EXAMPLE_PERIPH_WE); +} + +/*@}*/ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h new file mode 100644 index 0000000000..160f52c805 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ll.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024) +#define HC32_FLASH_SIZE (2 * 1024 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) + +#define HC32_SRAM_SIZE (512) +#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION +extern int Image$$RW_IRAM2$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END HC32_SRAM_END + +void PeripheralRegister_Unlock(void); +void PeripheralClock_Config(void); +void SystemBase_Config(void); +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c new file mode 100644 index 0000000000..1724fe292f --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c @@ -0,0 +1,701 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include "board_config.h" +#include "tca9539.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)CM_USART1: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC); + GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART6) + case (rt_uint32_t)CM_USART6: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC); + GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_I2C) +rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + (void)GPIO_StructInit(&stcGpioInit); + + switch ((rt_uint32_t)I2Cx) + { +#if defined(BSP_USING_I2C1) + case (rt_uint32_t)CM_I2C1: + /* Configure I2C1 SDA/SCL pin. */ + GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC); + GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(RT_USING_ADC) +rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)ADCx) + { +#if defined(BSP_USING_ADC1) + case (rt_uint32_t)CM_ADC1: + (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC2) + case (rt_uint32_t)CM_ADC2: + (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC3) + case (rt_uint32_t)CM_ADC3: + (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_DAC) +rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)DACx) + { +#if defined(BSP_USING_DAC1) + case (rt_uint32_t)CM_DAC1: + (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_DAC2) + case (rt_uint32_t)CM_DAC2: + (void)GPIO_Init(DAC2_CH1_PORT, DAC2_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC2_CH2_PORT, DAC2_CH2_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_CAN) +void CanPhyEnable(void) +{ + TCA9539_WritePin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_DIR_OUT); +} +rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)CANx) + { +#if defined(BSP_USING_CAN1) + case (rt_uint32_t)CM_CAN1: + GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC); + GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC); + break; +#endif +#if defined(BSP_USING_CAN2) + case (rt_uint32_t)CM_CAN2: + GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC); + GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + + +#if defined (RT_USING_SPI) +rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) +{ + rt_err_t result = RT_EOK; +#if defined(BSP_USING_SPI1) + stc_gpio_init_t stcGpioInit; +#endif + + switch ((rt_uint32_t)CM_SPIx) + { +#if defined(BSP_USING_SPI1) + case (rt_uint32_t)CM_SPI1: + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_SET; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); + GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); + GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_ETH) +/* PHY hardware reset time */ +#define PHY_HW_RST_DELAY (0x40U) + +rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) +{ + TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + return RT_EOK; +} + +rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx) +{ +#if defined(ETH_INTERFACE_USING_RMII) + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); + GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); + GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); + GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC); + GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); + GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); + GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); +#else + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_MII_TX_CLK_PORT, ETH_MII_TX_CLK_PIN, ETH_MII_TX_CLK_FUNC); + GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC); + GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC); + GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC); + GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC); + GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC); + GPIO_SetFunc(ETH_MII_RX_CLK_PORT, ETH_MII_RX_CLK_PIN, ETH_MII_RX_CLK_FUNC); + GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC); + GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC); + GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC); + GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC); + GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC); + GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC); + GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC); + GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC); +#endif + return RT_EOK; +} +#endif + +#if defined (RT_USING_SDIO) +rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + switch ((rt_uint32_t)SDIOCx) + { +#if defined(BSP_USING_SDIO1) + case (rt_uint32_t)CM_SDIOC1: + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); + + GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); + GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC); + GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); + GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); + GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); + GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PWM) +#if defined(BSP_USING_PWM_TMRA) +rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PWM_TMRA_1) + case (rt_uint32_t)CM_TMRA_1: +#ifdef BSP_USING_PWM_TMRA_1_CH1 + GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH2 + GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH3 + GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH4 + GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR4) +rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR4x) + { +#if defined(BSP_USING_PWM_TMR4_1) + case (rt_uint32_t)CM_TMR4_1: +#ifdef BSP_USING_PWM_TMR4_1_OUH + GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OUL + GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVH + GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVL + GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWH + GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWL + GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR6) +rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR6x) + { +#if defined(BSP_USING_PWM_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: +#ifdef BSP_USING_PWM_TMR6_1_A + GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR6_1_B + GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif +#endif + +#if defined (BSP_USING_SDRAM) +rt_err_t rt_hw_board_sdram_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + /* DMC_CKE */ + (void)GPIO_Init(SDRAM_CKE_PORT, SDRAM_CKE_PIN, &stcGpioInit); + /* DMC_CLK */ + (void)GPIO_Init(SDRAM_CLK_PORT, SDRAM_CLK_PIN, &stcGpioInit); + /* DMC_LDQM && DMC_UDQM */ + (void)GPIO_Init(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, &stcGpioInit); + /* DMC_BA[0:1] */ + (void)GPIO_Init(SDRAM_BA0_PORT, SDRAM_BA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_BA1_PORT, SDRAM_BA1_PIN, &stcGpioInit); + /* DMC_CAS && DMC_RAS */ + (void)GPIO_Init(SDRAM_CAS_PORT, SDRAM_CAS_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_RAS_PORT, SDRAM_RAS_PIN, &stcGpioInit); + /* DMC_WE */ + (void)GPIO_Init(SDRAM_WE_PORT, SDRAM_WE_PIN, &stcGpioInit); + /* DMC_DATA[0:15] */ + (void)GPIO_Init(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, &stcGpioInit); + /* DMC_ADD[0:11]*/ + (void)GPIO_Init(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* DMC_CKE */ + GPIO_SetFunc(SDRAM_CKE_PORT, SDRAM_CKE_PIN, SDRAM_CKE_FUNC); + /* DMC_CLK */ + GPIO_SetFunc(SDRAM_CLK_PORT, SDRAM_CLK_PIN, SDRAM_CLK_FUNC); + /* DMC_LDQM && DMC_UDQM */ + GPIO_SetFunc(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, SDRAM_DQM0_FUNC); + GPIO_SetFunc(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, SDRAM_DQM1_FUNC); + /* DMC_BA[0:1] */ + GPIO_SetFunc(SDRAM_BA0_PORT, SDRAM_BA0_PIN, SDRAM_BA0_FUNC); + GPIO_SetFunc(SDRAM_BA1_PORT, SDRAM_BA1_PIN, SDRAM_BA1_FUNC); + /* DMC_CS */ + GPIO_SetFunc(SDRAM_CS_PORT, SDRAM_CS_PIN, SDRAM_CS_FUNC); + /* DMC_CAS && DMC_RAS */ + GPIO_SetFunc(SDRAM_CAS_PORT, SDRAM_CAS_PIN, SDRAM_CAS_FUNC); + GPIO_SetFunc(SDRAM_RAS_PORT, SDRAM_RAS_PIN, SDRAM_RAS_FUNC); + /* DMC_WE */ + GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC); + /* DMC_DATA[0:15] */ + GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); + GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); + GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); + GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); + GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); + GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); + GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); + GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); + GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); + GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); + GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC); + GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC); + GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC); + GPIO_SetFunc(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, SDRAM_DATA13_FUNC); + GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC); + GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC); + /* DMC_ADD[0:11]*/ + GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); + GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); + GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); + GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); + GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); + GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); + GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); + GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); + GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); + GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); + GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC); + GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC); + + return result; +} +#endif + +#ifdef RT_USING_PM +void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) +{ + switch (run_mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + break; + + case PM_RUN_MODE_LOW_SPEED: + /* Ensure that system clock less than 8M */ + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL); + + default: + break; + } +} +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +rt_err_t rt_hw_usb_board_init(void) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); +#if defined(BSP_USING_USBFS) + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD) + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ +#endif +#if defined(BSP_USING_USBH) + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ +#endif +#elif defined(BSP_USING_USBHS) +#if defined(BSP_USING_USBHS_PHY_EMBED) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD) + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); +#endif +#if defined(BSP_USING_USBH) + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ +#endif +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + +#endif + return RT_EOK; +} +#endif + +#if defined(BSP_USING_QSPI) +rt_err_t rt_hw_qspi_board_init(void) +{ + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; +#ifndef BSP_QSPI_USING_SOFT_CS + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); +#endif + (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC); + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmra_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined (BSP_USING_NAND) +rt_err_t rt_hw_board_nand_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + /* NFC_CE */ + (void)GPIO_Init(NAND_CE_PORT, NAND_CE_PIN, &stcGpioInit); + /* NFC_RE */ + (void)GPIO_Init(NAND_RE_PORT, NAND_RE_PIN, &stcGpioInit); + /* NFC_WE */ + (void)GPIO_Init(NAND_WE_PORT, NAND_WE_PIN, &stcGpioInit); + /* NFC_CLE */ + (void)GPIO_Init(NAND_CLE_PORT, NAND_CLE_PIN, &stcGpioInit); + /* NFC_ALE */ + (void)GPIO_Init(NAND_ALE_PORT, NAND_ALE_PIN, &stcGpioInit); + /* NFC_WP */ + (void)GPIO_Init(NAND_WP_PORT, NAND_WP_PIN, &stcGpioInit); + GPIO_SetPins(NAND_WP_PORT, NAND_WP_PIN); + + /* NFC_DATA[0:7] */ + (void)GPIO_Init(NAND_DATA0_PORT, NAND_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA1_PORT, NAND_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA2_PORT, NAND_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA3_PORT, NAND_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA4_PORT, NAND_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA5_PORT, NAND_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA6_PORT, NAND_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA7_PORT, NAND_DATA7_PIN, &stcGpioInit); + /* NFC_RB */ + (void)GPIO_Init(NAND_RB_PORT, NAND_RB_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* NFC_CE */ + GPIO_SetFunc(NAND_CE_PORT, NAND_CE_PIN, NAND_CE_FUNC); + /* NFC_RE */ + GPIO_SetFunc(NAND_RE_PORT, NAND_RE_PIN, NAND_RE_FUNC); + /* NFC_WE */ + GPIO_SetFunc(NAND_WE_PORT, NAND_WE_PIN, NAND_WE_FUNC); + /* NFC_CLE */ + GPIO_SetFunc(NAND_CLE_PORT, NAND_CLE_PIN, NAND_CLE_FUNC); + /* NFC_ALE */ + GPIO_SetFunc(NAND_ALE_PORT, NAND_ALE_PIN, NAND_ALE_FUNC); + /* NFC_WP */ + GPIO_SetFunc(NAND_WP_PORT, NAND_WP_PIN, NAND_WP_FUNC); + /* NFC_RB */ + GPIO_SetFunc(NAND_RB_PORT, NAND_RB_PIN, NAND_RB_FUNC); + /* NFC_DATA[0:7] */ + GPIO_SetFunc(NAND_DATA0_PORT, NAND_DATA0_PIN, NAND_DATA0_FUNC); + GPIO_SetFunc(NAND_DATA1_PORT, NAND_DATA1_PIN, NAND_DATA1_FUNC); + GPIO_SetFunc(NAND_DATA2_PORT, NAND_DATA2_PIN, NAND_DATA2_FUNC); + GPIO_SetFunc(NAND_DATA3_PORT, NAND_DATA3_PIN, NAND_DATA3_FUNC); + GPIO_SetFunc(NAND_DATA4_PORT, NAND_DATA4_PIN, NAND_DATA4_FUNC); + GPIO_SetFunc(NAND_DATA5_PORT, NAND_DATA5_PIN, NAND_DATA5_FUNC); + GPIO_SetFunc(NAND_DATA6_PORT, NAND_DATA6_PIN, NAND_DATA6_FUNC); + GPIO_SetFunc(NAND_DATA7_PORT, NAND_DATA7_PIN, NAND_DATA7_FUNC); + + return result; +} +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h new file mode 100644 index 0000000000..13a33752bf --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h @@ -0,0 +1,678 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ll.h" +#include "drv_config.h" + + +/************************* XTAL port **********************/ +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_IN_PIN (GPIO_PIN_01) +#define XTAL_OUT_PIN (GPIO_PIN_00) + +/************************ USART port **********************/ +#if defined(BSP_USING_UART1) + #define USART1_RX_PORT (GPIO_PORT_A) + #define USART1_RX_PIN (GPIO_PIN_10) + #define USART1_RX_FUNC (GPIO_FUNC_20) + + #define USART1_TX_PORT (GPIO_PORT_A) + #define USART1_TX_PIN (GPIO_PIN_09) + #define USART1_TX_FUNC (GPIO_FUNC_20) +#endif + +#if defined(BSP_USING_UART6) + #define USART6_RX_PORT (GPIO_PORT_H) + #define USART6_RX_PIN (GPIO_PIN_06) + #define USART6_RX_FUNC (GPIO_FUNC_37) + + #define USART6_TX_PORT (GPIO_PORT_E) + #define USART6_TX_PIN (GPIO_PIN_06) + #define USART6_TX_FUNC (GPIO_FUNC_36) +#endif + +/************************ I2C port **********************/ +#if defined(BSP_USING_I2C1) + #define I2C1_SDA_PORT (GPIO_PORT_F) + #define I2C1_SDA_PIN (GPIO_PIN_10) + #define I2C1_SDA_FUNC (GPIO_FUNC_48) + + #define I2C1_SCL_PORT (GPIO_PORT_D) + #define I2C1_SCL_PIN (GPIO_PIN_03) + #define I2C1_SCL_FUNC (GPIO_FUNC_49) +#endif + +/*********** ADC configure *********/ +#if defined(BSP_USING_ADC1) + #define ADC1_CH_PORT (GPIO_PORT_C) + #define ADC1_CH_PIN (GPIO_PIN_00) +#endif + +#if defined(BSP_USING_ADC2) + #define ADC2_CH_PORT (GPIO_PORT_C) + #define ADC2_CH_PIN (GPIO_PIN_01) +#endif + +#if defined(BSP_USING_ADC3) + #define ADC3_CH_PORT (GPIO_PORT_C) + #define ADC3_CH_PIN (GPIO_PIN_02) +#endif + +/*********** DAC configure *********/ +#if defined(BSP_USING_DAC1) + #define DAC1_CH1_PORT (GPIO_PORT_A) + #define DAC1_CH1_PIN (GPIO_PIN_04) + #define DAC1_CH2_PORT (GPIO_PORT_A) + #define DAC1_CH2_PIN (GPIO_PIN_05) +#endif + +#if defined(BSP_USING_DAC2) + #define DAC2_CH1_PORT (GPIO_PORT_C) + #define DAC2_CH1_PIN (GPIO_PIN_04) + #define DAC2_CH2_PORT (GPIO_PORT_C) + #define DAC2_CH2_PIN (GPIO_PIN_05) +#endif + +/*********** CAN configure *********/ +#if defined(BSP_USING_CAN1) + #define CAN1_TX_PORT (GPIO_PORT_D) + #define CAN1_TX_PIN (GPIO_PIN_05) + #define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) + + #define CAN1_RX_PORT (GPIO_PORT_D) + #define CAN1_RX_PIN (GPIO_PIN_04) + #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) +#endif + +#if defined(BSP_USING_CAN2) + #define CAN2_TX_PORT (GPIO_PORT_D) + #define CAN2_TX_PIN (GPIO_PIN_07) + #define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) + + #define CAN2_RX_PORT (GPIO_PORT_D) + #define CAN2_RX_PIN (GPIO_PIN_06) + #define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) +#endif + +/************************* SPI port ***********************/ +#if defined(BSP_USING_SPI1) + #define SPI1_CS_PORT (GPIO_PORT_A) + #define SPI1_CS_PIN (GPIO_PIN_04) + + #define SPI1_SCK_PORT (GPIO_PORT_A) + #define SPI1_SCK_PIN (GPIO_PIN_05) + #define SPI1_SCK_FUNC (GPIO_FUNC_40) + + #define SPI1_MOSI_PORT (GPIO_PORT_A) + #define SPI1_MOSI_PIN (GPIO_PIN_07) + #define SPI1_MOSI_FUNC (GPIO_FUNC_41) + + #define SPI1_MISO_PORT (GPIO_PORT_A) + #define SPI1_MISO_PIN (GPIO_PIN_06) + #define SPI1_MISO_FUNC (GPIO_FUNC_42) + + #define SPI1_WP_PORT (GPIO_PORT_B) + #define SPI1_WP_PIN (GPIO_PIN_10) + + #define SPI1_HOLD_PORT (GPIO_PORT_B) + #define SPI1_HOLD_PIN (GPIO_PIN_02) +#endif + +/************************* ETH port ***********************/ + +#if defined(BSP_USING_ETH) + #if defined(ETH_INTERFACE_USING_RMII) + #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) + #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) + #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + + #define ETH_SMI_MDC_PORT (GPIO_PORT_C) + #define ETH_SMI_MDC_PIN (GPIO_PIN_01) + #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) + #define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) + #define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_TXD0_PORT (GPIO_PORT_G) + #define ETH_RMII_TXD0_PIN (GPIO_PIN_13) + #define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_TXD1_PORT (GPIO_PORT_G) + #define ETH_RMII_TXD1_PIN (GPIO_PIN_14) + #define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) + #define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) + #define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) + #define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) + #define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_RXD0_PORT (GPIO_PORT_C) + #define ETH_RMII_RXD0_PIN (GPIO_PIN_04) + #define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) + + #define ETH_RMII_RXD1_PORT (GPIO_PORT_C) + #define ETH_RMII_RXD1_PIN (GPIO_PIN_05) + #define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) + #else + #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) + #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) + #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + + #define ETH_SMI_MDC_PORT (GPIO_PORT_C) + #define ETH_SMI_MDC_PIN (GPIO_PIN_01) + #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TX_CLK_PORT (GPIO_PORT_B) + #define ETH_MII_TX_CLK_PIN (GPIO_PIN_06) + #define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TX_EN_PORT (GPIO_PORT_G) + #define ETH_MII_TX_EN_PIN (GPIO_PIN_11) + #define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TXD0_PORT (GPIO_PORT_G) + #define ETH_MII_TXD0_PIN (GPIO_PIN_13) + #define ETH_MII_TXD0_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TXD1_PORT (GPIO_PORT_G) + #define ETH_MII_TXD1_PIN (GPIO_PIN_14) + #define ETH_MII_TXD1_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TXD2_PORT (GPIO_PORT_B) + #define ETH_MII_TXD2_PIN (GPIO_PIN_09) + #define ETH_MII_TXD2_FUNC (GPIO_FUNC_11) + + #define ETH_MII_TXD3_PORT (GPIO_PORT_B) + #define ETH_MII_TXD3_PIN (GPIO_PIN_08) + #define ETH_MII_TXD3_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RX_CLK_PORT (GPIO_PORT_A) + #define ETH_MII_RX_CLK_PIN (GPIO_PIN_01) + #define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RX_DV_PORT (GPIO_PORT_A) + #define ETH_MII_RX_DV_PIN (GPIO_PIN_07) + #define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RXD0_PORT (GPIO_PORT_C) + #define ETH_MII_RXD0_PIN (GPIO_PIN_04) + #define ETH_MII_RXD0_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RXD1_PORT (GPIO_PORT_C) + #define ETH_MII_RXD1_PIN (GPIO_PIN_05) + #define ETH_MII_RXD1_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RXD2_PORT (GPIO_PORT_B) + #define ETH_MII_RXD2_PIN (GPIO_PIN_00) + #define ETH_MII_RXD2_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RXD3_PORT (GPIO_PORT_B) + #define ETH_MII_RXD3_PIN (GPIO_PIN_01) + #define ETH_MII_RXD3_FUNC (GPIO_FUNC_11) + + #define ETH_MII_RX_ER_PORT (GPIO_PORT_I) + #define ETH_MII_RX_ER_PIN (GPIO_PIN_10) + #define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11) + + #define ETH_MII_CRS_PORT (GPIO_PORT_H) + #define ETH_MII_CRS_PIN (GPIO_PIN_02) + #define ETH_MII_CRS_FUNC (GPIO_FUNC_11) + + #define ETH_MII_COL_PORT (GPIO_PORT_H) + #define ETH_MII_COL_PIN (GPIO_PIN_03) + #define ETH_MII_COL_FUNC (GPIO_FUNC_11) + #endif +#endif + +/************************ NAND port **********************/ +#if defined(BSP_USING_NAND) + #define NAND_CE_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE0 */ + #define NAND_CE_PIN (GPIO_PIN_02) + #define NAND_CE_FUNC (GPIO_FUNC_12) + + #define NAND_RE_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ + #define NAND_RE_PIN (GPIO_PIN_11) + #define NAND_RE_FUNC (GPIO_FUNC_12) + + #define NAND_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ + #define NAND_WE_PIN (GPIO_PIN_00) + #define NAND_WE_FUNC (GPIO_FUNC_12) + + #define NAND_CLE_PORT (GPIO_PORT_I) /* PI12 - EXMC_CLE */ + #define NAND_CLE_PIN (GPIO_PIN_12) + #define NAND_CLE_FUNC (GPIO_FUNC_12) + + #define NAND_ALE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ + #define NAND_ALE_PIN (GPIO_PIN_03) + #define NAND_ALE_FUNC (GPIO_FUNC_12) + + #define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ + #define NAND_WP_PIN (GPIO_PIN_15) + #define NAND_WP_FUNC (GPIO_FUNC_12) + + #define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */ + #define NAND_RB_PIN (GPIO_PIN_06) + #define NAND_RB_FUNC (GPIO_FUNC_12) + + #define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ + #define NAND_DATA0_PIN (GPIO_PIN_14) + #define NAND_DATA0_FUNC (GPIO_FUNC_12) + #define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ + #define NAND_DATA1_PIN (GPIO_PIN_15) + #define NAND_DATA1_FUNC (GPIO_FUNC_12) + #define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ + #define NAND_DATA2_PIN (GPIO_PIN_00) + #define NAND_DATA2_FUNC (GPIO_FUNC_12) + #define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ + #define NAND_DATA3_PIN (GPIO_PIN_01) + #define NAND_DATA3_FUNC (GPIO_FUNC_12) + #define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ + #define NAND_DATA4_PIN (GPIO_PIN_07) + #define NAND_DATA4_FUNC (GPIO_FUNC_12) + #define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ + #define NAND_DATA5_PIN (GPIO_PIN_08) + #define NAND_DATA5_FUNC (GPIO_FUNC_12) + #define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ + #define NAND_DATA6_PIN (GPIO_PIN_09) + #define NAND_DATA6_FUNC (GPIO_FUNC_12) + #define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ + #define NAND_DATA7_PIN (GPIO_PIN_10) + #define NAND_DATA7_FUNC (GPIO_FUNC_12) +#endif + +/************************ SDIOC port **********************/ +#if defined(BSP_USING_SDIO1) + #define SDIOC1_CK_PORT (GPIO_PORT_C) + #define SDIOC1_CK_PIN (GPIO_PIN_12) + #define SDIOC1_CK_FUNC (GPIO_FUNC_9) + + #define SDIOC1_CMD_PORT (GPIO_PORT_D) + #define SDIOC1_CMD_PIN (GPIO_PIN_02) + #define SDIOC1_CMD_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D0_PORT (GPIO_PORT_C) + #define SDIOC1_D0_PIN (GPIO_PIN_08) + #define SDIOC1_D0_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D1_PORT (GPIO_PORT_C) + #define SDIOC1_D1_PIN (GPIO_PIN_09) + #define SDIOC1_D1_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D2_PORT (GPIO_PORT_C) + #define SDIOC1_D2_PIN (GPIO_PIN_10) + #define SDIOC1_D2_FUNC (GPIO_FUNC_9) + + #define SDIOC1_D3_PORT (GPIO_PORT_C) + #define SDIOC1_D3_PIN (GPIO_PIN_11) + #define SDIOC1_D3_FUNC (GPIO_FUNC_9) +#endif + +/************************ SDRAM port **********************/ +#if defined(BSP_USING_SDRAM) + #define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ + #define SDRAM_CKE_PIN (GPIO_PIN_03) + #define SDRAM_CKE_FUNC (GPIO_FUNC_12) + + #define SDRAM_CLK_PORT (GPIO_PORT_G) /* PD03 - EXMC_CLK */ + #define SDRAM_CLK_PIN (GPIO_PIN_08) + #define SDRAM_CLK_FUNC (GPIO_FUNC_12) + + #define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ + #define SDRAM_DQM0_PIN (GPIO_PIN_00) + #define SDRAM_DQM0_FUNC (GPIO_FUNC_12) + #define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ + #define SDRAM_DQM1_PIN (GPIO_PIN_01) + #define SDRAM_DQM1_FUNC (GPIO_FUNC_12) + + #define SDRAM_BA0_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16 */ + #define SDRAM_BA0_PIN (GPIO_PIN_11) + #define SDRAM_BA0_FUNC (GPIO_FUNC_12) + #define SDRAM_BA1_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17 */ + #define SDRAM_BA1_PIN (GPIO_PIN_12) + #define SDRAM_BA1_FUNC (GPIO_FUNC_12) + + #define SDRAM_CS_PORT (GPIO_PORT_G) /* PG09 - EXMC_CE1 */ + #define SDRAM_CS_PIN (GPIO_PIN_09) + #define SDRAM_CS_FUNC (GPIO_FUNC_12) + + #define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ + #define SDRAM_RAS_PIN (GPIO_PIN_11) + #define SDRAM_RAS_FUNC (GPIO_FUNC_12) + + #define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ + #define SDRAM_CAS_PIN (GPIO_PIN_15) + #define SDRAM_CAS_FUNC (GPIO_FUNC_12) + + #define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ + #define SDRAM_WE_PIN (GPIO_PIN_00) + #define SDRAM_WE_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ + #define SDRAM_ADD0_PIN (GPIO_PIN_00) + #define SDRAM_ADD0_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ + #define SDRAM_ADD1_PIN (GPIO_PIN_01) + #define SDRAM_ADD1_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ + #define SDRAM_ADD2_PIN (GPIO_PIN_02) + #define SDRAM_ADD2_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ + #define SDRAM_ADD3_PIN (GPIO_PIN_03) + #define SDRAM_ADD3_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ + #define SDRAM_ADD4_PIN (GPIO_PIN_04) + #define SDRAM_ADD4_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ + #define SDRAM_ADD5_PIN (GPIO_PIN_05) + #define SDRAM_ADD5_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ + #define SDRAM_ADD6_PIN (GPIO_PIN_12) + #define SDRAM_ADD6_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ + #define SDRAM_ADD7_PIN (GPIO_PIN_13) + #define SDRAM_ADD7_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ + #define SDRAM_ADD8_PIN (GPIO_PIN_14) + #define SDRAM_ADD8_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ + #define SDRAM_ADD9_PIN (GPIO_PIN_15) + #define SDRAM_ADD9_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ + #define SDRAM_ADD10_PIN (GPIO_PIN_00) + #define SDRAM_ADD10_FUNC (GPIO_FUNC_12) + + #define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ + #define SDRAM_ADD11_PIN (GPIO_PIN_01) + #define SDRAM_ADD11_FUNC (GPIO_FUNC_12) + + #define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ + #define SDRAM_DATA0_PIN (GPIO_PIN_14) + #define SDRAM_DATA0_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ + #define SDRAM_DATA1_PIN (GPIO_PIN_15) + #define SDRAM_DATA1_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ + #define SDRAM_DATA2_PIN (GPIO_PIN_00) + #define SDRAM_DATA2_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ + #define SDRAM_DATA3_PIN (GPIO_PIN_01) + #define SDRAM_DATA3_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ + #define SDRAM_DATA4_PIN (GPIO_PIN_07) + #define SDRAM_DATA4_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ + #define SDRAM_DATA5_PIN (GPIO_PIN_08) + #define SDRAM_DATA5_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ + #define SDRAM_DATA6_PIN (GPIO_PIN_09) + #define SDRAM_DATA6_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ + #define SDRAM_DATA7_PIN (GPIO_PIN_10) + #define SDRAM_DATA7_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ + #define SDRAM_DATA8_PIN (GPIO_PIN_11) + #define SDRAM_DATA8_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ + #define SDRAM_DATA9_PIN (GPIO_PIN_12) + #define SDRAM_DATA9_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ + #define SDRAM_DATA10_PIN (GPIO_PIN_13) + #define SDRAM_DATA10_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ + #define SDRAM_DATA11_PIN (GPIO_PIN_14) + #define SDRAM_DATA11_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ + #define SDRAM_DATA12_PIN (GPIO_PIN_15) + #define SDRAM_DATA12_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ + #define SDRAM_DATA13_PIN (GPIO_PIN_08) + #define SDRAM_DATA13_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ + #define SDRAM_DATA14_PIN (GPIO_PIN_09) + #define SDRAM_DATA14_FUNC (GPIO_FUNC_12) + #define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ + #define SDRAM_DATA15_PIN (GPIO_PIN_10) + #define SDRAM_DATA15_FUNC (GPIO_FUNC_12) +#endif + +/************************ RTC/PM *****************************/ +#if defined(BSP_USING_RTC) || defined(RT_USING_PM) + #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + #define XTAL32_PORT (GPIO_PORT_C) + #define XTAL32_IN_PIN (GPIO_PIN_15) + #define XTAL32_OUT_PIN (GPIO_PIN_14) + #endif +#endif + +#if defined(RT_USING_PWM) + /*********** PWM_TMRA configure *********/ + #if defined(BSP_USING_PWM_TMRA_1) + #if defined(BSP_USING_PWM_TMRA_1_CH1) + #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) + #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH2) + #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) + #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH3) + #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) + #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH4) + #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) + #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) + #endif + #endif + + /*********** PWM_TMR4 configure *********/ + #if defined(BSP_USING_PWM_TMR4_1) + #if defined(BSP_USING_PWM_TMR4_1_OUH) + #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) + #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OUL) + #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) + #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVH) + #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) + #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVL) + #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) + #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWH) + #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) + #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWL) + #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) + #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) + #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) + #endif + #endif + + /*********** PWM_TMR6 configure *********/ + #if defined(BSP_USING_PWM_TMR6_1) + #if defined(BSP_USING_PWM_TMR6_1_A) + #define PWM_TMR6_1_A_PORT (GPIO_PORT_F) + #define PWM_TMR6_1_A_PIN (GPIO_PIN_13) + #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #endif + #if defined(BSP_USING_PWM_TMR6_1_B) + #define PWM_TMR6_1_B_PORT (GPIO_PORT_F) + #define PWM_TMR6_1_B_PIN (GPIO_PIN_14) + #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif + #endif + +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) + #if defined(BSP_USING_USBFS) + /* USBFS Core*/ + #define USBF_DP_PORT (GPIO_PORT_A) + #define USBF_DP_PIN (GPIO_PIN_12) + #define USBF_DP_FUNC (GPIO_FUNC_10) + #define USBF_DM_PORT (GPIO_PORT_A) + #define USBF_DM_PIN (GPIO_PIN_11) + #define USBF_DM_FUNC (GPIO_FUNC_10) + #define USBF_VBUS_PORT (GPIO_PORT_A) + #define USBF_VBUS_PIN (GPIO_PIN_09) + #define USBF_VBUS_FUNC (GPIO_FUNC_10) + #define USBF_DRVVBUS_PORT (GPIO_PORT_C) + #define USBF_DRVVBUS_PIN (GPIO_PIN_09) + #define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) + #elif defined(BSP_USING_USBHS) + /* USBHS Core*/ + #if defined(BSP_USING_USBHS_PHY_EMBED) + #define USBH_DP_PORT (GPIO_PORT_B) + #define USBH_DP_PIN (GPIO_PIN_15) + #define USBH_DP_FUNC (GPIO_FUNC_10) + #define USBH_DM_PORT (GPIO_PORT_B) + #define USBH_DM_PIN (GPIO_PIN_14) + #define USBH_DM_FUNC (GPIO_FUNC_10) + #define USBH_VBUS_PORT (GPIO_PORT_B) + #define USBH_VBUS_PIN (GPIO_PIN_13) + #define USBH_VBUS_FUNC (GPIO_FUNC_12) + #define USBH_DRVVBUS_PORT (GPIO_PORT_B) + #define USBH_DRVVBUS_PIN (GPIO_PIN_11) + #define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) + #else + /* USBHS Core, external PHY */ + #define USBH_ULPI_CLK_PORT (GPIO_PORT_E) + #define USBH_ULPI_CLK_PIN (GPIO_PIN_12) + #define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_DIR_PORT (GPIO_PORT_C) + #define USBH_ULPI_DIR_PIN (GPIO_PIN_02) + #define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_NXT_PORT (GPIO_PORT_C) + #define USBH_ULPI_NXT_PIN (GPIO_PIN_03) + #define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_STP_PORT (GPIO_PORT_C) + #define USBH_ULPI_STP_PIN (GPIO_PIN_00) + #define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D0_PORT (GPIO_PORT_E) + #define USBH_ULPI_D0_PIN (GPIO_PIN_13) + #define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D1_PORT (GPIO_PORT_E) + #define USBH_ULPI_D1_PIN (GPIO_PIN_14) + #define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D2_PORT (GPIO_PORT_E) + #define USBH_ULPI_D2_PIN (GPIO_PIN_15) + #define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D3_PORT (GPIO_PORT_B) + #define USBH_ULPI_D3_PIN (GPIO_PIN_10) + #define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D4_PORT (GPIO_PORT_B) + #define USBH_ULPI_D4_PIN (GPIO_PIN_11) + #define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D5_PORT (GPIO_PORT_B) + #define USBH_ULPI_D5_PIN (GPIO_PIN_12) + #define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D6_PORT (GPIO_PORT_B) + #define USBH_ULPI_D6_PIN (GPIO_PIN_13) + #define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) + #define USBH_ULPI_D7_PORT (GPIO_PORT_E) + #define USBH_ULPI_D7_PIN (GPIO_PIN_11) + #define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) + /* 3300 reset */ + #define USB_3300_RESET_PORT (EIO_PORT1) + #define USB_3300_RESET_PIN (EIO_USB3300_RST) + #endif + #endif +#endif + +#if defined(BSP_USING_QSPI) + #ifndef BSP_QSPI_USING_SOFT_CS + /* QSSN */ + #define QSPI_FLASH_CS_PORT (GPIO_PORT_C) + #define QSPI_FLASH_CS_PIN (GPIO_PIN_07) + #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) + #endif + /* QSCK */ + #define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) + #define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) + #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) + /* QSIO0 */ + #define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) + #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) + /* QSIO1 */ + #define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) + #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) + /* QSIO2 */ + #define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) + #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) + /* QSIO3 */ + #define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) + #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) +#endif + +/*********** TMRA_PULSE_ENCODER configure *********/ +#if defined(RT_USING_PULSE_ENCODER) + #if defined(BSP_USING_TMRA_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) + #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) + #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) + #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) + #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + #endif /* BSP_USING_TMRA_PULSE_ENCODER */ + + #if defined(BSP_USING_TMR6_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) + #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) + #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) + #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) + #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#endif /* RT_USING_PULSE_ENCODER */ + +#endif + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h new file mode 100644 index 0000000000..9374d2e9ab --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_INIT_PARAMS +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC1_INIT_PARAMS */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_INIT_PARAMS +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC2_INIT_PARAMS */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_INIT_PARAMS +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC3_INIT_PARAMS */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h new file mode 100644 index 0000000000..81ab895cfb --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_CAN1 +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#ifdef RT_CAN_USING_CANFD +#define CAN1_CANFD_MODE (CAN_FD_MD_ISO) +#endif +#define CAN1_NAME ("can1") +#ifndef CAN1_INIT_PARAMS +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN1_INIT_PARAMS */ +#endif /* BSP_USING_CAN1 */ + +#ifdef BSP_USING_CAN2 +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#ifdef RT_CAN_USING_CANFD +#define CAN2_CANFD_MODE (CAN_FD_MD_ISO) +#endif +#define CAN2_NAME ("can2") +#ifndef CAN2_INIT_PARAMS +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN2_INIT_PARAMS */ +#endif /* BSP_USING_CAN2 */ + +/* Bit time config + Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW. + + Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + TQ = u32Prescaler / CANClock. + Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + + The following bit time configures are based on CAN Clock 40M +*/ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h new file mode 100644 index 0000000000..f697eba881 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-05-12 CDT first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_INIT_PARAMS +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + } +#endif /* DAC1_INIT_PARAMS */ +#endif /* BSP_USING_DAC1 */ + +#ifdef BSP_USING_DAC2 +#ifndef DAC2_INIT_PARAMS +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ + } +#endif /* DAC2_INIT_PARAMS */ +#endif /* BSP_USING_DAC2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h new file mode 100644 index 0000000000..9cd020ad93 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h @@ -0,0 +1,372 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 ch0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) +#define SDIO1_RX_DMA_INSTANCE CM_DMA1 +#define SDIO1_RX_DMA_CHANNEL DMA_CH0 +#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#endif + +/* DMA1 ch1 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) +#define SDIO1_TX_DMA_INSTANCE CM_DMA1 +#define SDIO1_TX_DMA_CHANNEL DMA_CH1 +#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#endif + +/* DMA1 ch2 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) +#define SDIO2_RX_DMA_INSTANCE CM_DMA1 +#define SDIO2_RX_DMA_CHANNEL DMA_CH2 +#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#endif + +/* DMA1 ch3 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) +#define SDIO2_TX_DMA_INSTANCE CM_DMA1 +#define SDIO2_TX_DMA_CHANNEL DMA_CH3 +#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_INSTANCE CM_DMA1 +#define QSPI_DMA_CHANNEL DMA_CH3 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#endif + +/* DMA1 ch4 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH4 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) +#define I2C3_TX_DMA_INSTANCE CM_DMA1 +#define I2C3_TX_DMA_CHANNEL DMA_CH4 +#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 +#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#endif + +/* DMA1 ch5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH5 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) +#define I2C3_RX_DMA_INSTANCE CM_DMA1 +#define I2C3_RX_DMA_CHANNEL DMA_CH5 +#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 +#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#endif + +/* DMA1 ch6 */ +#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH6 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE) +#define I2C4_TX_DMA_INSTANCE CM_DMA1 +#define I2C4_TX_DMA_CHANNEL DMA_CH6 +#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 +#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#endif + +/* DMA1 ch7 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH7 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE) +#define I2C4_RX_DMA_INSTANCE CM_DMA1 +#define I2C4_RX_DMA_CHANNEL DMA_CH7 +#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 +#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#endif + +/* DMA2 ch0 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE) +#define I2C5_TX_DMA_INSTANCE CM_DMA2 +#define I2C5_TX_DMA_CHANNEL DMA_CH0 +#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 +#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#endif + +/* DMA2 ch1 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE) +#define I2C5_RX_DMA_INSTANCE CM_DMA2 +#define I2C5_RX_DMA_CHANNEL DMA_CH1 +#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 +#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#endif + +/* DMA2 ch2 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE) +#define I2C6_TX_DMA_INSTANCE CM_DMA2 +#define I2C6_TX_DMA_CHANNEL DMA_CH2 +#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 +#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#endif + +/* DMA2 ch3 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE) +#define I2C6_RX_DMA_INSTANCE CM_DMA2 +#define I2C6_RX_DMA_CHANNEL DMA_CH3 +#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 +#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#endif + +/* DMA2 ch4 */ +#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) +#define UART6_RX_DMA_INSTANCE CM_DMA2 +#define UART6_RX_DMA_CHANNEL DMA_CH4 +#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#endif + +/* DMA2 ch5 */ +#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) +#define UART6_TX_DMA_INSTANCE CM_DMA2 +#define UART6_TX_DMA_CHANNEL DMA_CH5 +#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#endif + +/* DMA2 ch6 */ +#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) +#define UART7_RX_DMA_INSTANCE CM_DMA2 +#define UART7_RX_DMA_CHANNEL DMA_CH6 +#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO +#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#endif + +/* DMA2 ch7 */ +#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_TX_DMA_INSTANCE CM_DMA2 +#define UART7_TX_DMA_CHANNEL DMA_CH7 +#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO +#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h new file mode 100644 index 0000000000..f28e5b19c7 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __ETH_CONFIG_H__ +#define __ETH_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_ETH) + +#ifndef ETH_IRQ_CONFIG +#define ETH_IRQ_CONFIG \ + { \ + .irq_num = BSP_ETH_IRQ_NUM, \ + .irq_prio = BSP_ETH_IRQ_PRIO, \ + .int_src = INT_SRC_ETH_GLB_INT, \ + } +#endif /* ETH_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __ETH_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h new file mode 100644 index 0000000000..ee17e1230d --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __GPIO_CONFIG_H__ +#define __GPIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(RT_USING_PIN) + +#ifndef EXTINT0_IRQ_CONFIG +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT1_IRQ_CONFIG +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT2_IRQ_CONFIG +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ + } +#endif /* EXTINT2_IRQ_CONFIG */ + +#ifndef EXTINT3_IRQ_CONFIG +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ + } +#endif /* EXTINT3_IRQ_CONFIG */ + +#ifndef EXTINT4_IRQ_CONFIG +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ + } +#endif /* EXTINT4_IRQ_CONFIG */ + +#ifndef EXTINT5_IRQ_CONFIG +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ + } +#endif /* EXTINT5_IRQ_CONFIG */ + +#ifndef EXTINT6_IRQ_CONFIG +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ + } +#endif /* EXTINT6_IRQ_CONFIG */ + +#ifndef EXTINT7_IRQ_CONFIG +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ + } +#endif /* EXTINT7_IRQ_CONFIG */ + +#ifndef EXTINT8_IRQ_CONFIG +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ + } +#endif /* EXTINT8_IRQ_CONFIG */ + +#ifndef EXTINT9_IRQ_CONFIG +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ + } +#endif /* EXTINT9_IRQ_CONFIG */ + +#ifndef EXTINT10_IRQ_CONFIG +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ + } +#endif /* EXTINT10_IRQ_CONFIG */ + +#ifndef EXTINT11_IRQ_CONFIG +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ + } +#endif /* EXTINT11_IRQ_CONFIG */ + +#ifndef EXTINT12_IRQ_CONFIG +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ + } +#endif /* EXTINT12_IRQ_CONFIG */ + +#ifndef EXTINT13_IRQ_CONFIG +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ + } +#endif /* EXTINT13_IRQ_CONFIG */ + +#ifndef EXTINT14_IRQ_CONFIG +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ + } +#endif /* EXTINT14_IRQ_CONFIG */ + +#ifndef EXTINT15_IRQ_CONFIG +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ + } +#endif /* EXTINT15_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h new file mode 100644 index 0000000000..57fe15696f --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h @@ -0,0 +1,331 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_I2C1) +#ifndef I2C1_CONFIG +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C1_CONFIG */ +#endif + +#if defined(BSP_I2C1_USING_DMA) +#ifndef I2C1_TX_DMA_CONFIG +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_TX_DMA_CONFIG */ + +#ifndef I2C1_RX_DMA_CONFIG +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_USING_DMA */ + +#if defined(BSP_USING_I2C2) +#ifndef I2C2_CONFIG +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C2_CONFIG */ + +#if defined(BSP_I2C2_USING_DMA) +#ifndef I2C2_TX_DMA_CONFIG +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_TX_DMA_CONFIG */ + +#ifndef I2C2_RX_DMA_CONFIG +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C3) +#ifndef I2C3_CONFIG +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C3_CONFIG */ + +#if defined(BSP_I2C3_USING_DMA) +#ifndef I2C3_TX_DMA_CONFIG +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_TX_DMA_CONFIG */ + +#ifndef I2C3_RX_DMA_CONFIG +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C4) +#ifndef I2C4_CONFIG +#define I2C4_CONFIG \ + { \ + .name = "i2c4", \ + .Instance = CM_I2C4, \ + .clock = FCG1_PERIPH_I2C4, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C4_CONFIG */ + +#if defined(BSP_I2C4_USING_DMA) +#ifndef I2C4_TX_DMA_CONFIG +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + .clock = I2C4_TX_DMA_CLOCK, \ + .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_TEI, \ + .flag = I2C4_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C4_TX_DMA_IRQn, \ + .irq_prio = I2C4_TX_DMA_INT_PRIO, \ + .int_src = I2C4_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C4_TX_DMA_CONFIG */ + +#ifndef I2C4_RX_DMA_CONFIG +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + .clock = I2C4_RX_DMA_CLOCK, \ + .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_RXI, \ + .flag = I2C4_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C4_RX_DMA_IRQn, \ + .irq_prio = I2C4_RX_DMA_INT_PRIO, \ + .int_src = I2C4_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C5) +#ifndef I2C5_CONFIG +#define I2C5_CONFIG \ + { \ + .name = "i2c5", \ + .Instance = CM_I2C5, \ + .clock = FCG1_PERIPH_I2C5, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C5_CONFIG */ + +#if defined(BSP_I2C5_USING_DMA) +#ifndef I2C5_TX_DMA_CONFIG +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .channel = I2C5_TX_DMA_CHANNEL, \ + .clock = I2C5_TX_DMA_CLOCK, \ + .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_TEI, \ + .flag = I2C5_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C5_TX_DMA_IRQn, \ + .irq_prio = I2C5_TX_DMA_INT_PRIO, \ + .int_src = I2C5_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C5_TX_DMA_CONFIG */ + +#ifndef I2C5_RX_DMA_CONFIG +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .channel = I2C5_RX_DMA_CHANNEL, \ + .clock = I2C5_RX_DMA_CLOCK, \ + .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_RXI, \ + .flag = I2C5_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C5_RX_DMA_IRQn, \ + .irq_prio = I2C5_RX_DMA_INT_PRIO, \ + .int_src = I2C5_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C5_RX_DMA_CONFIG */ +#endif /* BSP_I2C5_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C6) +#ifndef I2C6_CONFIG +#define I2C6_CONFIG \ + { \ + .name = "i2c6", \ + .Instance = CM_I2C6, \ + .clock = FCG1_PERIPH_I2C6, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C6_CONFIG */ + +#if defined(BSP_I2C6_USING_DMA) +#ifndef I2C6_TX_DMA_CONFIG +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .channel = I2C6_TX_DMA_CHANNEL, \ + .clock = I2C6_TX_DMA_CLOCK, \ + .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_TEI, \ + .flag = I2C6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C6_TX_DMA_IRQn, \ + .irq_prio = I2C6_TX_DMA_INT_PRIO, \ + .int_src = I2C6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C6_TX_DMA_CONFIG */ + +#ifndef I2C6_RX_DMA_CONFIG +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .channel = I2C6_RX_DMA_CHANNEL, \ + .clock = I2C6_RX_DMA_CLOCK, \ + .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_RXI, \ + .flag = I2C6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C6_RX_DMA_IRQn, \ + .irq_prio = I2C6_RX_DMA_INT_PRIO, \ + .int_src = I2C6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C6_RX_DMA_CONFIG */ +#endif /* BSP_I2C6_USING_DMA */ +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h new file mode 100644 index 0000000000..689d982537 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h @@ -0,0 +1,479 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __IRQ_CONFIG_H__ +#define __IRQ_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch4 */ +#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch6 */ +#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch7 */ +#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA2 ch0 */ +#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch1 */ +#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch2 */ +#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch3 */ +#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch4 */ +#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch5 */ +#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch6 */ +#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch7 */ +#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_USING_ETH) +#define BSP_ETH_IRQ_NUM INT104_IRQn +#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART1) +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT089_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT088_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART1_RX_USING_DMA) +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT091_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT090_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART2_RX_USING_DMA) +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT095_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT094_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT097_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT096_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RX_IRQ_NUM INT101_IRQn +#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_IRQ_NUM INT100_IRQn +#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn +#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RX_IRQ_NUM INT103_IRQn +#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_IRQ_NUM INT102_IRQn +#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART6_RX_USING_DMA) +#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn +#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RX_IRQ_NUM INT107_IRQn +#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_IRQ_NUM INT106_IRQn +#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART7_RX_USING_DMA) +#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn +#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) +#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_SPI3) +#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI4) +#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART8) +#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn +#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RX_IRQ_NUM INT109_IRQn +#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_IRQ_NUM INT108_IRQn +#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(RT_USING_SERIAL_V2) +#define BSP_UART8_TX_CPLT_IRQ_NUM INT001_IRQn +#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn +#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RX_IRQ_NUM INT110_IRQn +#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_TX_IRQ_NUM INT111_IRQn +#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn +#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RX_IRQ_NUM INT114_IRQn +#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_IRQ_NUM INT113_IRQn +#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART10 */ + +#if defined(BSP_USING_CAN1) +#define BSP_CAN1_IRQ_NUM INT092_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN1 */ + +#if defined(BSP_USING_CAN2) +#define BSP_CAN2_IRQ_NUM INT093_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN2 */ + +#if defined(BSP_USING_SDIO1) +#define BSP_SDIO1_IRQ_NUM INT004_IRQn +#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#define BSP_SDIO2_IRQ_NUM INT005_IRQn +#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO2 */ + +#if defined(RT_USING_ALARM) +#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* RT_USING_ALARM */ + + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) +#define BSP_USB_GLB_IRQ_NUM INT003_IRQn +#define BSP_USB_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_USBD */ + +#if defined (BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_QSPI */ + +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_2) +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_3) +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_4) +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_5) +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_6) +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_7) +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_8) +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_9) +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_9 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_10) +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_10 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_11) +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_11 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_12) +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_12 */ + +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_2) +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_3) +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_4) +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_4 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_5) +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_5 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_6) +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_6 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_7) +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_7 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_8) +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_8 */ + +#if defined(BSP_USING_TMRA_1) +#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_1 */ +#if defined(BSP_USING_TMRA_2) +#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_2 */ +#if defined(BSP_USING_TMRA_3) +#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_3 */ +#if defined(BSP_USING_TMRA_4) +#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_4 */ +#if defined(BSP_USING_TMRA_5) +#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_5 */ +#if defined(BSP_USING_TMRA_6) +#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_6 */ +#if defined(BSP_USING_TMRA_7) +#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn +#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_7 */ +#if defined(BSP_USING_TMRA_8) +#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn +#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_8 */ +#if defined(BSP_USING_TMRA_9) +#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn +#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_9 */ +#if defined(BSP_USING_TMRA_10) +#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn +#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_10 */ +#if defined(BSP_USING_TMRA_11) +#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn +#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_11 */ +#if defined(BSP_USING_TMRA_12) +#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn +#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_12 */ +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h new file mode 100644 index 0000000000..3779fdbec5 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-05-12 CDT first version + */ + +#ifndef __PM_CONFIG_H__ +#define __PM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PM +extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); + +#ifndef PM_TICKLESS_TIMER_ENABLE_MASK +#define PM_TICKLESS_TIMER_ENABLE_MASK \ +( (1UL << PM_SLEEP_MODE_IDLE) | \ + (1UL << PM_SLEEP_MODE_DEEP)) +#endif + +/** + * @brief run mode config @ref pm_run_mode_config structure + */ +#ifndef PM_RUN_MODE_CFG +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ + } +#endif /* PM_RUN_MODE_CFG */ + +/** + * @brief sleep idle config @ref pm_sleep_mode_idle_config structure + */ +#ifndef PM_SLEEP_IDLE_CFG +#define PM_SLEEP_IDLE_CFG \ +{ \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ +} +#endif /*PM_SLEEP_IDLE_CFG*/ + +/** + * @brief sleep deep config @ref pm_sleep_mode_deep_config structure + */ +#ifndef PM_SLEEP_DEEP_CFG +#define PM_SLEEP_DEEP_CFG \ +{ \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ +} +#endif /*PM_SLEEP_DEEP_CFG*/ + +/** + * @brief sleep standby config @ref pm_sleep_mode_standby_config structure + */ +#ifndef PM_SLEEP_STANDBY_CFG +#define PM_SLEEP_STANDBY_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_STANDBY_CFG*/ + +/** + * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure + */ +#ifndef PM_SLEEP_SHUTDOWN_CFG +#define PM_SLEEP_SHUTDOWN_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_SHUTDOWN_CFG*/ + +#endif /* BSP_USING_PM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PM_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h new file mode 100644 index 0000000000..c4f76f3906 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h @@ -0,0 +1,544 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-06-09 CDT first version + */ + +#ifndef __PULSE_ENCODER_CONFIG_H__ +#define __PULSE_ENCODER_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_PULSE_ENCODER) + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_1 +#ifndef PULSE_ENCODER_TMRA_1_CONFIG +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_1, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ + } +#endif /* PULSE_ENCODER_TMRA_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_2 +#ifndef PULSE_ENCODER_TMRA_2_CONFIG +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_2, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ + } +#endif /* PULSE_ENCODER_TMRA_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_3 +#ifndef PULSE_ENCODER_TMRA_3_CONFIG +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_3, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ + } +#endif /* PULSE_ENCODER_TMRA_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_4 +#ifndef PULSE_ENCODER_TMRA_4_CONFIG +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_4, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ + } +#endif /* PULSE_ENCODER_TMRA_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_5 +#ifndef PULSE_ENCODER_TMRA_5_CONFIG +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_5, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ + } +#endif /* PULSE_ENCODER_TMRA_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_6 +#ifndef PULSE_ENCODER_TMRA_6_CONFIG +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_6, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ + } +#endif /* PULSE_ENCODER_TMRA_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_7 +#ifndef PULSE_ENCODER_TMRA_7_CONFIG +#define PULSE_ENCODER_TMRA_7_CONFIG \ + { \ + .tmr_handler = CM_TMRA_7, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_7, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a7" \ + } +#endif /* PULSE_ENCODER_TMRA_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_8 +#ifndef PULSE_ENCODER_TMRA_8_CONFIG +#define PULSE_ENCODER_TMRA_8_CONFIG \ + { \ + .tmr_handler = CM_TMRA_8, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_8, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a8" \ + } +#endif /* PULSE_ENCODER_TMRA_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_9 +#ifndef PULSE_ENCODER_TMRA_9_CONFIG +#define PULSE_ENCODER_TMRA_9_CONFIG \ + { \ + .tmr_handler = CM_TMRA_9, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_9, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a9" \ + } +#endif /* PULSE_ENCODER_TMRA_9_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_10 +#ifndef PULSE_ENCODER_TMRA_10_CONFIG +#define PULSE_ENCODER_TMRA_10_CONFIG \ + { \ + .tmr_handler = CM_TMRA_10, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_10, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a10" \ + } +#endif /* PULSE_ENCODER_TMRA_10_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_11 +#ifndef PULSE_ENCODER_TMRA_11_CONFIG +#define PULSE_ENCODER_TMRA_11_CONFIG \ + { \ + .tmr_handler = CM_TMRA_11, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_11, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a11" \ + } +#endif /* PULSE_ENCODER_TMRA_11_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_12 +#ifndef PULSE_ENCODER_TMRA_12_CONFIG +#define PULSE_ENCODER_TMRA_12_CONFIG \ + { \ + .tmr_handler = CM_TMRA_12, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_12, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a12" \ + } +#endif /* PULSE_ENCODER_TMRA_12_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_1 +#ifndef PULSE_ENCODER_TMR6_1_CONFIG +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_1, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ + } +#endif /* PULSE_ENCODER_TMR6_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_2 +#ifndef PULSE_ENCODER_TMR6_2_CONFIG +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_2, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ + } +#endif /* PULSE_ENCODER_TMR6_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_3 +#ifndef PULSE_ENCODER_TMR6_3_CONFIG +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_3, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ + } +#endif /* PULSE_ENCODER_TMR6_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_4 +#ifndef PULSE_ENCODER_TMR6_4_CONFIG +#define PULSE_ENCODER_TMR6_4_CONFIG \ + { \ + .tmr_handler = CM_TMR6_4, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_4, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_64" \ + } +#endif /* PULSE_ENCODER_TMR6_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_5 +#ifndef PULSE_ENCODER_TMR6_5_CONFIG +#define PULSE_ENCODER_TMR6_5_CONFIG \ + { \ + .tmr_handler = CM_TMR6_5, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_5, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_65" \ + } +#endif /* PULSE_ENCODER_TMR6_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_6 +#ifndef PULSE_ENCODER_TMR6_6_CONFIG +#define PULSE_ENCODER_TMR6_6_CONFIG \ + { \ + .tmr_handler = CM_TMR6_6, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_6, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_66" \ + } +#endif /* PULSE_ENCODER_TMR6_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_7 +#ifndef PULSE_ENCODER_TMR6_7_CONFIG +#define PULSE_ENCODER_TMR6_7_CONFIG \ + { \ + .tmr_handler = CM_TMR6_7, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_7, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_67" \ + } +#endif /* PULSE_ENCODER_TMR6_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_8 +#ifndef PULSE_ENCODER_TMR6_8_CONFIG +#define PULSE_ENCODER_TMR6_8_CONFIG \ + { \ + .tmr_handler = CM_TMR6_8, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_8, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_68" \ + } +#endif /* PULSE_ENCODER_TMR6_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */ + +#endif /* RT_USING_PULSE_ENCODER */ + +#endif /* __PULSE_ENCODER_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h new file mode 100644 index 0000000000..da87f320f8 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h @@ -0,0 +1,881 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-22 CDT first version + */ + +#ifndef __PWM_TMR_CONFIG_H__ +#define __PWM_TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM_TMRA + +#ifdef BSP_USING_PWM_TMRA_1 +#ifndef PWM_TMRA_1_CONFIG +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_1_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_1 */ + +#ifdef BSP_USING_PWM_TMRA_2 +#ifndef PWM_TMRA_2_CONFIG +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_2_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_2 */ + +#ifdef BSP_USING_PWM_TMRA_3 +#ifndef PWM_TMRA_3_CONFIG +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_3_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_3 */ + +#ifdef BSP_USING_PWM_TMRA_4 +#ifndef PWM_TMRA_4_CONFIG +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_4_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_4 */ + +#ifdef BSP_USING_PWM_TMRA_5 +#ifndef PWM_TMRA_5_CONFIG +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_5_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_5 */ + +#ifdef BSP_USING_PWM_TMRA_6 +#ifndef PWM_TMRA_6_CONFIG +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_6_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_6 */ + +#ifdef BSP_USING_PWM_TMRA_7 +#ifndef PWM_TMRA_7_CONFIG +#define PWM_TMRA_7_CONFIG \ + { \ + .name = "pwm_a7", \ + .instance = CM_TMRA_7, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_7_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_7 */ + +#ifdef BSP_USING_PWM_TMRA_8 +#ifndef PWM_TMRA_8_CONFIG +#define PWM_TMRA_8_CONFIG \ + { \ + .name = "pwm_a8", \ + .instance = CM_TMRA_8, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_8_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_8 */ + +#ifdef BSP_USING_PWM_TMRA_9 +#ifndef PWM_TMRA_9_CONFIG +#define PWM_TMRA_9_CONFIG \ + { \ + .name = "pwm_a9", \ + .instance = CM_TMRA_9, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_9_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_9 */ + +#ifdef BSP_USING_PWM_TMRA_10 +#ifndef PWM_TMRA_10_CONFIG +#define PWM_TMRA_10_CONFIG \ + { \ + .name = "pwm_a10", \ + .instance = CM_TMRA_10, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_10_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_10 */ + +#ifdef BSP_USING_PWM_TMRA_11 +#ifndef PWM_TMRA_11_CONFIG +#define PWM_TMRA_11_CONFIG \ + { \ + .name = "pwm_a11", \ + .instance = CM_TMRA_11, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_11_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_11 */ + +#ifdef BSP_USING_PWM_TMRA_12 +#ifndef PWM_TMRA_12_CONFIG +#define PWM_TMRA_12_CONFIG \ + { \ + .name = "pwm_a12", \ + .instance = CM_TMRA_12, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_12_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_12 */ + +#endif /* BSP_USING_PWM_TMRA */ + +#ifdef BSP_USING_PWM_TMR4 + +#ifdef BSP_USING_PWM_TMR4_1 +#ifndef PWM_TMR4_1_CONFIG +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_1 */ + +#ifdef BSP_USING_PWM_TMR4_2 +#ifndef PWM_TMR4_2_CONFIG +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_2 */ + +#ifdef BSP_USING_PWM_TMR4_3 +#ifndef PWM_TMR4_3_CONFIG +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_3 */ + +#endif /* BSP_USING_PWM_TMR4 */ + +#ifdef BSP_USING_PWM_TMR6 + +#ifdef BSP_USING_PWM_TMR6_1 +#ifndef PWM_TMR6_1_CONFIG +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_1 */ +#ifdef BSP_USING_PWM_TMR6_2 +#ifndef PWM_TMR6_2_CONFIG +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_2 */ +#ifdef BSP_USING_PWM_TMR6_3 +#ifndef PWM_TMR6_3_CONFIG +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_3 */ +#ifdef BSP_USING_PWM_TMR6_4 +#ifndef PWM_TMR6_4_CONFIG +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t64", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_4_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_4 */ +#ifdef BSP_USING_PWM_TMR6_5 +#ifndef PWM_TMR6_5_CONFIG +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t65", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_5_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_5 */ +#ifdef BSP_USING_PWM_TMR6_6 +#ifndef PWM_TMR6_6_CONFIG +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t66", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_6_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_6 */ +#ifdef BSP_USING_PWM_TMR6_7 +#ifndef PWM_TMR6_7_CONFIG +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t67", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_7_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_7 */ +#ifdef BSP_USING_PWM_TMR6_8 +#ifndef PWM_TMR6_8_CONFIG +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t68", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } \ + }, \ + } +#endif /* PWM_TMR6_8_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_8 */ + +#endif /* BSP_USING_PWM_TMR6 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_TMRA_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h new file mode 100644 index 0000000000..b8e74bfae1 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-06-15 CDT first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ + } +#endif /* QSPI_BUS_CONFIG */ + +#ifndef QSPI_INIT_PARAMS +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ + } +#endif /* QSPI_INIT_PARAMS */ + +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ +#endif /* BSP_USING_SPI1 */ + +#ifdef __cplusplus +} +#endif + +#endif /*__QSPI_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h new file mode 100644 index 0000000000..8d1d1bf897 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-14 CDT first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_SDIO1) +#ifndef SDIO1_BUS_CONFIG +#define SDIO1_BUS_CONFIG \ + { \ + .name = "sdio1", \ + .instance = CM_SDIOC1, \ + .clock = FCG1_PERIPH_SDIOC1, \ + .irq_config = \ + { \ + .irq_num = BSP_SDIO1_IRQ_NUM, \ + .irq_prio = BSP_SDIO1_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC1_SD, \ + }, \ + .dma_rx = \ + { \ + .Instance = SDIO1_RX_DMA_INSTANCE, \ + .channel = SDIO1_RX_DMA_CHANNEL, \ + .clock = SDIO1_RX_DMA_CLOCK, \ + .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAR, \ + }, \ + .dma_tx = \ + { \ + .Instance = SDIO1_TX_DMA_INSTANCE, \ + .channel = SDIO1_TX_DMA_CHANNEL, \ + .clock = SDIO1_TX_DMA_CLOCK, \ + .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAW, \ + }, \ + } +#endif /* SDIO1_BUS_CONFIG */ +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#ifndef SDIO2_BUS_CONFIG +#define SDIO2_BUS_CONFIG \ + { \ + .name = "sdio2", \ + .instance = CM_SDIOC2, \ + .clock = FCG1_PERIPH_SDIOC2, \ + .irq_config = \ + { \ + .irq_num = BSP_SDIO2_IRQ_NUM, \ + .irq_prio = BSP_SDIO2_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC2_SD, \ + }, \ + .dma_rx = \ + { \ + .Instance = SDIO2_RX_DMA_INSTANCE, \ + .channel = SDIO2_RX_DMA_CHANNEL, \ + .clock = SDIO2_RX_DMA_CLOCK, \ + .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAR, \ + }, \ + .dma_tx = \ + { \ + .Instance = SDIO2_TX_DMA_INSTANCE, \ + .channel = SDIO2_TX_DMA_CHANNEL, \ + .clock = SDIO2_TX_DMA_CLOCK, \ + .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAW, \ + }, \ + } +#endif /* SDIO2_BUS_CONFIG */ +#endif /* BSP_USING_SDIO2 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h new file mode 100644 index 0000000000..a839686bd3 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI5_SPEI, \ + }, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .flag = SPI5_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .flag = SPI5_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI6_SPEI, \ + }, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .flag = SPI6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .flag = SPI6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h new file mode 100644 index 0000000000..553ffc8629 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-06-21 CDT first version + */ + +#ifndef __TMR_CONFIG_H__ +#define __TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TMRA_1 +#ifndef TMRA_1_CONFIG +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ + } +#endif /* TMRA_1_CONFIG */ +#endif /* BSP_USING_TMRA_1 */ + +#ifdef BSP_USING_TMRA_2 +#ifndef TMRA_2_CONFIG +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ + } +#endif /* TMRA_2_CONFIG */ +#endif /* BSP_USING_TMRA_2 */ + +#ifdef BSP_USING_TMRA_3 +#ifndef TMRA_3_CONFIG +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ + } +#endif /* TMRA_3_CONFIG */ +#endif /* BSP_USING_TMRA_3 */ + +#ifdef BSP_USING_TMRA_4 +#ifndef TMRA_4_CONFIG +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ + } +#endif /* TMRA_4_CONFIG */ +#endif /* BSP_USING_TMRA_4 */ + +#ifdef BSP_USING_TMRA_5 +#ifndef TMRA_5_CONFIG +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ + } +#endif /* TMRA_5_CONFIG */ +#endif /* BSP_USING_TMRA_5 */ + +#ifdef BSP_USING_TMRA_6 +#ifndef TMRA_6_CONFIG +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ + } +#endif /* TMRA_6_CONFIG */ +#endif /* BSP_USING_TMRA_6 */ + +#ifdef BSP_USING_TMRA_7 +#ifndef TMRA_7_CONFIG +#define TMRA_7_CONFIG \ + { \ + .tmr_handle = CM_TMRA_7, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_7, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_7_OVF, \ + .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ + }, \ + .name = "tmra_7" \ + } +#endif /* TMRA_7_CONFIG */ +#endif /* BSP_USING_TMRA_7 */ + +#ifdef BSP_USING_TMRA_8 +#ifndef TMRA_8_CONFIG +#define TMRA_8_CONFIG \ + { \ + .tmr_handle = CM_TMRA_8, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_8, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_8_OVF, \ + .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ + }, \ + .name = "tmra_8" \ + } +#endif /* TMRA_8_CONFIG */ +#endif /* BSP_USING_TMRA_8 */ + +#ifdef BSP_USING_TMRA_9 +#ifndef TMRA_9_CONFIG +#define TMRA_9_CONFIG \ + { \ + .tmr_handle = CM_TMRA_9, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_9, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_9_OVF, \ + .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ + }, \ + .name = "tmra_9" \ + } +#endif /* TMRA_9_CONFIG */ +#endif /* BSP_USING_TMRA_9 */ + +#ifdef BSP_USING_TMRA_10 +#ifndef TMRA_10_CONFIG +#define TMRA_10_CONFIG \ + { \ + .tmr_handle = CM_TMRA_10, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_10, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_10_OVF, \ + .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ + }, \ + .name = "tmra_10" \ + } +#endif /* TMRA_10_CONFIG */ +#endif /* BSP_USING_TMRA_10 */ + +#ifdef BSP_USING_TMRA_11 +#ifndef TMRA_11_CONFIG +#define TMRA_11_CONFIG \ + { \ + .tmr_handle = CM_TMRA_11, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_11, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_11_OVF, \ + .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ + }, \ + .name = "tmra_11" \ + } +#endif /* TMRA_11_CONFIG */ +#endif /* BSP_USING_TMRA_11 */ + +#ifdef BSP_USING_TMRA_12 +#ifndef TMRA_12_CONFIG +#define TMRA_12_CONFIG \ + { \ + .tmr_handle = CM_TMRA_12, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_12, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_12_OVF, \ + .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ + }, \ + .name = "tmra_12" \ + } +#endif /* TMRA_12_CONFIG */ +#endif /* BSP_USING_TMRA_12 */ +#endif /* __TMR_CONFIG_H__ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h new file mode 100644 index 0000000000..e69b988d00 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h @@ -0,0 +1,728 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_RX_CONFIG */ + +#ifndef UART1_RXTO_CONFIG +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ + } +#endif /* UART1_RXTO_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#endif /* UART1_TX_CPLT_CONFIG */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_RX_CONFIG */ + +#ifndef UART2_RXTO_CONFIG +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ + } +#endif /* UART2_RXTO_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#endif /* UART2_TX_CPLT_CONFIG */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ + } +#endif /* UART3_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART3_TX_CPLT_CONFIG +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ + } +#endif +#endif /* UART3_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ + } +#endif /* UART4_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif +#endif /* UART4_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART5_RX_IRQ_NUM, \ + .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART5_TX_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TI, \ + }, \ + } +#endif /* UART5_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART5_TX_CPLT_CONFIG +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ + } +#endif +#endif /* UART5_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART6_RX_IRQ_NUM, \ + .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART6_TX_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TI, \ + }, \ + } +#endif /* UART6_CONFIG */ + +#if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_DMA_RX_CONFIG +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .clock = UART6_RX_DMA_CLOCK, \ + .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_RI, \ + .flag = UART6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART6_RX_DMA_IRQn, \ + .irq_prio = UART6_RX_DMA_INT_PRIO, \ + .int_src = UART6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_RX_CONFIG */ + +#ifndef UART6_RXTO_CONFIG +#define UART6_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RTO, \ + }, \ + } +#endif /* UART6_RXTO_CONFIG */ +#endif /* BSP_UART6_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#endif /* UART6_TX_CPLT_CONFIG */ + +#if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_DMA_TX_CONFIG +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .channel = UART6_TX_DMA_CHANNEL, \ + .clock = UART6_TX_DMA_CLOCK, \ + .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_TI, \ + .flag = UART6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART6_TX_DMA_IRQn, \ + .irq_prio = UART6_TX_DMA_INT_PRIO, \ + .int_src = UART6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_TX_CONFIG */ +#endif /* BSP_UART6_TX_USING_DMA */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = CM_USART7, \ + .clock = FCG3_PERIPH_USART7, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART7_RX_IRQ_NUM, \ + .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART7_TX_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ + } +#endif /* UART7_CONFIG */ + +#if defined(BSP_UART7_RX_USING_DMA) +#ifndef UART7_DMA_RX_CONFIG +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .channel = UART7_RX_DMA_CHANNEL, \ + .clock = UART7_RX_DMA_CLOCK, \ + .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_RI, \ + .flag = UART7_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART7_RX_DMA_IRQn, \ + .irq_prio = UART7_RX_DMA_INT_PRIO, \ + .int_src = UART7_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_RX_CONFIG */ + +#ifndef UART7_RXTO_CONFIG +#define UART7_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = \ + { \ + .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RTO, \ + }, \ + } +#endif /* UART7_RXTO_CONFIG */ +#endif /* BSP_UART7_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#endif /* UART7_TX_CPLT_CONFIG */ + +#if defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_DMA_TX_CONFIG +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .channel = UART7_TX_DMA_CHANNEL, \ + .clock = UART7_TX_DMA_CLOCK, \ + .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART7_TX_DMA_IRQn, \ + .irq_prio = UART7_TX_DMA_INT_PRIO, \ + .int_src = UART7_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_TX_CONFIG */ +#endif /* BSP_UART7_TX_USING_DMA */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +#ifndef UART8_CONFIG +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = CM_USART8, \ + .clock = FCG3_PERIPH_USART8, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART8_RX_IRQ_NUM, \ + .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART8_TX_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TI, \ + }, \ + } +#endif /* UART8_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART8_TX_CPLT_CONFIG +#define UART8_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TCI, \ + }, \ + } +#endif +#endif /* UART8_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +#ifndef UART9_CONFIG +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = CM_USART9, \ + .clock = FCG3_PERIPH_USART9, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART9_RX_IRQ_NUM, \ + .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART9_TX_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TI, \ + }, \ + } +#endif /* UART9_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART9_TX_CPLT_CONFIG +#define UART9_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TCI, \ + }, \ + } +#endif +#endif /* UART9_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +#ifndef UART10_CONFIG +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = CM_USART10, \ + .clock = FCG3_PERIPH_USART10, \ + .rxerr_irq.irq_config = \ + { \ + .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_EI, \ + }, \ + .rx_irq.irq_config = \ + { \ + .irq_num = BSP_UART10_RX_IRQ_NUM, \ + .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_RI, \ + }, \ + .tx_irq.irq_config = \ + { \ + .irq_num = BSP_UART10_TX_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TI, \ + }, \ + } +#endif /* UART10_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART10_TX_CPLT_CONFIG +#define UART10_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TCI, \ + }, \ + } +#endif +#endif /* UART10_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART10 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h new file mode 100644 index 0000000000..52d43fca67 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-14 CDT first version + */ + +#ifndef __USB_APP_CONF_H__ +#define __USB_APP_CONF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "rtconfig.h" + +/* USB MODE CONFIGURATION */ +/* +USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment +(1) If only defined USB_FS_MODE: + MCU USBFS core work in full speed using internal PHY. +(2) If only defined USB_HS_MODE: + MCU USBHS core work in full speed using internal PHY. +(3) If both defined USB_HS_MODE && USB_HS_EXTERNAL_PHY + MCU USBHS core work in high speed using external PHY. +(4) Other combination: + Not support, forbid!! +*/ + +#if defined(BSP_USING_USBHS) +#define USB_HS_MODE +#elif defined(BSP_USING_USBFS) +#define USB_FS_MODE +#else +#define USB_FS_MODE +#endif + +#if defined(BSP_USING_USBD) +#define USE_DEVICE_MODE +#elif defined(BSP_USING_USBH) +#define USE_HOST_MODE +#else +#define USE_DEVICE_MODE +#endif + +#if defined(USB_HS_MODE) && defined(BSP_USING_USBHS_PHY_EXTERN) +#define USB_HS_EXTERNAL_PHY +#endif + +#ifndef USB_HS_MODE +#ifndef USB_FS_MODE +#error "USB_HS_MODE or USB_FS_MODE should be defined" +#endif +#endif + +#ifndef USE_DEVICE_MODE +#ifndef USE_HOST_MODE +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#endif +#endif + +#if defined(BSP_USING_USBD) +/* USB DEVICE FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) +#define TX6_FIFO_FS_SIZE (32U) +#define TX7_FIFO_FS_SIZE (32U) +#define TX8_FIFO_FS_SIZE (32U) +#define TX9_FIFO_FS_SIZE (32U) +#define TX10_FIFO_FS_SIZE (32U) +#define TX11_FIFO_FS_SIZE (32U) +#define TX12_FIFO_FS_SIZE (32U) +#define TX13_FIFO_FS_SIZE (32U) +#define TX14_FIFO_FS_SIZE (32U) +#define TX15_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ + TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ + TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ + TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \ + TX15_FIFO_FS_SIZE) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TX0_FIFO_HS_SIZE (64U) +#define TX1_FIFO_HS_SIZE (64U) +#define TX2_FIFO_HS_SIZE (64U) +#define TX3_FIFO_HS_SIZE (64U) +#define TX4_FIFO_HS_SIZE (64U) +#define TX5_FIFO_HS_SIZE (64U) +#define TX6_FIFO_HS_SIZE (64U) +#define TX7_FIFO_HS_SIZE (64U) +#define TX8_FIFO_HS_SIZE (64U) +#define TX9_FIFO_HS_SIZE (64U) +#define TX10_FIFO_HS_SIZE (64U) +#define TX11_FIFO_HS_SIZE (64U) +#define TX12_FIFO_HS_SIZE (64U) +#define TX13_FIFO_HS_SIZE (64U) +#define TX14_FIFO_HS_SIZE (64U) +#define TX15_FIFO_HS_SIZE (64U) + +#if ((RX_FIFO_HS_SIZE + \ + TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ + TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ + TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \ + TX15_FIFO_HS_SIZE) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif + +#if defined(BSP_USING_USBD_VBUS_SENSING) +#define VBUS_SENSING_ENABLED +#endif +#endif + +#if defined(BSP_USING_USBH) +/* USB HOST FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (32U) +#define TXH_P_FS_FIFOSIZ (64U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TXH_NP_HS_FIFOSIZ (128U) +#define TXH_P_HS_FIFOSIZ (256U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_APP_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h new file mode 100644 index 0000000000..76b5b37d81 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-14 CDT first version + */ + +#ifndef __USB_BSP_H__ +#define __USB_BSP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "hc32_ll_utility.h" + +extern void usb_udelay(const uint32_t usec); +extern void usb_mdelay(const uint32_t msec); + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_BSP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/drv_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/drv_config.h new file mode 100644 index 0000000000..6ec87e9ee9 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/drv_config.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dma_config.h" +#include "uart_config.h" +#include "spi_config.h" +#include "adc_config.h" +#include "dac_config.h" +#include "gpio_config.h" +#include "eth_config.h" +#include "can_config.h" +#include "sdio_config.h" +#include "pm_config.h" +#include "i2c_config.h" +#include "qspi_config.h" +#include "pulse_encoder_config.h" +#include "timer_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h new file mode 100644 index 0000000000..7d733e221a --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h @@ -0,0 +1,204 @@ +/** + ******************************************************************************* + * @file template/source/hc32f4xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_CONF_H__ +#define __HC32F4XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_HRPWM_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR2_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F4A0_LQFP176 (1U) + +/** + * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F4XX (BSP_EV_HC32F4A0_LQFP176) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_GT9XX_ENABLE (DDL_OFF) +#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF) +#define BSP_IS62WV51216_ENABLE (DDL_OFF) +#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_OV5640_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8731_ENABLE (DDL_OFF) + +/** + * @brief Ethernet and PHY Configuration. + */ +/* MAC ADDRESS */ +#define ETH_MAC_ADDR0 (0x02U) +#define ETH_MAC_ADDR1 (0x00U) +#define ETH_MAC_ADDR2 (0x00U) +#define ETH_MAC_ADDR3 (0x00U) +#define ETH_MAC_ADDR4 (0x00U) +#define ETH_MAC_ADDR5 (0x00U) + +/* Common PHY Registers */ +#define PHY_BCR (0x00U) /*!< Basic Control Register */ +#define PHY_BSR (0x01U) /*!< Basic Status Register */ + +#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */ +#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */ +#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */ + +#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */ +#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */ +#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */ +#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */ +#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */ + +#if defined (ETH_PHY_USING_RTL8201F) +/* PHY(RTL8201F) Address*/ +#define ETH_PHY_ADDR (0x00U) + +/* PHY Configuration delay(ms) */ +#define ETH_PHY_RST_DELAY (0x0080UL) +#define ETH_PHY_CONFIG_DELAY (0x0800UL) +#define ETH_PHY_RD_TIMEOUT (0x0005UL) +#define ETH_PHY_WR_TIMEOUT (0x0005UL) + +/* PHY Status Register */ +#define PHY_SR (PHY_BCR) /*!< PHY status register */ + +#define PHY_DUPLEX_STATUS (PHY_FULLDUPLEX_10M) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (PHY_HALFDUPLEX_100M) /*!< PHY Speed mask */ + +#endif + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf new file mode 100644 index 0000000000..863d995ff9 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf @@ -0,0 +1,115 @@ +/***************************************************************************//** + * \file HC32F4A0.icf + * \version 1.0 + * + * \brief Linker file for the IAR compiler. + * +******************************************************************************** +* \copyright + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause +*******************************************************************************/ +/*###ICF### Section handled by ICF editor, don't touch! *****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +// Check that necessary symbols have been passed to linker via command line interface +if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) { + error "Link location not defined or not supported!"; +} +if((!isdefinedsymbol(_HC32F4A0_2M_)) && (!isdefinedsymbol(_HC32F4A0_1M_SINGLE_)) && (!isdefinedsymbol(_HC32F4A0_1M_DUAL_))) { + error "Mcu type or size not defined or not supported!"; +} + +/******************************************************************************* + * Memory address and size definitions + ******************************************************************************/ +define symbol ram1_base_address = 0x1FFE0000; +define symbol ram1_end_address = 0x2005FFFF; + +if(isdefinedsymbol(_LINK_RAM_)) { + define symbol ram_start_reserve = 0x20000; + define symbol rom1_base_address = ram1_base_address; + define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; + define symbol rom3_base_address = 0x0; + define symbol rom3_end_address = 0x0; +} else { + define symbol ram_start_reserve = 0x0; + define symbol rom1_base_address = 0x0; + define symbol rom3_base_address = 0x03000000; + define symbol rom3_end_address = 0x030017FF; + if (isdefinedsymbol(_HC32F4A0_2M_)) { + define symbol rom1_end_address = 0x001FFFFF; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; + } else if (isdefinedsymbol(_HC32F4A0_1M_SINGLE_)) { + define symbol rom1_end_address = 0x000FFFFF; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; + } else if (isdefinedsymbol(_HC32F4A0_1M_DUAL_)) { + define symbol rom1_end_address = 0x0007FFFF; + define symbol rom2_base_address = 0x00100000; + define symbol rom2_end_address = 0x0017FFFF; + } +} + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = rom1_base_address; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address; +define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address; +define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address; +define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address; +define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address; +define symbol __ICFEDIT_region_IROM3_end__ = rom3_end_address; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve; +define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +/******************************************************************************* + * Memory definitions + ******************************************************************************/ +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region OTP_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in OTP_region { readonly section .otp_data }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.ld b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.ld new file mode 100644 index 0000000000..8be3ef8823 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.ld @@ -0,0 +1,270 @@ +/****************************************************************************** + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F4A0xI.ld */ +/* Abstract Linker script for HC32F4A0 Device with */ +/* 2MByte FLASH, 516KByte RAM */ +/* Version V1.0 */ +/* Date 2022-03-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 16 for example. */ +__OTP_DATA_START = 0x03000000; +__OTP_DATA_SIZE = 2048; +__OTP_LOCK_START = 0x03001840; +__OTP_LOCK_SIZE = 4; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + __bss_start = .; + .bss __StackTop (NOLOAD): + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + . = ALIGN(4); + *(.noinit*) + . = ALIGN(4); + } >RAM + __bss_end = .; + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.sct b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.sct new file mode 100644 index 0000000000..0bf7fc8eb1 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.sct @@ -0,0 +1,22 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00000000 0x00200000 { ; load region size_region + ER_IROM1 0x00000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFE0000 UNINIT 0x00000008 { ; RW data + *(.bss.noinit) + } + RW_IRAM2 0x1FFE0008 0x0007FFF8 { ; RW data + .ANY (+RW +ZI) + .ANY (RAMCODE) + } + RW_IRAMB 0x200F0000 0x00001000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/SConscript b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/SConscript new file mode 100644 index 0000000000..3c57bc9c6d --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/SConscript @@ -0,0 +1,12 @@ +import os +from building import * + +objs = [] +cwd = GetCurrentDir() + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/drv_spi_flash.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/drv_spi_flash.c new file mode 100644 index 0000000000..f1db0fff56 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/drv_spi_flash.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef BSP_USING_SPI_FLASH + +#include "spi_flash.h" +#ifdef RT_USING_SFUD + #include "spi_flash_sfud.h" +#endif + +#define SPI_BUS_NAME "spi1" +#define SPI_FLASH_DEVICE_NAME "spi10" +#define SPI_FLASH_CHIP "w25q64" +#define SPI_FLASH_SS_PORT GPIO_PORT_A +#define SPI_FLASH_SS_PIN GPIO_PIN_04 +/* Partition Name */ +#define FS_PARTITION_NAME "filesystem" + +#ifdef RT_USING_SFUD +static void rt_hw_spi_flash_reset(char *spi_dev_name) +{ + struct rt_spi_device *spi_dev_w25; + rt_uint8_t w25_en_reset = 0x66; + rt_uint8_t w25_reset_dev = 0x99; + + spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name); + if (!spi_dev_w25) + { + rt_kprintf("Can't find %s device!\n", spi_dev_name); + } + else + { + rt_spi_send(spi_dev_w25, &w25_en_reset, 1U); + rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U); + DDL_DelayMS(1U); + rt_kprintf("Reset ext flash!\n"); + } +} + +static int rt_hw_spi_flash_with_sfud_init(void) +{ + rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PORT, SPI_FLASH_SS_PIN); + + if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME)) + { + rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME); + if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME)) + { + return -RT_ERROR; + } + } + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); + +static int rt_hw_fs_init(void) +{ + struct rt_device *mtd_dev = RT_NULL; + + /* 初始化 fal */ + fal_init(); + /* 生成 mtd 设备 */ + mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME); + if (!mtd_dev) + { + LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME); + return -RT_ERROR; + } + else + { + /* 挂载 littlefs */ + if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0)) + { + LOG_I("Filesystem initialized!"); + return RT_EOK; + } + else + { + /* 格式化文件系统 */ + if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME)) + { + /* 挂载 littlefs */ + if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0)) + { + LOG_I("Filesystem initialized!"); + return RT_EOK; + } + else + { + LOG_E("Failed to initialize filesystem!"); + return -RT_ERROR; + } + } + else + { + LOG_E("Failed to Format fs!"); + return -RT_ERROR; + } + } + } +} +INIT_APP_EXPORT(rt_hw_fs_init); + +#endif /* RT_USING_SFUD */ + +#endif /* BSP_USING_SPI_FLASH */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/SConscript b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/SConscript new file mode 100644 index 0000000000..cee47c2d7e --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/SConscript @@ -0,0 +1,20 @@ + +from building import * +import rtconfig + +cwd = GetCurrentDir() + +src = [] + +src += Glob('*.c') +CPPPATH = [cwd] +LOCAL_CFLAGS = '' + +if rtconfig.PLATFORM in ['gcc', 'armclang']: + LOCAL_CFLAGS += ' -std=c99' +elif rtconfig.PLATFORM in ['armcc']: + LOCAL_CFLAGS += ' --c99' + +group = DefineGroup('FAL', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS) + +Return('group') diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_cfg.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_cfg.h new file mode 100644 index 0000000000..5d8fbbe9e6 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_cfg.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +/* enable hc32f4 onchip flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_HC32F4 +/* enable SFUD flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_SFUD + +extern const struct fal_flash_dev hc32_onchip_flash; +extern struct fal_flash_dev ext_nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ +} + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_flash_sfud_port.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_flash_sfud_port.c new file mode 100644 index 0000000000..b52d72de00 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_flash_sfud_port.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include + +#include +#ifdef RT_USING_SFUD + #include +#endif + +#ifndef FAL_USING_NOR_FLASH_DEV_NAME + #define FAL_USING_NOR_FLASH_DEV_NAME "w25q64" +#endif + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static sfud_flash_t sfud_dev = NULL; +struct fal_flash_dev ext_nor_flash0 = +{ + .name = FAL_USING_NOR_FLASH_DEV_NAME, + .addr = 0, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = {init, read, write, erase}, + .write_gran = 1 +}; + +static int init(void) +{ + /* RT-Thread RTOS platform */ + sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME); + if (NULL == sfud_dev) + { + return -1; + } + /* update the flash chip information */ + ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran; + ext_nor_flash0.len = sfud_dev->chip.capacity; + + return 0; +} + +static int read(long offset, uint8_t *buf, size_t size) +{ + assert(sfud_dev); + assert(sfud_dev->init_ok); + sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf); + + return size; +} + +static int write(long offset, const uint8_t *buf, size_t size) +{ + assert(sfud_dev); + assert(sfud_dev->init_ok); + if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} + +static int erase(long offset, size_t size) +{ + assert(sfud_dev); + assert(sfud_dev->init_ok); + if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h new file mode 100644 index 0000000000..34b62b6fa3 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-03-01 CDT first version + */ + +#ifndef __NAND_PORT_H__ +#define __NAND_PORT_H__ + +/******************** NAND chip information ***********************************/ +#define NAND_BYTES_PER_PAGE 2048UL +#define NAND_SPARE_AREA_SIZE 64UL +#define NAND_PAGES_PER_BLOCK 64UL +#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) +#define NAND_BLOCKS_PER_PLANE 1024UL +#define NAND_PLANE_PER_DEVICE 2UL +#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) +#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) + +/******************** EXMC_NFC configure **************************************/ +/* chip: EXMC_NFC_BANK0~7 */ +#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0 + +/* density:2Gbit */ +#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT + +/* device width: 8-bit */ +#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT + +/* page size: 2KByte */ +#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE + +/* row address cycle: 3 */ +#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE + +/* ECC mode */ +#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC + +/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */ +/* TS: ALE/CLE/CE setup time(min=10ns) */ +#define NAND_TS 1U + +/* TWP: WE# pulse width (min=10ns) */ +#define NAND_TWP 1U + +/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */ +#define NAND_TRP 2U + +/* TTH: ALE/CLE/CE hold time (min=5ns) */ +#define NAND_TH 1U + +/* TWH: WE# pulse width HIGH (min=10ns) */ +#define NAND_TWH 1U + +/* TRH: RE# pulse width HIGH (min=7ns) */ +#define NAND_TRH 1U + +/* TRR: Ready to RE# LOW (min=20ns) */ +#define NAND_TRR 2U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TWB 1U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TRB 1U + +/* TCCS: Change read column and Change write column delay */ +#define NAND_TCCS 5U + +/* TWTR: WE# HIGH to RE# LOW (min=60ns) */ +#define NAND_TWTR 4U + +/* TRTW: RE# HIGH to WE# LOW (min=100ns) */ +#define NAND_TRTW 7U + +/* TADL: ALE to data start (min=70ns) */ +#define NAND_TADL 5U + +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h new file mode 100644 index 0000000000..48f5437055 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-24 CDT first version + * 2024-02-20 CDT modify timing configuration for using exclk clock frequency 30MHz + * add t_rcd/t_rfc/t_rp configuration macros-definition + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +/* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */ +#define SDRAM_CHIP EXMC_DMC_CHIP1 +/* bank address */ +#define SDRAM_BANK_ADDR (0x80000000UL) +/* size(kbyte):8MB = 8*1024*1KBytes */ +#define SDRAM_SIZE (8UL * 1024UL * 1024UL) +/* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */ +#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 +/* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */ +#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT +/* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */ +#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM8 +/* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */ +#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM12 +/* cas latency clock number: 2, 3 */ +#define SDRAM_CAS_LATENCY 2UL +/* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */ +#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT + +/* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */ +#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD +/* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */ +#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL +/* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ +#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED + +/* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */ +/* refresh rate counter (EXCLK clock) */ +#define SDRAM_REFRESH_COUNT (450U) +/* TMDR: mode register command time (EXCLK clock) */ +#define SDRAM_TMDR 2U +/* TRAS: RAS to precharge delay time (EXCLK clock) */ +#define SDRAM_TRAS 2U +/* TRC: active bank x to active bank x delay time (EXCLK clock) */ +#define SDRAM_TRC 2U +/* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ +#define SDRAM_TRCD_B 3U +#define SDRAM_TRCD_P 0U +/* TRFC: autorefresh command time (EXCLK clock) */ +#define SDRAM_TRFC_B 3U +#define SDRAM_TRFC_P 0U +/* TRP: precharge to RAS delay time (EXCLK clock) */ +#define SDRAM_TRP_B 3U +#define SDRAM_TRP_P 0U +/* TRRD: active bank x to active bank y delay time (EXCLK clock) */ +#define SDRAM_TRRD 1U +/* TWR: write to precharge delay time (EXCLK clock). */ +#define SDRAM_TWR 2U +/* TWTR: write to read delay time (EXCLK clock). */ +#define SDRAM_TWTR 1U +/* TXP: exit power-down command time (EXCLK clock). */ +#define SDRAM_TXP 1U +/* TXSR: exit self-refresh command time (EXCLK clock). */ +#define SDRAM_TXSR 5U +/* TESR: self-refresh command time (EXCLK clock). */ +#define SDRAM_TESR 5U + +/* memory mode register */ +#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) +#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) +#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) +#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) +#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) +#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) + +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.c new file mode 100644 index 0000000000..b27410cdf2 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.c @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#include +#include +#include + +#ifdef BSP_USING_TCA9539 + +#include "tca9539.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Define for TCA9539 */ +#define BSP_TCA9539_I2C_BUS_NAME "i2c1" +#define BSP_TCA9539_DEV_ADDR (0x74U) + +#define TCA9539_RST_PIN (45) /* PC13 */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static struct rt_i2c_bus_device *i2c_bus = RT_NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief BSP TCA9539 write data. + * @param [in] bus: Pointer to the i2c bus device. + * @param [in] reg: Register to be written. + * @param [in] data: The pointer to the buffer contains the data to be written. + * @param [in] len: Buffer size in byte. + * @retval rt_err_t: + * - RT_EOK + * - -RT_ERROR + */ +static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len) +{ + struct rt_i2c_msg msgs; + rt_uint8_t buf[6]; + + buf[0] = reg; + if (len > 0) + { + if (len < 6) + { + rt_memcpy(buf + 1, data, len); + } + else + { + return -RT_ERROR; + } + } + msgs.addr = BSP_TCA9539_DEV_ADDR; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = len + 1; + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +/** + * @brief BSP TCA9539 Read data. + * @param [in] bus: Pointer to the i2c bus device. + * @param [in] reg: Register to be read. + * @param [out] data: The pointer to the buffer contains the data to be read. + * @param [in] len: Buffer size in byte. + * @retval rt_err_t: + * - RT_EOK + * - -RT_ERROR + */ +static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len) +{ + struct rt_i2c_msg msgs; + + if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0)) + { + return -RT_ERROR; + } + msgs.addr = BSP_TCA9539_DEV_ADDR; + msgs.flags = RT_I2C_RD; + msgs.buf = data; + msgs.len = len; + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + + +/** + * @brief Reset TCA9539. + * @param [in] None + * @retval None + */ +static void TCA9539_Reset(void) +{ + rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT); + /* Reset the device */ + rt_pin_write(TCA9539_RST_PIN, PIN_LOW); + rt_thread_mdelay(3U); + rt_pin_write(TCA9539_RST_PIN, PIN_HIGH); +} + +/** + * @brief Write TCA9539 pin output value. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @param [in] u8PinState Pin state to be written. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Pin_State_Definition + * @retval rt_err_t: + * - RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + if (0U == u8PinState) + { + u8TempData[1] &= (uint8_t)(~u8Pin); + } + else + { + u8TempData[1] |= u8Pin; + } + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Read TCA9539 pin input value. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @param [in] u8PinState Pin state to be written. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Pin_State_Definition + * @retval rt_err_t: + * - RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + if (0U != (u8TempData[1] & u8Pin)) + { + *pu8PinState = TCA9539_PIN_SET; + } + else + { + *pu8PinState = TCA9539_PIN_RESET; + } + + return RT_EOK; +} + +/** + * @brief Toggle TCA9539 pin output value. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @retval rt_err_t: + * - -RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + u8TempData[1] ^= u8Pin; + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Configuration TCA9539 pin. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @param [in] u8Dir Pin output direction. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Direction_Definition + * @retval rt_err_t: + * - -RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + if (TCA9539_DIR_OUT == u8Dir) + { + u8TempData[1] &= (uint8_t)(~u8Pin); + } + else + { + u8TempData[1] |= u8Pin; + } + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Initialize TCA9539. + * @param [in] None + * @retval rt_err_t: + * - -RT_ERROR + * - RT_EOK + */ +int TCA9539_Init(void) +{ + char name[RT_NAME_MAX]; + uint8_t u8TempData[2]; + + TCA9539_Reset(); + rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX); + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name); + if (i2c_bus == RT_NULL) + { + rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME); + return -RT_ERROR; + } + /* All Pins are input as default */ + u8TempData[0] = TCA9539_REG_CONFIG_PORT0; + u8TempData[1] = 0xFFU; + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + u8TempData[0] = TCA9539_REG_CONFIG_PORT1; + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_PREV_EXPORT(TCA9539_Init); + +#endif /* BSP_USING_TCA9539 */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.h new file mode 100644 index 0000000000..ee1f84db08 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __TCA9539_H__ +#define __TCA9539_H__ + +#include + +/** + * @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition + * @{ + */ +#define TCA9539_REG_INPUT_PORT0 (0x00U) +#define TCA9539_REG_INPUT_PORT1 (0x01U) +#define TCA9539_REG_OUTPUT_PORT0 (0x02U) +#define TCA9539_REG_OUTPUT_PORT1 (0x03U) +#define TCA9539_REG_INVERT_PORT0 (0x04U) +#define TCA9539_REG_INVERT_PORT1 (0x05U) +#define TCA9539_REG_CONFIG_PORT0 (0x06U) +#define TCA9539_REG_CONFIG_PORT1 (0x07U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Port_Definition TCA9539 Port Definition + * @{ + */ +#define TCA9539_IO_PORT0 (0x00U) +#define TCA9539_IO_PORT1 (0x01U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition + * @{ + */ +#define TCA9539_IO_PIN0 (0x01U) +#define TCA9539_IO_PIN1 (0x02U) +#define TCA9539_IO_PIN2 (0x04U) +#define TCA9539_IO_PIN3 (0x08U) +#define TCA9539_IO_PIN4 (0x10U) +#define TCA9539_IO_PIN5 (0x20U) +#define TCA9539_IO_PIN6 (0x40U) +#define TCA9539_IO_PIN7 (0x80U) +#define TCA9539_IO_PIN_ALL (0xFFU) +/** + * @} + */ + +/** + * @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition + * @{ + */ +#define TCA9539_DIR_OUT (0x00U) +#define TCA9539_DIR_IN (0x01U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition + * @{ + */ +#define TCA9539_PIN_RESET (0x00U) +#define TCA9539_PIN_SET (0x01U) +/** + * @} + */ + +/** + * @defgroup HC32F4A0_EV_IO_Function_Sel Expand IO function definition + * @{ + */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ +#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ + +#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ +#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ +#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ +#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ +#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +/** + * @} + */ + +/** + * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition + * @{ + */ +#define LED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) +/** + * @} + */ + +/** + * @defgroup BSP CAN PHY STB port/pin definition + * @{ + */ +#define CAN_STB_PORT (TCA9539_IO_PORT1) +#define CAN_STB_PIN (EIO_CAN_STB) +/** + * @} + */ + +int TCA9539_Init(void); +rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState); +rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState); +rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin); +rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir); + +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/figures/board.png b/bsp/hc32/lckfb-hc32f4a0-lqfp100/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..0d356ad184d257affcfc0187ee86c2951655132d GIT binary patch literal 871042 zcmd42b95wMy9OHDPA0Z(+fHU;JDJ$FZB1-UoQXQN&53QBw}0n5=X~E;>)!uwuUf0S zs&{o&?cT4R=XoQQ6{Qg2@Zdl|KoDi5#Z^H-Ab}sjwPC=3Z(3q*@W3}vXH_XtkeVs{ z6W|Vng@}R(2uOWA{JRlw=vTXpxQM!k{&@~`K8D2Husdg`_>>_S1S%*?vIuiPxv2_^ z_tpk3BMu1UV2qZMK;ven^Hhe6F>fOp#3)$O9sIY$x34Pm!wY!&{QTo8qC0c%_A21Z zJFO;XRcqLFBca}k^<$4aE}hk9LTHuc%XIiXncz;z?f-oz=VG6T)^(%VW;yI(g&Cp$ zzqii>OL79Jq<i%bJ*v;^;WtotNV|ek;LqAqzC!W;s1H5?_lu%`A~uXd17kM|K}~JP}G6^d-}@J zG(mp;_p^r?sl)#N?Q(vUcB_-j2zy+^n<>C)YcTm|GW|7Kv4c($z7@Bi|5a-I*ZkEh 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### uVision Project, (C) Keil Software
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..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll.c + + + hc32f4a0_ll_interrupts_share.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32f4a0_ll_interrupts_share.c + + + hc32_ll_sram.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_sram.c + + + hc32_ll_rmu.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_rmu.c + + + system_hc32f4a0.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f4a0.c + + + hc32_ll_pwc.c + 1 + ..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_pwc.c + + + + + + + + + + + + + + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h new file mode 100644 index 0000000000..eec81b94d9 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h @@ -0,0 +1,354 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +/* end of kservice optimization */ + +/* klibc optimization */ + +/* end of klibc optimization */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_HC32 +#define SOC_SERIES_HC32F4 + +/* Hardware Drivers Config */ + +#define SOC_HC32F4A0SI + +/* On-chip Drivers */ + +#define BSP_USING_ON_CHIP_FLASH_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH +/* end of On-chip Drivers */ + +/* Onboard Peripheral Drivers */ + +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py new file mode 100644 index 0000000000..568d50f2a6 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + else: + EXEC_PATH = r'C:/Users/XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.ewp b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.ewp new file mode 100644 index 0000000000..28a74860dc --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.ewp @@ -0,0 +1,1927 @@ + + + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.eww b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvoptx b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvoptx new file mode 100644 index 0000000000..42535c50ec --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD1FFE0000 -FF0HC32F4A0_2M -FF1HC32F4A0_otp -FL0200000 -FL11800 -FS00 -FS13000000 -FP0($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_2M.FLM) -FP1($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_otp.FLM) + + + 0 + CMSIS_AGDI + -X"LCKFB-CMSIS-DAP" -ULCKFB-V1.0.0-8437443312050767921 -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_2M.FLM) -FF1HC32F4A0_otp.FLM -FS13000000 -FL11800 -FP1($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_otp.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvprojx b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvprojx new file mode 100644 index 0000000000..591f3cb5cc --- /dev/null +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/template.uvprojx @@ -0,0 +1,392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + HC32F4A0PITB + HDSC + HDSC.HC32F4A0.1.0.5 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IRAM(0x1FFE0000,0x80000) IROM(0x00000000,0x200000) IROM2(0x03000000,0x1800) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F4A0_2M -FS00 -FL0200000 -FF1HC32F4A0_otp -FS13000000 -FL11800 -FP0($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_2M.FLM) -FP1($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_otp.FLM)) + 0 + $$Device:HC32F4A0PITB$Device\Include\HC32F4A0PITB.h + + + + + + + + + + $$Device:HC32F4A0PITB$SVD\HDSC_HC32F4A0PITB.svd + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 8 + 0 + 0 + 0 + 0 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1ffe0000 + 0x80000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x3000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1ffe0000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + +