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add_raspi4_uart

This commit is contained in:
bigmagic 2020-05-26 13:34:02 +08:00
parent b377859946
commit db0b00d12a
10 changed files with 422 additions and 48 deletions
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6
bsp/raspberry-pi/raspi4-32/.config
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@ -65,7 +65,7 @@ CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart" CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40003 CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set # CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARMV8=y CONFIG_ARCH_ARMV8=y
@ -437,6 +437,10 @@ CONFIG_BCM2711_SOC=y
# #
CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART0=y CONFIG_RT_USING_UART0=y
# CONFIG_RT_USING_UART1 is not set
CONFIG_RT_USING_UART3=y
CONFIG_RT_USING_UART4=y
# CONFIG_RT_USING_UART5 is not set
CONFIG_BSP_USING_GIC=y CONFIG_BSP_USING_GIC=y
CONFIG_BSP_USING_GIC400=y CONFIG_BSP_USING_GIC400=y
# CONFIG_BSP_USING_GIC500 is not set # CONFIG_BSP_USING_GIC500 is not set

3
bsp/raspberry-pi/raspi4-32/README.md
View File

@ -47,6 +47,7 @@ enable_uart=1
arm_64bit=0 arm_64bit=0
kernel_addr=0x8000 kernel_addr=0x8000
kernel=kernel7.img kernel=kernel7.img
core_freq=250
``` ```
按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息： 按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：
@ -66,7 +67,7 @@ msh />
| 驱动 | 支持情况 | 备注 | | 驱动 | 支持情况 | 备注 |
| ------ | ---- | :------: | | ------ | ---- | :------: |
| UART | 支持 | UART0| | UART | 支持 | UART0,UART2,UART3,UART4,UART5 |
## 5. 联系人信息 ## 5. 联系人信息

16
bsp/raspberry-pi/raspi4-32/driver/Kconfig
View File

@ -14,6 +14,22 @@ menu "Hardware Drivers Config"
config RT_USING_UART0 config RT_USING_UART0
bool "Enabel UART 0" bool "Enabel UART 0"
default y default y
config RT_USING_UART1
bool "Enabel UART 1"
default n
config RT_USING_UART3
bool "Enabel UART 3"
default n
config RT_USING_UART4
bool "Enabel UART 4"
default n
config RT_USING_UART5
bool "Enabel UART 5"
default n
endif endif
menuconfig BSP_USING_GIC menuconfig BSP_USING_GIC

34
bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c
View File

@ -11,13 +11,36 @@
#include "drv_gpio.h" #include "drv_gpio.h"
#ifdef BSP_USING_PIN #ifdef BSP_USING_PIN
void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode)
static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
{ {
uint32_t fselnum = pin / 10; uint32_t fselnum = pin / 10;
uint32_t fselrest = pin % 10; uint32_t fselrest = pin % 10;
uint32_t gpfsel = 0; uint32_t gpfsel = 0;
switch (fselnum)
{
case 0:
gpfsel = GPIO_REG_GPFSEL0(GPIO_BASE);
break;
case 1:
gpfsel = GPIO_REG_GPFSEL1(GPIO_BASE);
break;
case 2:
gpfsel = GPIO_REG_GPFSEL2(GPIO_BASE);
break;
case 3:
gpfsel = GPIO_REG_GPFSEL3(GPIO_BASE);
break;
case 4:
gpfsel = GPIO_REG_GPFSEL4(GPIO_BASE);
break;
case 5:
gpfsel = GPIO_REG_GPFSEL5(GPIO_BASE);
break;
default:
break;
}
gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3))); gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
gpfsel |= (uint32_t)(mode << (fselrest * 3)); gpfsel |= (uint32_t)(mode << (fselrest * 3));
@ -46,6 +69,11 @@ static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
} }
} }
static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
{
prev_raspi_pin_mode((GPIO_PIN)pin, (GPIO_FUNC)mode);
}
static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value) static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
{ {
uint32_t num = pin / 32; uint32_t num = pin / 32;

46
bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h
View File

@ -60,6 +60,50 @@
#define GPIO_REG_REV9(BASE) HWREG32(BASE + 0xA0) #define GPIO_REG_REV9(BASE) HWREG32(BASE + 0xA0)
#define GPIO_REG_TEST(BASE) HWREG32(BASE + 0xA4) #define GPIO_REG_TEST(BASE) HWREG32(BASE + 0xA4)
typedef enum {
GPIO_PIN_0,
GPIO_PIN_1,
GPIO_PIN_2,
GPIO_PIN_3,
GPIO_PIN_4,
GPIO_PIN_5,
GPIO_PIN_6,
GPIO_PIN_7,
GPIO_PIN_8,
GPIO_PIN_9,
GPIO_PIN_10,
GPIO_PIN_11,
GPIO_PIN_12,
GPIO_PIN_13,
GPIO_PIN_14,
GPIO_PIN_15,
GPIO_PIN_16,
GPIO_PIN_17,
GPIO_PIN_18,
GPIO_PIN_19,
GPIO_PIN_20,
GPIO_PIN_21,
GPIO_PIN_22,
GPIO_PIN_23,
GPIO_PIN_24,
GPIO_PIN_25,
GPIO_PIN_26,
GPIO_PIN_27,
GPIO_PIN_28,
GPIO_PIN_29,
GPIO_PIN_30,
GPIO_PIN_31,
GPIO_PIN_32,
GPIO_PIN_33,
GPIO_PIN_34,
GPIO_PIN_35,
GPIO_PIN_36,
GPIO_PIN_37,
GPIO_PIN_38,
GPIO_PIN_39,
GPIO_PIN_40,
} GPIO_PIN;
typedef enum { typedef enum {
INPUT = 0b000, INPUT = 0b000,
OUTPUT = 0b001, OUTPUT = 0b001,
@ -71,7 +115,7 @@ typedef enum {
ALT5 = 0b010 ALT5 = 0b010
} GPIO_FUNC; } GPIO_FUNC;
void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode);
int rt_hw_gpio_init(void); int rt_hw_gpio_init(void);
#endif /* __DRV_GPIO_H__ */ #endif /* __DRV_GPIO_H__ */

280
bsp/raspberry-pi/raspi4-32/driver/drv_uart.c
View File

@ -6,6 +6,7 @@
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2020-04-16 bigmagic first version * 2020-04-16 bigmagic first version
* 2020-05-26 bigmagic add other uart
*/ */
#include <rthw.h> #include <rthw.h>
@ -16,6 +17,26 @@
#include "drv_uart.h" #include "drv_uart.h"
#include "drv_gpio.h" #include "drv_gpio.h"
#ifdef RT_USING_UART0
static struct rt_serial_device _serial0;
#endif
#ifdef RT_USING_UART1
static struct rt_serial_device _serial1;
#endif
#ifdef RT_USING_UART3
static struct rt_serial_device _serial3;
#endif
#ifdef RT_USING_UART4
static struct rt_serial_device _serial4;
#endif
#ifdef RT_USING_UART5
static struct rt_serial_device _serial5;
#endif
struct hw_uart_device struct hw_uart_device
{ {
rt_ubase_t hw_base; rt_ubase_t hw_base;
@ -30,26 +51,54 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data; uart = (struct hw_uart_device *)serial->parent.user_data;
if(uart->hw_base == PL011_BASE)
if(uart->hw_base == AUX_BASE)
{ {
uint32_t gpfsel = 0; prev_raspi_pin_mode(GPIO_PIN_14, ALT5);
prev_raspi_pin_mode(GPIO_PIN_15, ALT5);
gpfsel &= ~((uint32_t)(0x07 << (4 * 3))); AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */
gpfsel |= (uint32_t)(ALT0 << (4 * 3)); AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */
GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel; AUX_MU_CNTL_REG(uart->hw_base) = 0; /* Disable Transmitter and Receiver */
AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */
gpfsel &= ~((uint32_t)(0x07 << (5 * 3))); AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */
gpfsel |= (uint32_t)(ALT0 << (5 * 3)); AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */
GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel; AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */
PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/ return RT_EOK;
PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
PL011_REG_IBRD(uart->hw_base) = ibrd;
PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
} }
if(uart->hw_base == UART0_BASE)
{
prev_raspi_pin_mode(GPIO_PIN_14, ALT0);
prev_raspi_pin_mode(GPIO_PIN_15, ALT0);
}
if(uart->hw_base == UART3_BASE)
{
prev_raspi_pin_mode(GPIO_PIN_4, ALT4);
prev_raspi_pin_mode(GPIO_PIN_5, ALT4);
}
if(uart->hw_base == UART4_BASE)
{
prev_raspi_pin_mode(GPIO_PIN_8, ALT4);
prev_raspi_pin_mode(GPIO_PIN_9, ALT4);
}
if(uart->hw_base == UART5_BASE)
{
prev_raspi_pin_mode(GPIO_PIN_12, ALT4);
prev_raspi_pin_mode(GPIO_PIN_13, ALT4);
}
PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
PL011_REG_IBRD(uart->hw_base) = ibrd;
PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
return RT_EOK; return RT_EOK;
} }
@ -64,17 +113,30 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
{ {
case RT_DEVICE_CTRL_CLR_INT: case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */ /* disable rx irq */
PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM); if(uart->hw_base == AUX_BASE)
{
AUX_MU_IER_REG(uart->hw_base) = 0x0;
}
else
{
PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM);
}
rt_hw_interrupt_mask(uart->irqno); rt_hw_interrupt_mask(uart->irqno);
break; break;
case RT_DEVICE_CTRL_SET_INT: case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */ /* enable rx irq */
PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM; if(uart->hw_base == AUX_BASE)
{
AUX_MU_IER_REG(uart->hw_base) = 0x1;
}
else
{
PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
}
rt_hw_interrupt_umask(uart->irqno); rt_hw_interrupt_umask(uart->irqno);
break; break;
} }
return RT_EOK; return RT_EOK;
} }
@ -84,10 +146,16 @@ static int uart_putc(struct rt_serial_device *serial, char c)
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data; uart = (struct hw_uart_device *)serial->parent.user_data;
if(uart->hw_base == AUX_BASE)
while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF)); {
PL011_REG_DR(uart->hw_base) = (uint8_t)c; while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
AUX_MU_IO_REG(uart->hw_base) = c;
}
else
{
while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
PL011_REG_DR(uart->hw_base) = (uint8_t)c;
}
return 1; return 1;
} }
@ -99,9 +167,19 @@ static int uart_getc(struct rt_serial_device *serial)
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data; uart = (struct hw_uart_device *)serial->parent.user_data;
if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0) if(uart->hw_base == AUX_BASE)
{ {
ch = PL011_REG_DR(uart->hw_base) & 0xff; if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
{
ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
}
}
else
{
if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
{
ch = PL011_REG_DR(uart->hw_base) & 0xff;
}
} }
return ch; return ch;
@ -115,38 +193,166 @@ static const struct rt_uart_ops _uart_ops =
uart_getc, uart_getc,
}; };
static void rt_hw_uart_isr(int irqno, void *param) #ifdef RT_USING_UART1
static void rt_hw_aux_uart_isr(int irqno, void *param)
{ {
struct rt_serial_device *serial = (struct rt_serial_device*)param; struct rt_serial_device *serial = (struct rt_serial_device*)param;
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE; }
#endif
static void rt_hw_uart_isr(int irqno, void *param)
{
#ifdef RT_USING_UART0
if((PACTL_CS & IRQ_UART0) == IRQ_UART0)
{
PACTL_CS &= ~(IRQ_UART0);
rt_hw_serial_isr(&_serial0, RT_SERIAL_EVENT_RX_IND);
PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
}
#endif
#ifdef RT_USING_UART3
if((PACTL_CS & IRQ_UART3) == IRQ_UART3)
{
PACTL_CS &= ~(IRQ_UART3);
rt_hw_serial_isr(&_serial3, RT_SERIAL_EVENT_RX_IND);
PL011_REG_ICR(UART3_BASE) = PL011_INTERRUPT_RECEIVE;
}
#endif
#ifdef RT_USING_UART4
if((PACTL_CS & IRQ_UART4) == IRQ_UART4)
{
PACTL_CS &= ~(IRQ_UART4);
rt_hw_serial_isr(&_serial4, RT_SERIAL_EVENT_RX_IND);
PL011_REG_ICR(UART4_BASE) = PL011_INTERRUPT_RECEIVE;
}
#endif
#ifdef RT_USING_UART5
if((PACTL_CS & IRQ_UART5) == IRQ_UART5)
{
PACTL_CS &= ~(IRQ_UART5);
rt_hw_serial_isr(&_serial5, RT_SERIAL_EVENT_RX_IND);
PL011_REG_ICR(UART5_BASE) = PL011_INTERRUPT_RECEIVE;
}
#endif
} }
#ifdef RT_USING_UART0
/* UART device driver structure */ /* UART device driver structure */
static struct hw_uart_device _uart0_device = static struct hw_uart_device _uart0_device =
{ {
PL011_BASE, UART0_BASE,
IRQ_PL011, IRQ_PL011,
}; };
#endif
static struct rt_serial_device _serial0; #ifdef RT_USING_UART1
/* UART device driver structure */
static struct hw_uart_device _uart1_device =
{
AUX_BASE,
IRQ_AUX_UART,
};
#endif
#ifdef RT_USING_UART3
static struct hw_uart_device _uart3_device =
{
UART3_BASE,
IRQ_PL011,
};
#endif
#ifdef RT_USING_UART4
static struct hw_uart_device _uart4_device =
{
UART4_BASE,
IRQ_PL011,
};
#endif
#ifdef RT_USING_UART5
static struct hw_uart_device _uart5_device =
{
UART5_BASE,
IRQ_PL011,
};
#endif
int rt_hw_uart_init(void) int rt_hw_uart_init(void)
{ {
struct hw_uart_device *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef RT_USING_UART0
uart = &_uart0_device; struct hw_uart_device *uart0;
uart0 = &_uart0_device;
_serial0.ops = &_uart_ops; _serial0.ops = &_uart_ops;
_serial0.config = config; _serial0.config = config;
/* register UART1 device */ /* register UART0 device */
rt_hw_serial_register(&_serial0, "uart", rt_hw_serial_register(&_serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart); uart0);
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart"); rt_hw_interrupt_install(uart0->irqno, rt_hw_uart_isr, &_serial0, "uart0");
#endif
#ifdef RT_USING_UART1
struct hw_uart_device *uart1;
uart1 = &_uart1_device;
_serial1.ops = &_uart_ops;
_serial1.config = config;
/* register UART1 device */
rt_hw_serial_register(&_serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart1);
rt_hw_interrupt_install(uart1->irqno, rt_hw_aux_uart_isr, &_serial1, "uart1");
#endif
#ifdef RT_USING_UART3
struct hw_uart_device *uart3;
uart3 = &_uart3_device;
_serial3.ops = &_uart_ops;
_serial3.config = config;
/* register UART3 device */
rt_hw_serial_register(&_serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart3);
rt_hw_interrupt_install(uart3->irqno, rt_hw_uart_isr, &_serial3, "uart3");
#endif
#ifdef RT_USING_UART4
struct hw_uart_device *uart4;
uart4 = &_uart4_device;
_serial4.ops = &_uart_ops;
_serial4.config = config;
/* register UART4 device */
rt_hw_serial_register(&_serial4, "uart4",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart4);
rt_hw_interrupt_install(uart4->irqno, rt_hw_uart_isr, &_serial4, "uart4");
#endif
#ifdef RT_USING_UART5
struct hw_uart_device *uart5;
uart5 = &_uart5_device;
_serial5.ops = &_uart_ops;
_serial5.config = config;
/* register UART5 device */
rt_hw_serial_register(&_serial5, "uart5",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart5);
rt_hw_interrupt_install(uart5->irqno, rt_hw_uart_isr, &_serial5, "uart5");
#endif
return 0; return 0;
} }

24
bsp/raspberry-pi/raspi4-32/driver/drv_uart.h
View File

@ -78,6 +78,30 @@
#define PL011_REG_ITOP(BASE) HWREG32(BASE + 0x88) #define PL011_REG_ITOP(BASE) HWREG32(BASE + 0x88)
#define PL011_REG_TDR(BASE) HWREG32(BASE + 0x8C) #define PL011_REG_TDR(BASE) HWREG32(BASE + 0x8C)
/*
* Auxiliary
*/
#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */
#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */
#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */
#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */
#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */
#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */
#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */
#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */
#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */
#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */
#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */
#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */
#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */
#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */
#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */
#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */
#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */
#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */
#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */
#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */
int rt_hw_uart_init(void); int rt_hw_uart_init(void);
#endif /* DRV_UART_H__ */ #endif /* DRV_UART_H__ */

56
bsp/raspberry-pi/raspi4-32/driver/raspi4.h
View File

@ -11,8 +11,24 @@
/* base address */ /* base address */
#define PER_BASE (0xFE000000) #define PER_BASE (0xFE000000)
//gpio offset
#define GPIO_BASE_OFFSET (0x00200000)
//pl011 offset
#define PL011_UART0_BASE_OFFSET (0x00201000)
#define PL011_UART2_BASE_OFFSET (0x00201400)
#define PL011_UART3_BASE_OFFSET (0x00201600)
#define PL011_UART4_BASE_OFFSET (0x00201800)
#define PL011_UART5_BASE_OFFSET (0x00201A00)
//pactl cs offset
#define PACTL_CS_OFFSET (0x00204E00)
//aux offset
#define AUX_BASE_OFFSET (0x00215000)
/* GPIO */ /* GPIO */
#define GPIO_BASE (PER_BASE + 0x00200000) #define GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET)
/* Timer (ARM side) */ /* Timer (ARM side) */
#define ARM_TIMER_IRQ (64) #define ARM_TIMER_IRQ (64)
@ -28,11 +44,43 @@
#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420) #define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420)
/* UART PL011 */ /* UART PL011 */
#define UART0_BASE (PER_BASE + 0x00201000) #define UART0_BASE (PER_BASE + PL011_UART0_BASE_OFFSET)
#define PL011_BASE UART0_BASE #define UART2_BASE (PER_BASE + PL011_UART2_BASE_OFFSET)
#define IRQ_PL011 (96 + 57) #define UART3_BASE (PER_BASE + PL011_UART3_BASE_OFFSET)
#define UART4_BASE (PER_BASE + PL011_UART4_BASE_OFFSET)
#define UART5_BASE (PER_BASE + PL011_UART5_BASE_OFFSET)
#define IRQ_AUX_UART (96 + 29)
#define UART_REFERENCE_CLOCK (48000000) #define UART_REFERENCE_CLOCK (48000000)
/* AUX */
#define AUX_BASE (PER_BASE + AUX_BASE_OFFSET)
#define IRQ_PL011 (96 + 57)
/* Peripheral IRQ OR-ing */
#define PACTL_CS HWREG32((PER_BASE + PACTL_CS_OFFSET))
typedef enum {
IRQ_SPI0 = 0x00000000,
IRQ_SPI1 = 0x00000002,
IRQ_SPI2 = 0x00000004,
IRQ_SPI3 = 0x00000008,
IRQ_SPI4 = 0x00000010,
IRQ_SPI5 = 0x00000020,
IRQ_SPI6 = 0x00000040,
IRQ_I2C0 = 0x00000100,
IRQ_I2C1 = 0x00000200,
IRQ_I2C2 = 0x00000400,
IRQ_I2C3 = 0x00000800,
IRQ_I2C4 = 0x00001000,
IRQ_I2C5 = 0x00002000,
IRQ_I2C6 = 0x00004000,
IRQ_I2C7 = 0x00008000,
IRQ_UART5 = 0x00010000,
IRQ_UART4 = 0x00020000,
IRQ_UART3 = 0x00040000,
IRQ_UART2 = 0x00080000,
IRQ_UART0 = 0x00100000
} PACTL_CS_VAL;
// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control // 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
#define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040) #define CORE0_TIMER_IRQ_CTRL HWREG32(0xFF800040)
#define TIMER_IRQ 30 #define TIMER_IRQ 30

4
bsp/raspberry-pi/raspi4-32/rtconfig.h
View File

@ -40,7 +40,7 @@
#define RT_USING_DEVICE #define RT_USING_DEVICE
#define RT_USING_CONSOLE #define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart" #define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40003 #define RT_VER_NUM 0x40003
#define ARCH_ARMV8 #define ARCH_ARMV8
@ -162,6 +162,8 @@
#define BSP_USING_UART #define BSP_USING_UART
#define RT_USING_UART0 #define RT_USING_UART0
#define RT_USING_UART3
#define RT_USING_UART4
#define BSP_USING_GIC #define BSP_USING_GIC
#define BSP_USING_GIC400 #define BSP_USING_GIC400
#define BSP_USING_PIN #define BSP_USING_PIN

1
bsp/raspberry-pi/raspi4-64/README.md
View File

@ -81,6 +81,7 @@ EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'
enable_uart=1 enable_uart=1
arm_64bit=1 arm_64bit=1
kernel=rtthread.bin kernel=rtthread.bin
core_freq=250
``` ```
按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息： 按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：