[bsp][ab32vg1] Add env config to choose whether use internal clock

This commit is contained in:
iysheng 2021-03-23 10:21:01 +08:00
parent 011564e1eb
commit d8e906e6c8
3 changed files with 29 additions and 10 deletions

View File

@ -167,11 +167,16 @@ menu "On-chip Peripheral Drivers"
default n
endif
config BSP_USING_ONCHIP_RTC
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
if BSP_USING_ONCHIP_RTC
config RTC_USING_INTERNAL_CLK
bool "Using internal clock RTC"
default y
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"

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@ -96,18 +96,33 @@ uint8_t irtc_sfr_read(uint32_t cmd)
IRTC_EXIT_CRITICAL();
}
static void _init_rtc_clock(void)
{
uint8_t rtccon0;
uint8_t rtccon2;
rtccon0 = irtc_sfr_read(RTCCON0_CMD);
rtccon2 = irtc_sfr_read(RTCCON2_CMD);
#ifdef RTC_USING_INTERNAL_CLK
rtccon0 &= ~RTC_CON0_XOSC32K_ENABLE;
rtccon0 |= RTC_CON0_INTERNAL_32K;
rtccon2 | RTC_CON2_32K_SELECT;
#else
rtccon0 |= RTC_CON0_XOSC32K_ENABLE;
rtccon0 &= ~RTC_CON0_INTERNAL_32K;
rtccon2 & ~RTC_CON2_32K_SELECT;
#endif
irtc_sfr_write(RTCCON0_CMD, rtccon0);
irtc_sfr_write(RTCCON2_CMD, rtccon2);
}
void hal_rtc_init(void)
{
time_t sec = 0;
struct tm tm_new = {0};
uint8_t temp;
uint8_t temp = irtc_sfr_read(RTCCON0_CMD);
temp &= ~RTC_CON0_XOSC32K_ENABLE;
temp |= RTC_CON0_EXTERNAL_32K;
irtc_sfr_write(RTCCON0_CMD, temp);
temp = irtc_sfr_read(RTCCON2_CMD);
irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT);
_init_rtc_clock();
temp = irtc_sfr_read(RTCCON0_CMD);
if (temp & RTC_CON0_PWRUP_FIRST) {
temp &= ~RTC_CON0_PWRUP_FIRST;
@ -119,7 +134,6 @@ void hal_rtc_init(void)
irtc_time_write(RTCCNT_CMD, sec);
}
}
/************** HAL End *******************/

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@ -34,7 +34,7 @@ enum
// RTCCON0
#define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */
#define RTC_CON0_EXTERNAL_32K (0x01u << 6) /*!< External 32K select */
#define RTC_CON0_INTERNAL_32K (0x01u << 6) /*!< Internal 32K select */
#define RTC_CON0_VDD_ENABLE (0x01u << 5) /*!< RTC VDD12 enable */
#define RTC_CON0_BG_ENABLE (0x01u << 4) /*!< BG enable */
#define RTC_CON0_LVD_OUTPUT_ENABLE (0x01u << 3) /*!< LVD output enable */