From d8d0af9143bc40c017aa7d9833b6a87e5d843968 Mon Sep 17 00:00:00 2001
From: Chen Wang <unicorn_wang@outlook.com>
Date: Mon, 13 May 2024 08:05:34 +0800
Subject: [PATCH] bsp:cvitek: add calibration for adc

The ADC controller needs to be calibrated during the initialization
phase, otherwise the measured voltage value will be inaccurate.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
 bsp/cvitek/drivers/drv_adc.c |  8 +++++++-
 bsp/cvitek/drivers/drv_adc.h | 18 ++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/bsp/cvitek/drivers/drv_adc.c b/bsp/cvitek/drivers/drv_adc.c
index 39440cd49a..242d2216eb 100644
--- a/bsp/cvitek/drivers/drv_adc.c
+++ b/bsp/cvitek/drivers/drv_adc.c
@@ -103,7 +103,13 @@ static const struct rt_adc_ops _adc_ops =
 int rt_hw_adc_init(void)
 {
     rt_uint8_t i;
-    for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i ++)
+
+    for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++)
+    {
+        cvi_do_calibration(adc_dev_config[i].base);
+    }
+
+    for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i++)
     {
         if (rt_hw_adc_register(&adc_dev_config[i].device, adc_dev_config[i].name, &_adc_ops, &adc_dev_config[i]) != RT_EOK)
         {
diff --git a/bsp/cvitek/drivers/drv_adc.h b/bsp/cvitek/drivers/drv_adc.h
index 7539ab5604..3ef86a2ecb 100644
--- a/bsp/cvitek/drivers/drv_adc.h
+++ b/bsp/cvitek/drivers/drv_adc.h
@@ -48,6 +48,11 @@
 #define SARADC_RESULT_MASK                  0x0FFF
 #define SARADC_RESULT_VALID                 (1 << 15)
 
+#define SARADC_TEST_OFFSET                  0x030
+#define SARADC_TEST_VREFSEL_BIT             2
+
+#define SARADC_TRIM_OFFSET                  0x034
+
 rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
 {
     value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET);
@@ -78,6 +83,19 @@ rt_inline void cvi_set_cyc(unsigned long reg_base)
     mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
 }
 
+rt_inline void cvi_do_calibration(unsigned long reg_base)
+{
+    rt_uint32_t val;
+
+    val = mmio_read_32(reg_base + SARADC_TEST_OFFSET);
+    val |= 1 << SARADC_TEST_VREFSEL_BIT;
+    mmio_write_32(reg_base + SARADC_TEST_OFFSET, val);
+
+    val = mmio_read_32(reg_base + SARADC_TRIM_OFFSET);
+    val |= 0x4;
+    mmio_write_32(reg_base + SARADC_TRIM_OFFSET, val);
+}
+
 int rt_hw_adc_init(void);
 
 #endif /* __DRV_ADC_H__ */