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mips:gs232:LS1C300 have 5 group INTC cells but LS1B have 4 group INTC cells

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This commit is contained in:
michael 2021-01-31 21:56:30 +08:00
parent 0af3666882
commit d874ab1109
3 changed files with 10 additions and 3 deletions
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2
bsp/ls1cdev/Kconfig
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@ -19,7 +19,7 @@ source "$RTT_DIR/Kconfig"
source "$RTT_DIR/libcpu/mips/common/Kconfig" source "$RTT_DIR/libcpu/mips/common/Kconfig"
source "$PKGS_DIR/Kconfig" source "$PKGS_DIR/Kconfig"
config SOC_1C300 config SOC_LS1C300
bool bool
select RT_USING_COMPONENTS_INIT select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN select RT_USING_USER_MAIN

2
bsp/ls1cdev/rtconfig.h
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@ -161,7 +161,7 @@
/* samples: kernel and components samples */ /* samples: kernel and components samples */
#define SOC_1C300 #define SOC_LS1C300
#define RT_LS1C_BAICAIBOARD #define RT_LS1C_BAICAIBOARD
#define RT_USING_SELF_BOOT #define RT_USING_SELF_BOOT
#define RT_SELF_BOOT_DEBUG #define RT_SELF_BOOT_DEBUG

7
libcpu/mips/gs232/gs232.h
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@ -17,7 +17,14 @@
#define INTC_BASE 0xBFD01040 #define INTC_BASE 0xBFD01040
#ifdef SOC_LS1B
#define GS232_INTC_CELLS 4
#endif
#ifdef SOC_LS1C300
#define GS232_INTC_CELLS 5 #define GS232_INTC_CELLS 5
#endif
#define GS232_NR_IRQS (32 * GS232_INTC_CELLS) #define GS232_NR_IRQS (32 * GS232_INTC_CELLS)
#define GMAC0_BASE 0xBFE10000 #define GMAC0_BASE 0xBFE10000