diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript index 32d7aa7085..7e9b391e3e 100644 --- a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript @@ -54,7 +54,7 @@ if GetDepend('RT_USING_USB_DEVICE'): src += Glob('usb/phy/*.c') CPPDEFINES += ['ENDIANNESS'] -if GetDepend('BOARD_RT1050_EVK') or GetDepend('BOARD_RT1050_SeeedStudio'): +if GetDepend('BOARD_RT1050_EVK'): if GetDepend('RT_USING_LWIP'): src += ['drv_eth.c', 'fsl_phy.c'] CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE'] diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth.c index a884d8d065..6ea1e16d6e 100644 --- a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth.c +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_eth.c @@ -43,7 +43,7 @@ #define PHY_ADDRESS 0x00u #endif -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) +#if defined(BOARD_RT1050_EVK) #define PHY_ADDRESS 0x02u #endif /* debug option */ @@ -137,7 +137,7 @@ void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, break; } } -#if defined(BOARD_RT1050_SeeedStudio) || defined(BOARD_RT1050_EVK) +#if defined(BOARD_RT1050_EVK) static void evk_enet_io_init(void) { CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ @@ -1127,7 +1127,7 @@ static int rt_hw_imxrt_eth_init(void) fire_enet_io_init(); #endif -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) +#if defined(BOARD_RT1050_EVK) evk_enet_io_init(); #endif _enet_clk_init(); diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.c b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.c index b10b1e6cd8..a8f3d2f3b2 100644 --- a/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.c +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.c @@ -328,7 +328,7 @@ status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t * #if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg); #endif -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) +#if defined(BOARD_RT1050_EVK) result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); #endif if (result == kStatus_Success) diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.h b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.h index a1b4f5f89b..8de59535d6 100644 --- a/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.h +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/fsl_phy.h @@ -56,7 +56,7 @@ #if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) #define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/ #endif -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) +#if defined(BOARD_RT1050_EVK) #define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ #endif /*! @brief Defines the mask flag in basic control register. */ @@ -83,7 +83,7 @@ #define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ #define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) #endif -#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) +#if defined(BOARD_RT1050_EVK) #define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ #define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ #define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ diff --git a/bsp/imxrt/imxrt1050-ArchMix/.config b/bsp/imxrt/imxrt1050-ArchMix/.config new file mode 100644 index 0000000000..3406bd3ee8 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/.config @@ -0,0 +1,420 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_CORTEXM=y +CONFIG_RT_USING_I2C=y +CONFIG_RT_USING_I2C_BITOPS=y +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_MTD is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RTC_SYNC_USING_NTP is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_W25QXX is not set +# CONFIG_RT_USING_GD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using WiFi +# +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_POSIX is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# ARM CMSIS +# +# CONFIG_RT_USING_CMSIS_OS is not set +# CONFIG_RT_USING_RTT_CMSIS is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_BEEPPLAYER is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set + +# +# sample package +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_SOC_IMXRT1052=y +CONFIG_BOARD_RT1050_ArchMix=y +# CONFIG_BOARD_USING_HYPERFLASH is not set +CONFIG_BOARD_USING_QSPIFLASH=y + +# +# RT1050 Bsp Config +# + +# +# Select uart drivers +# +CONFIG_RT_USING_UART1=y +# CONFIG_RT_USING_UART2 is not set +# CONFIG_RT_USING_UART3 is not set +# CONFIG_RT_USING_UART8 is not set + +# +# Select spi bus and dev drivers +# +CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD1=y +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL3PFD0 is not set +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2 is not set +# CONFIG_LPSPI_CLK_SOURCE_FROM_PLL2PFD2 is not set +CONFIG_LPSPI_CLK_SOURCE=0 +CONFIG_LPSPI_CLK_SOURCE_DIVIDER=8 +# CONFIG_RT_USING_SPIBUS3 is not set +CONFIG_RT_USING_SPIBUS4=y +CONFIG_LPSPI4_SCK_GPIO_2=y +CONFIG_LPSPI4_SDO_GPIO_2=y +CONFIG_LPSPI4_SDI_GPIO_2=y +# CONFIG_RT_USING_SPI_FLASH is not set + +# +# Select iic bus drivers +# +CONFIG_RT_USING_HW_I2C1=y +CONFIG_HW_I2C1_BADURATE_100kHZ=y +# CONFIG_HW_I2C1_BADURATE_400kHZ is not set +# CONFIG_RT_USING_HW_I2C3 is not set +# CONFIG_RT_USING_HW_I2C4 is not set + +# +# Select lcd driver +# + +# +# Notice: Arch Mix Board para: 480*272 4 4 8 2 40 10 127 45 +# +CONFIG_RT_USING_LCD=y +CONFIG_LCD_WIDTH=480 +CONFIG_LCD_HEIGHT=272 +CONFIG_LCD_HFP=4 +CONFIG_LCD_VFP=4 +CONFIG_LCD_HBP=8 +CONFIG_LCD_VBP=2 +CONFIG_LCD_HSW=40 +CONFIG_LCD_VSW=10 +CONFIG_LCD_BL_PIN=127 +CONFIG_LCD_RST_PIN=45 +CONFIG_RT_USING_SDRAM=y +CONFIG_RT_USING_RTC_HP=y diff --git a/bsp/imxrt/imxrt1050-ArchMix/Kconfig b/bsp/imxrt/imxrt1050-ArchMix/Kconfig new file mode 100644 index 0000000000..89c79cc4e4 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/Kconfig @@ -0,0 +1,308 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +config SOC_IMXRT1052 + bool + select ARCH_ARM_CORTEX_M7 + select ARCH_ARM_CORTEX_FPU + default y + +# RT1050 board config! +config BOARD_RT1050_ArchMix + bool + default y + +# RT1050 flash select! +choice + prompt "RT1050 Flash select" + default BOARD_USING_QSPIFLASH + config BOARD_USING_HYPERFLASH + bool "HYPERFLASH" + config BOARD_USING_QSPIFLASH + bool "QSPIFLASH" + +endchoice + +menu "RT1050 Bsp Config" + +menu "Select uart drivers" + config RT_USING_UART1 + bool "Using uart1" + select RT_USING_SERIAL + default y + config RT_USING_UART2 + bool "Using uart2" + select RT_USING_SERIAL + default n + config RT_USING_UART3 + bool "Using uart3" + select RT_USING_SERIAL + default n + config RT_USING_UART8 + bool "Using uart8" + select RT_USING_SERIAL + default n +endmenu + +menu "Select spi bus and dev drivers" + choice + prompt "SPI bus clock source" + default LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + + config LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + bool "PLL3PFD1" + config LPSPI_CLK_SOURCE_FROM_PLL3PFD0 + bool "PLL3PFD0" + config LPSPI_CLK_SOURCE_FROM_PLL2 + bool "PLL2" + config LPSPI_CLK_SOURCE_FROM_PLL2PFD2 + bool "PLL2PFD2" + endchoice + config LPSPI_CLK_SOURCE + int + default 0 if LPSPI_CLK_SOURCE_FROM_PLL3PFD1 + default 1 if LPSPI_CLK_SOURCE_FROM_PLL3PFD0 + default 2 if LPSPI_CLK_SOURCE_FROM_PLL2 + default 3 if LPSPI_CLK_SOURCE_FROM_PLL2PFD2 + + config LPSPI_CLK_SOURCE_DIVIDER + int "SPI bus clock source divider" + range 1 8 + default 8 + + config RT_USING_SPIBUS3 + bool "Using spi3 bus" + select RT_USING_SPI + default n + choice + prompt "spi3 bus sck io choice" + default LPSPI3_SCK_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SCK_GPIO_1 + bool "GPIO_AD_B1_15" + endchoice + choice + prompt "spi3 bus sdo io choice" + default LPSPI3_SDO_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SDO_GPIO_1 + bool "GPIO_AD_B1_14" + endchoice + choice + prompt "spi3 bus sdi io choice" + default LPSPI3_SDI_GPIO_1 + depends on RT_USING_SPIBUS3 + config LPSPI3_SDI_GPIO_1 + bool "GPIO_AD_B1_13" + endchoice + + config RT_USING_SPIBUS4 + bool "Using spi4 bus" + select RT_USING_SPI + default y + choice + prompt "spi4 bus sck io choice" + default LPSPI4_SCK_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SCK_GPIO_2 + bool "GPIO_B1_07" + endchoice + choice + prompt "spi4 bus sdo io choice" + default LPSPI4_SDO_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SDO_GPIO_2 + bool "GPIO_B1_06" + endchoice + choice + prompt "spi4 bus sdi io choice" + default LPSPI4_SDI_GPIO_1 + depends on RT_USING_SPIBUS4 + config LPSPI4_SDI_GPIO_2 + bool "GPIO_B1_05" + endchoice + + config RT_USING_SPI_FLASH + bool "Using spi flash with sfud" + default n + select RT_USING_SPI + select RT_USING_SFUD + select RT_USING_PIN + choice + prompt "SPI flash using spibus" + default SPI_FLASH_USING_SPIBUS4 + depends on RT_USING_SPI_FLASH + + config SPI_FLASH_USING_SPIBUS1 + bool "spi1" + select RT_USING_SPIBUS1 + config SPI_FLASH_USING_SPIBUS2 + bool "spi2" + select RT_USING_SPIBUS2 + config SPI_FLASH_USING_SPIBUS3 + bool "spi3" + select RT_USING_SPIBUS3 + config SPI_FLASH_USING_SPIBUS4 + bool "spi4" + select RT_USING_SPIBUS4 + endchoice + config SPI_FLASH_USING_SPIBUS_NAME + string + default "spi1" if SPI_FLASH_USING_SPIBUS1 + default "spi2" if SPI_FLASH_USING_SPIBUS2 + default "spi3" if SPI_FLASH_USING_SPIBUS3 + default "spi4" if SPI_FLASH_USING_SPIBUS4 + + config SPI_FLASH_NAME + string "SPI flash device name" + default "flash0" + depends on RT_USING_SPI_FLASH + + config SPI_FLASH_USING_CS_PIN + int "SPI flash cs pin index" + default 79 + range 1 127 + depends on RT_USING_SPI_FLASH +endmenu + +menu "Select iic bus drivers" + + config RT_USING_HW_I2C1 + bool "using hardware i2c1" + select RT_USING_I2C + default y + choice + prompt "i2c1 bus badurate choice" + default HW_I2C1_BADURATE_100kHZ + depends on RT_USING_HW_I2C1 + config HW_I2C1_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C1_BADURATE_400kHZ + bool "400kHZ" + endchoice + + config RT_USING_HW_I2C3 + bool "using hardware i2c3" + select RT_USING_I2C + default n + choice + prompt "i2c3 bus badurate choice" + default HW_I2C3_BADURATE_100kHZ + depends on RT_USING_HW_I2C3 + config HW_I2C3_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C3_BADURATE_400kHZ + bool "400kHZ" + endchoice + + config RT_USING_HW_I2C4 + bool "using hardware i2c4" + select RT_USING_I2C + default n + choice + prompt "i2c4 bus badurate choice" + default HW_I2C4_BADURATE_100kHZ + depends on RT_USING_HW_I2C4 + config HW_I2C4_BADURATE_100kHZ + bool "100kHZ" + config HW_I2C4_BADURATE_400kHZ + bool "400kHZ" + endchoice + +endmenu + +menu "Select lcd driver" + + if RT_USING_LCD + comment "Notice: Arch Mix Board para: 480*272 4 4 8 2 40 10 127 45" + endif + + config RT_USING_LCD + bool "Using lcd" + default n + + config LCD_WIDTH + int "Width pixel num" + default 480 + depends on RT_USING_LCD + config LCD_HEIGHT + int "Height pixel num" + default 272 + depends on RT_USING_LCD + config LCD_HFP + int "HFP" + default 4 + depends on RT_USING_LCD + config LCD_VFP + int "VFP" + default 4 + depends on RT_USING_LCD + config LCD_HBP + int "HBP" + default 8 + depends on RT_USING_LCD + config LCD_VBP + int "VBP" + default 2 + depends on RT_USING_LCD + config LCD_HSW + int "HSW" + default 40 + depends on RT_USING_LCD + config LCD_VSW + int "VSW" + default 10 + depends on RT_USING_LCD + config LCD_BL_PIN + int "Backlight pin index" + default 127 + depends on RT_USING_LCD + config LCD_RST_PIN + int "Reset pin index" + default 45 + depends on RT_USING_LCD +endmenu + +#menu "Select SDRAM driver" + config RT_USING_SDRAM + bool "Using sdram" + default y +#endmenu + +#menu "Select RTC driver" + config RT_USING_RTC_HP + bool "Using hp rtc" + select RT_USING_RTC + default n +#endmenu + +if RT_USING_USB_DEVICE + choice + prompt "select usb device controller" + default RT_USING_EHCI0_AS_DEVICE + + config RT_USING_EHCI0_AS_DEVICE + bool "set EHCI0 as device" + config RT_USING_EHCI1_AS_DEVICE + bool "set EHCI1 as device" + endchoice +endif + +endmenu diff --git a/bsp/imxrt/imxrt1050-ArchMix/README.md b/bsp/imxrt/imxrt1050-ArchMix/README.md new file mode 100644 index 0000000000..52ca795a94 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/README.md @@ -0,0 +1,83 @@ +# i.MX RT1050 Arch Mix + +## 1. 简介 + +i.MX RT 1050系列芯片，是由 NXP 半导体公司推出的跨界处理器芯片。它基于应用处理器的芯片架构，采用了微控制器的内核Cortex-M7，从而具有应用处理器的高性能及丰富的功能，又具备传统微控制器的易用、实时及低功耗的特性。 + +BSP默认支持的i.MX RT1052处理器具备以下简要的特性： + +| 介绍 | 描述 | +| ---- | ---- | +| 主CPU平台 | ARM Cortex-M7 | +| 最高频率 | 600MHz | +| 内部存储器 | 512KB SRAM | +| 外部存储器接口 | NAND、eMMC、QuadSPI NOR Flash 和 Parallel NOR Flash | + +## 2. 编译说明 + +i.MX RT1050板级包支持MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| ---------- | --------- | +| MDK5 | MDK525 | +| IAR | IAR 8.11.3.13984 | +| GCC | GCC 5.4.1 20160919 (release) | + +## 3.BSP使用 + +### 3.1 配置工程 + +i.MX RT1052 BSP 支持多种 Flash，包括 Hyper Flash 和 QSPI Flash。如果不是 QSPI Flash 版本，那么需要重新配置并生成工程： + +- 在 bsp 下打开 env 工具 +- 输入`menuconfig`命令，`RT1052 Flash select (***)-->`选择正确的 Flash 版本。 +- 输入`scons --target=mdk5 -s`或`scons --target=iar`来生成需要的工程 + +### 3.2 下载和仿真 + +连接外置仿真器 Jlink 后，就可以进行下载和仿真。使用 TTL 转串口工具连接开发板上 J3 的19/20 引脚，在终端工具里打开相应的串口。(19 接 TX，20 接 RX) + +### 3.3 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： + +``` + \ | / +- RT - Thread Operating System + / | \ 3.1.1 build Oct 9 2018 + 2006 - 2018 Copyright by rt-thread team +using armcc, version: 5060750 +build time: Oct 9 2018 14:21:49 +msh />[I/[SDIO]] SD card capacity 123904 KB. +[I/[SDIO]] probe mmcsd block device! +found part[0], begin: 67584, size: 120.958MB +File System initialized! +``` + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | ------ | +| UART | 支持 | UART 1~3/8 | +| GPIO | 支持 | | +| IIC | 支持 | IIC 1/3/4 | +| SPI | 支持 | SPI 3/4 | +| LCD | 支持 | | +| RTC | 支持 | | +| SDIO | 支持 | 暂时仅仅支持一个SDIO，还不支持中断方式 | +| SDRAM | 支持 | 32M SDRAM，后面 2M 作为 Non Cache 区域 | + +## 5. 联系人信息 + +维护人： + +- [tanek](https://github.com/TanekLiang) +- [liu2guang](https://github.com/liu2guang) + +## 6. 参考 + +- [MIMXRT1050-EVK: i.MX RT1050评估套件概述](https://www.nxp.com/cn/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK) +- [MIMXRT1050 EVK Board Hardware User’s Guide ](https://www.nxp.com/docs/en/user-guide/MIMXRT1050EVKHUG.pdf) +- [i.MX RT Series Crossover Processor Quick Start Guide](https://www.nxp.com/docs/en/user-guide/IMXRT1050EVKQSG.pdf) +- [i.MX RT Series Crossover Processor Fact Sheet](https://www.nxp.com/docs/en/fact-sheet/IMXRTSERIESFS.pdf) +- [Evaluation Kit Based on i.MX RT1050 Crossover Processors](https://www.nxp.com/docs/en/fact-sheet/IMXRT1050EVKFS.pdf) diff --git a/bsp/imxrt/imxrt1050-ArchMix/SConscript b/bsp/imxrt/imxrt1050-ArchMix/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imxrt/imxrt1050-ArchMix/SConstruct b/bsp/imxrt/imxrt1050-ArchMix/SConstruct new file mode 100644 index 0000000000..ea53aac131 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/SConstruct @@ -0,0 +1,72 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread-imxrt.' + rtconfig.TARGET_EXT + +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +objs = objs + SConscript('../Libraries/imxrt1050/SConscript') + +# make a building +DoBuilding(TARGET, objs) + +def Update_MDKFlashProgrammingAlgorithm(flash_dict): + import xml.etree.ElementTree as etree + from utils import xml_indent + + project_tree = etree.parse('project.uvoptx') + root = project_tree.getroot() + out = file('project.uvoptx', 'wb') + + for elem in project_tree.iterfind('.//Target/TargetOption/TargetDriverDllRegistry/SetRegEntry'): + Key = elem.find('Key') + if Key.text in flash_dict.keys(): + elem.find('Name').text = flash_dict[Key.text] + + xml_indent(root) + out.write(etree.tostring(root, encoding='utf-8')) + out.close() + +if GetOption('target') and GetDepend('BOARD_USING_QSPIFLASH'): + Update_MDKFlashProgrammingAlgorithm({ + "JL2CM3": '-U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000', + "CMSIS_AGDI": '-X"Any" -UAny -O974 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000', + }) diff --git a/bsp/imxrt/imxrt1050-ArchMix/applications/SConscript b/bsp/imxrt/imxrt1050-ArchMix/applications/SConscript new file mode 100644 index 0000000000..0a4d797abe --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/applications/SConscript @@ -0,0 +1,16 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/imxrt1050-ArchMix/applications/lcd_init.c b/bsp/imxrt/imxrt1050-ArchMix/applications/lcd_init.c new file mode 100644 index 0000000000..be209338b3 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/applications/lcd_init.c @@ -0,0 +1,42 @@ +/* + * File : lcd_init.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2018-06-12 Tanek first version + */ + +#include + +#if defined(PKG_USING_GUIENGINE) + +#include +int lcd_init(void) +{ + struct rt_device *device; + device = rt_device_find("lcd"); + if (device) + { + rtgui_graphic_set_device(device); + } + + return 0; +} +INIT_APP_EXPORT(lcd_init); +#endif diff --git a/bsp/imxrt/imxrt1050-ArchMix/applications/main.c b/bsp/imxrt/imxrt1050-ArchMix/applications/main.c new file mode 100644 index 0000000000..9f6060487a --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/applications/main.c @@ -0,0 +1,143 @@ +/* + * File : clock.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2017-10-10 Tanek first version + */ + +#include +#include +#include + +#ifdef RT_USING_DFS +#include +#endif + +#ifdef RT_USING_DEVICE +#include +#endif + +#include + +void dump_clock(void) +{ + rt_kprintf("OSC clock : %d\n", CLOCK_GetFreq(kCLOCK_OscClk)); + rt_kprintf("RTC clock : %d\n", CLOCK_GetFreq(kCLOCK_RtcClk)); + rt_kprintf("CPU clock: %d\n", CLOCK_GetFreq(kCLOCK_CpuClk)); + rt_kprintf("AHB clock : %d\n", CLOCK_GetFreq(kCLOCK_AhbClk)); + rt_kprintf("SEMC clock : %d\n", CLOCK_GetFreq(kCLOCK_SemcClk)); + rt_kprintf("IPG clock : %d\n", CLOCK_GetFreq(kCLOCK_IpgClk)); + rt_kprintf("ARMPLLCLK(PLL1) : %d\n", CLOCK_GetFreq(kCLOCK_ArmPllClk)); + rt_kprintf("SYSPLLCLK(PLL2/528_PLL) : %d\n", CLOCK_GetFreq(kCLOCK_SysPllClk)); + rt_kprintf("SYSPLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk)); + rt_kprintf("SYSPLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk)); + rt_kprintf("SYSPLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk)); + rt_kprintf("SYSPLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk)); + rt_kprintf("USB1PLLCLK(PLL3) : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk)); + rt_kprintf("USB1PLLPDF0CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk)); + rt_kprintf("USB1PLLPFD1CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk)); + rt_kprintf("USB1PLLPFD2CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk)); + rt_kprintf("USB1PLLPFD3CLK : %d\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk)); + rt_kprintf("Audio PLLCLK(PLL4) : %d\n", CLOCK_GetFreq(kCLOCK_AudioPllClk)); + rt_kprintf("Video PLLCLK(PLL5) : %d\n", CLOCK_GetFreq(kCLOCK_VideoPllClk)); + rt_kprintf("Enet PLLCLK ref_enetpll0 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk)); + rt_kprintf("Enet PLLCLK ref_enetpll1 : %d\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk)); + rt_kprintf("USB2PLLCLK(PLL7) : %d\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk)); +} + +void dump_cc_info(void) +{ +#if defined(__CC_ARM) + rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); +#elif defined(__ICCARM__) + rt_kprintf("using iccarm, version: %d\n", __VER__); +#elif defined(__GNUC__) + rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); +#endif +} + +void dump_link_info(void) +{ +#if defined(__CC_ARM) + +#elif defined(__ICCARM__) + +#elif defined(__GNUC__) + #define DUMP_SYMBOL(__SYM) \ + extern int __SYM; \ + rt_kprintf("%s: %p\n", #__SYM, &__SYM) + + DUMP_SYMBOL(__fsymtab_start); + DUMP_SYMBOL(__fsymtab_end); + DUMP_SYMBOL(__vsymtab_start); + DUMP_SYMBOL(__vsymtab_end); + DUMP_SYMBOL(__rt_init_start); + DUMP_SYMBOL(__rt_init_end); + + DUMP_SYMBOL(__exidx_start); + DUMP_SYMBOL(__exidx_end); + + DUMP_SYMBOL(__etext); + + DUMP_SYMBOL(__data_start__); + DUMP_SYMBOL(__data_end__); + + DUMP_SYMBOL(__noncachedata_start__); + DUMP_SYMBOL(__noncachedata_init_end__); + + DUMP_SYMBOL(__noncachedata_end__); + + DUMP_SYMBOL(__bss_start__); + DUMP_SYMBOL(__bss_end__); + + DUMP_SYMBOL(stack_start); + DUMP_SYMBOL(stack_end); + + DUMP_SYMBOL(heap_start); +#endif +} + +int main(void) +{ + rt_uint32_t result; + //dump_clock(); + dump_cc_info(); + dump_link_info(); + + rt_kprintf("build time: %s %s\n", __DATE__, __TIME__); + +#if defined(RT_USING_DFS) && defined(RT_USING_SDIO) + result = mmcsd_wait_cd_changed(RT_TICK_PER_SECOND); + if (result == MMCSD_HOST_PLUGED) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); + } + else + { + rt_kprintf("sdcard init fail or timeout: %d!\n", result); + } +#endif +} + +/*@}*/ diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript b/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript new file mode 100644 index 0000000000..a7090a02d3 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript @@ -0,0 +1,15 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +""") + +CPPPATH = [cwd] +CPPDEFINES = [] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/board.c b/bsp/imxrt/imxrt1050-ArchMix/drivers/board.c new file mode 100644 index 0000000000..a604df6d4c --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/board.c @@ -0,0 +1,204 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + */ +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" + +#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) +static struct rt_memheap system_heap; +#endif + +/* ARM PLL configuration for RUN mode */ +const clock_arm_pll_config_t armPllConfig = { .loopDivider = 100U }; + +/* SYS PLL configuration for RUN mode */ +const clock_sys_pll_config_t sysPllConfig = { .loopDivider = 1U }; + +/* USB1 PLL configuration for RUN mode */ +const clock_usb_pll_config_t usb1PllConfig = { .loopDivider = 0U }; + +static void BOARD_BootClockGate(void) +{ +// /* Disable all unused peripheral clock */ +// CCM->CCGR0 = 0x00C0000FU; +// CCM->CCGR1 = 0x30000000U; +// CCM->CCGR2 = 0x003F0030U; +// CCM->CCGR3 = 0xF0000330U; +// CCM->CCGR4 = 0x0000FF3CU; +// CCM->CCGR5 = 0xF000330FU; +// CCM->CCGR6 = 0x00FC0300U; +} + +static void BOARD_BootClockRUN(void) +{ + /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */ + CLOCK_SetXtalFreq(24000000U); + CLOCK_SetRtcXtalFreq(32768U); + + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + + /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12); + + CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ +#ifndef SKIP_SYSCLK_INIT + CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */ +#endif +#ifndef SKIP_USB_PLL_INIT + CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */ +#endif + CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */ + + CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ + + /* Disable unused clock */ + BOARD_BootClockGate(); + + /* Power down all unused PLL */ + CLOCK_DeinitAudioPll(); + CLOCK_DeinitVideoPll(); + CLOCK_DeinitEnetPll(); + CLOCK_DeinitUsb2Pll(); + + /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* Update core clock */ + SystemCoreClockUpdate(); +} + + +/* MPU configuration. */ +static void BOARD_ConfigMPU(void) +{ + /* Disable I cache and D cache */ + SCB_DisableICache(); + SCB_DisableDCache(); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Region 0 setting */ + MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 1 setting */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 2 setting */ + // spi flash: normal type, cacheable, no bufferable, no shareable + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 5 setting */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + +#if defined(SDRAM_MPU_INIT) + /* Region 7 setting */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); + + /* Region 8 setting */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); +#endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void SystemInitHook(void) +{ + BOARD_ConfigMPU(); + +#if defined(RT_USING_SDRAM) + extern int imxrt_sdram_init(void); + imxrt_sdram_init(); +#endif +} + +/** + * This function will initial rt1050 board. + */ +void rt_hw_board_init() +{ + BOARD_BootClockRUN(); + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_HEAP + +#if defined(RT_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP) + rt_kprintf("sdram heap, begin: 0x%p, end: 0x%p\n", SDRAM_BEGIN, SDRAM_END); + rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END); + + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE); +#else + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#endif +} + +/*@}*/ diff --git a/bsp/imxrt/imxrt1050-ArchMix/drivers/board.h b/bsp/imxrt/imxrt1050-ArchMix/drivers/board.h new file mode 100644 index 0000000000..80a61f1a3a --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/board.h @@ -0,0 +1,52 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include + +#ifdef __CC_ARM +extern int Image$$RTT_HEAP$$ZI$$Base; +extern int Image$$RTT_HEAP$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) +#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) + +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) + +#else +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) +#endif + +#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) + +#define SDRAM_MPU_INIT +#define SDRAM_BEGIN (0x80000000u) +#define SDRAM_END (0x81E00000u) + +void rt_hw_board_init(void); + +#endif + +//*** <<< end of configuration section >>> *** diff --git a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ini b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ini new file mode 100644 index 0000000000..1e21d31013 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ini @@ -0,0 +1,45 @@ +/* + * Copyright 2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +FUNC void Setup (void) { + + SP = _RDWORD(0x60002000); // Setup Stack Pointer + PC = _RDWORD(0x60002004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x60002000); // Setup Vector Table Offset Register +} + +FUNC void OnResetExec (void) { // executes upon software RESET + Setup(); // Setup for Running +} + +LOAD %L INCREMENTAL // Download + +Setup(); // Setup for Running + +// g, main diff --git a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ld b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ld new file mode 100644 index 0000000000..b8c229ae3c --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.ld @@ -0,0 +1,276 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_boot_data (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_image_vertor_table (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x1F7FDC00 + + m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000 + m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + + m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + .boot_data : + { + KEEP(*(.boot_hdr.conf)) + } > m_boot_data + + .image_vertor_table : + { + KEEP(*(.boot_hdr.ivt)) + KEEP(*(.boot_hdr.boot_data)) + KEEP(*(.boot_hdr.dcd_data)) + } > m_image_vertor_table + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + PROVIDE(__ctors_start__ = .); + /* __CTOR_LIST__ = .; */ + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + /* __CTOR_END__ = .; */ + PROVIDE(__ctors_end__ = .); + } > m_text + + .dtors : + { + PROVIDE(__dtors_start__ = .); + /* __DTOR_LIST__ = .; */ + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* __DTOR_END__ = .; */ + PROVIDE(__dtors_end__ = .); + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_dtcm + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_nocache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_nocache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_dtcm + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + } > m_dtcm + + .RTT_HEAP : + { + heap_start = .; + . = ALIGN(8); + } > m_dtcm + + PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm)); + + .ARM.attributes 0 : { *(.ARM.attributes) } + +} + diff --git a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf new file mode 100644 index 0000000000..5e0834cd48 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf @@ -0,0 +1,125 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1052CVL5A +** MIMXRT1052DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1050RM Rev.C, 08/2017 +** Version: rev. 0.1, 2017-01-10 +** Build: b170927 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_text_start 0x60002000 +#define m_text_size 0x1F7FE000 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x1000 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#include "rtconfig.h" + +#if (defined(BOARD_USING_HYPERFLASH)) +LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region +{ + RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address + { + * (.boot_hdr.conf, +FIRST) + } +} + +LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region +{ + RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address + { + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +} +#endif + +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +; load region size_region +LR_IROM1 m_text_start m_text_size +{ + ER_IROM1 m_text_start m_text_size ; load address = execution address + { + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} + + ; ncache RW data + RW_m_ncache m_ncache_start m_ncache_size + { + * (NonCacheable.init) + * (NonCacheable) + } +} diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.ewd b/bsp/imxrt/imxrt1050-ArchMix/project.ewd new file mode 100644 index 0000000000..60c31a48ee --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/project.ewd @@ -0,0 +1,2908 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.ewp b/bsp/imxrt/imxrt1050-ArchMix/project.ewp new file mode 100644 index 0000000000..9ad86219cf --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/project.ewp @@ -0,0 +1,2478 @@ + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Applications + + $PROJ_DIR$\applications\device_test.c + + + $PROJ_DIR$\applications\main.c + + + $PROJ_DIR$\applications\mem_dump.c + + + $PROJ_DIR$\applications\mem_test.c + + + + Drivers + + $PROJ_DIR$\drivers\board.c + + + $PROJ_DIR$\drivers\drv_uart.c + + + $PROJ_DIR$\drivers\drv_cache.c + + + $PROJ_DIR$\drivers\drv_sdram.c + + + $PROJ_DIR$\drivers\drv_pin.c + + + $PROJ_DIR$\drivers\drv_rtc.c + + + $PROJ_DIR$\drivers\drv_spi_bus.c + + + $PROJ_DIR$\drivers\drv_i2c.c + + + $PROJ_DIR$\drivers\drv_lcd.c + + + $PROJ_DIR$\drivers\drv_sdio.c + + + $PROJ_DIR$\drivers\drv_eth.c + + + $PROJ_DIR$\drivers\fsl_phy.c + + + + Libraries + + $PROJ_DIR$\Libraries\drivers\fsl_adc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_adc_etc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_aipstz.c + + + $PROJ_DIR$\Libraries\drivers\fsl_aoi.c + + + $PROJ_DIR$\Libraries\drivers\fsl_bee.c + + + $PROJ_DIR$\Libraries\drivers\fsl_cache.c + + + $PROJ_DIR$\Libraries\drivers\fsl_clock.c + + + $PROJ_DIR$\Libraries\drivers\fsl_cmp.c + + + $PROJ_DIR$\Libraries\drivers\fsl_common.c + + + $PROJ_DIR$\Libraries\drivers\fsl_csi.c + + + $PROJ_DIR$\Libraries\drivers\fsl_dcdc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_dcp.c + + + $PROJ_DIR$\Libraries\drivers\fsl_dmamux.c + + + $PROJ_DIR$\Libraries\drivers\fsl_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_elcdif.c + + + $PROJ_DIR$\Libraries\drivers\fsl_enc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_enet.c + + + $PROJ_DIR$\Libraries\drivers\fsl_ewm.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexcan.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_i2c_master.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_i2s.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_i2s_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_spi.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_spi_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_uart.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexio_uart_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexram.c + + + $PROJ_DIR$\Libraries\drivers\fsl_flexspi.c + + + $PROJ_DIR$\Libraries\drivers\fsl_gpc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_gpio.c + + + $PROJ_DIR$\Libraries\drivers\fsl_gpt.c + + + $PROJ_DIR$\Libraries\drivers\fsl_kpp.c + + + $PROJ_DIR$\Libraries\drivers\fsl_lpi2c.c + + + $PROJ_DIR$\Libraries\drivers\fsl_lpi2c_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_lpspi.c + + + $PROJ_DIR$\Libraries\drivers\fsl_lpspi_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_lpuart.c + + + $PROJ_DIR$\Libraries\drivers\fsl_lpuart_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_pit.c + + + $PROJ_DIR$\Libraries\drivers\fsl_pmu.c + + + $PROJ_DIR$\Libraries\drivers\fsl_pwm.c + + + $PROJ_DIR$\Libraries\drivers\fsl_pxp.c + + + $PROJ_DIR$\Libraries\drivers\fsl_qtmr.c + + + $PROJ_DIR$\Libraries\drivers\fsl_rtwdog.c + + + $PROJ_DIR$\Libraries\drivers\fsl_sai.c + + + $PROJ_DIR$\Libraries\drivers\fsl_sai_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_semc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_snvs_hp.c + + + $PROJ_DIR$\Libraries\drivers\fsl_snvs_lp.c + + + $PROJ_DIR$\Libraries\drivers\fsl_spdif.c + + + $PROJ_DIR$\Libraries\drivers\fsl_spdif_edma.c + + + $PROJ_DIR$\Libraries\drivers\fsl_src.c + + + $PROJ_DIR$\Libraries\drivers\fsl_trng.c + + + $PROJ_DIR$\Libraries\drivers\fsl_tsc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_usdhc.c + + + $PROJ_DIR$\Libraries\drivers\fsl_wdog.c + + + $PROJ_DIR$\Libraries\drivers\fsl_xbara.c + + + $PROJ_DIR$\Libraries\drivers\fsl_xbarb.c + + + $PROJ_DIR$\Libraries\system_MIMXRT1052.c + + + $PROJ_DIR$\Libraries\iar\startup_MIMXRT1052.s + + + + xip + + $PROJ_DIR$\xip\fsl_flexspi_nor_boot.c + + + $PROJ_DIR$\xip\fsl_flexspi_nor_flash.c + + + + Kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\components.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\memheap.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\signal.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + CORTEX-M7 + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m7\cpuport.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m7\context_iar.S + + + $PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c + + + + Filesystem + + $PROJ_DIR$\..\..\components\dfs\src\dfs.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_file.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\devfs\devfs.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c + + + + DeviceDrivers + + $PROJ_DIR$\..\..\components\drivers\i2c\i2c_core.c + + + $PROJ_DIR$\..\..\components\drivers\i2c\i2c_dev.c + + + $PROJ_DIR$\..\..\components\drivers\i2c\i2c-bit-ops.c + + + $PROJ_DIR$\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\components\drivers\rtc\rtc.c + + + $PROJ_DIR$\..\..\components\drivers\sdio\block_dev.c + + + $PROJ_DIR$\..\..\components\drivers\sdio\mmcsd_core.c + + + $PROJ_DIR$\..\..\components\drivers\sdio\sd.c + + + $PROJ_DIR$\..\..\components\drivers\sdio\sdio.c + + + $PROJ_DIR$\..\..\components\drivers\sdio\mmc.c + + + $PROJ_DIR$\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\components\drivers\spi\spi_core.c + + + $PROJ_DIR$\..\..\components\drivers\spi\spi_dev.c + + + $PROJ_DIR$\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\workqueue.c + + + + finsh + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\components\finsh\symbol.c + + + $PROJ_DIR$\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\components\finsh\msh_cmd.c + + + $PROJ_DIR$\..\..\components\finsh\msh_file.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_token.c + + + + dlib + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\libc.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\rmtx.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\stdio.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\time.c + + + + lwIP + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\arch\sys_arch.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\api_lib.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\api_msg.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\err.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netbuf.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netdb.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\netifapi.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\sockets.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\api\tcpip.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\def.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\dns.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\inet_chksum.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\init.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ip.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\memp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\netif.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\pbuf.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\raw.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\stats.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\sys.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp_in.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\tcp_out.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\timeouts.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\udp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\netif\ethernet.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\netif\ethernetif.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\netif\lowpan6.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\autoip.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\dhcp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\etharp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c + + + $PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.eww b/bsp/imxrt/imxrt1050-ArchMix/project.eww new file mode 100644 index 0000000000..faa93f37cd --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx b/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx new file mode 100644 index 0000000000..0a3c8c8bc0 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx @@ -0,0 +1,1858 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + RT-Thread IMXRT1052 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\flexspi_nor.ini + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST1 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O974 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FCF000 -FN1 -FF0iMXRT1052_W25Q256JV_By_Fire -FS060000000 -FL02000000 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\lcd_init.c + lcd_init.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\drivers\drv_cache.c + drv_cache.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\drivers\drv_sdram.c + drv_sdram.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\drivers\drv_pin.c + drv_pin.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\drivers\drv_rtc.c + drv_rtc.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\drivers\drv_spi_bus.c + drv_spi_bus.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\drivers\drv_i2c.c + drv_i2c.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\drivers\drv_lcd.c + drv_lcd.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\drivers\drv_sdio.c + drv_sdio.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\src\memheap.c + memheap.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\src\signal.c + signal.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + CORTEX-M7 + 0 + 0 + 0 + 0 + + 4 + 27 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m7\cpuport.c + cpuport.c + 0 + 0 + + + 4 + 28 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m7\context_rvds.S + context_rvds.S + 0 + 0 + + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + + + Filesystem + 0 + 0 + 0 + 0 + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs.c + dfs.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs_file.c + dfs_file.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs_fs.c + dfs_fs.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\src\dfs_posix.c + dfs_posix.c + 0 + 0 + + + 5 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\filesystems\devfs\devfs.c + devfs.c + 0 + 0 + + + 5 + 37 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + dfs_elm.c + 0 + 0 + + + 5 + 38 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\filesystems\elmfat\ff.c + ff.c + 0 + 0 + + + 5 + 39 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c + ccsbcs.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\cputime\cputime.c + cputime.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\cputime\cputime_cortexm.c + cputime_cortexm.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c_core.c + i2c_core.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c_dev.c + i2c_dev.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + i2c-bit-ops.c + 0 + 0 + + + 6 + 45 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 6 + 46 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\rtc\rtc.c + rtc.c + 0 + 0 + + + 6 + 47 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\sdio\block_dev.c + block_dev.c + 0 + 0 + + + 6 + 48 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\sdio\mmcsd_core.c + mmcsd_core.c + 0 + 0 + + + 6 + 49 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\sdio\sd.c + sd.c + 0 + 0 + + + 6 + 50 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\sdio\sdio.c + sdio.c + 0 + 0 + + + 6 + 51 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\sdio\mmc.c + mmc.c + 0 + 0 + + + 6 + 52 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + 6 + 53 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_core.c + spi_core.c + 0 + 0 + + + 6 + 54 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_dev.c + spi_dev.c + 0 + 0 + + + 6 + 55 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\completion.c + completion.c + 0 + 0 + + + 6 + 56 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\dataqueue.c + dataqueue.c + 0 + 0 + + + 6 + 57 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\pipe.c + pipe.c + 0 + 0 + + + 6 + 58 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 6 + 59 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 6 + 60 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\waitqueue.c + waitqueue.c + 0 + 0 + + + 6 + 61 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\src\workqueue.c + workqueue.c + 0 + 0 + + + + + finsh + 0 + 0 + 0 + 0 + + 7 + 62 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\symbol.c + symbol.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_cmd.c + msh_cmd.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_file.c + msh_file.c + 0 + 0 + + + + + libc + 0 + 0 + 0 + 0 + + 8 + 68 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\libc.c + libc.c + 0 + 0 + + + 8 + 69 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\mem_std.c + mem_std.c + 0 + 0 + + + 8 + 70 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\stdio.c + stdio.c + 0 + 0 + + + 8 + 71 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\stubs.c + stubs.c + 0 + 0 + + + 8 + 72 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\time.c + time.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 9 + 73 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc.c + fsl_adc.c + 0 + 0 + + + 9 + 74 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc_etc.c + fsl_adc_etc.c + 0 + 0 + + + 9 + 75 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aipstz.c + fsl_aipstz.c + 0 + 0 + + + 9 + 76 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aoi.c + fsl_aoi.c + 0 + 0 + + + 9 + 77 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_bee.c + fsl_bee.c + 0 + 0 + + + 9 + 78 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cache.c + fsl_cache.c + 0 + 0 + + + 9 + 79 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_clock.c + fsl_clock.c + 0 + 0 + + + 9 + 80 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cmp.c + fsl_cmp.c + 0 + 0 + + + 9 + 81 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_common.c + fsl_common.c + 0 + 0 + + + 9 + 82 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_csi.c + fsl_csi.c + 0 + 0 + + + 9 + 83 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcdc.c + fsl_dcdc.c + 0 + 0 + + + 9 + 84 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcp.c + fsl_dcp.c + 0 + 0 + + + 9 + 85 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dmamux.c + fsl_dmamux.c + 0 + 0 + + + 9 + 86 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_edma.c + fsl_edma.c + 0 + 0 + + + 9 + 87 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_elcdif.c + fsl_elcdif.c + 0 + 0 + + + 9 + 88 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enc.c + fsl_enc.c + 0 + 0 + + + 9 + 89 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enet.c + fsl_enet.c + 0 + 0 + + + 9 + 90 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_ewm.c + fsl_ewm.c + 0 + 0 + + + 9 + 91 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexcan.c + fsl_flexcan.c + 0 + 0 + + + 9 + 92 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio.c + fsl_flexio.c + 0 + 0 + + + 9 + 93 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2c_master.c + fsl_flexio_i2c_master.c + 0 + 0 + + + 9 + 94 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s.c + fsl_flexio_i2s.c + 0 + 0 + + + 9 + 95 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s_edma.c + fsl_flexio_i2s_edma.c + 0 + 0 + + + 9 + 96 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi.c + fsl_flexio_spi.c + 0 + 0 + + + 9 + 97 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi_edma.c + fsl_flexio_spi_edma.c + 0 + 0 + + + 9 + 98 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart.c + fsl_flexio_uart.c + 0 + 0 + + + 9 + 99 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart_edma.c + fsl_flexio_uart_edma.c + 0 + 0 + + + 9 + 100 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexram.c + fsl_flexram.c + 0 + 0 + + + 9 + 101 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexspi.c + fsl_flexspi.c + 0 + 0 + + + 9 + 102 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpc.c + fsl_gpc.c + 0 + 0 + + + 9 + 103 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpio.c + fsl_gpio.c + 0 + 0 + + + 9 + 104 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpt.c + fsl_gpt.c + 0 + 0 + + + 9 + 105 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_kpp.c + fsl_kpp.c + 0 + 0 + + + 9 + 106 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c.c + fsl_lpi2c.c + 0 + 0 + + + 9 + 107 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c_edma.c + fsl_lpi2c_edma.c + 0 + 0 + + + 9 + 108 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi.c + fsl_lpspi.c + 0 + 0 + + + 9 + 109 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi_edma.c + fsl_lpspi_edma.c + 0 + 0 + + + 9 + 110 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart.c + fsl_lpuart.c + 0 + 0 + + + 9 + 111 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart_edma.c + fsl_lpuart_edma.c + 0 + 0 + + + 9 + 112 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pit.c + fsl_pit.c + 0 + 0 + + + 9 + 113 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pmu.c + fsl_pmu.c + 0 + 0 + + + 9 + 114 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pwm.c + fsl_pwm.c + 0 + 0 + + + 9 + 115 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pxp.c + fsl_pxp.c + 0 + 0 + + + 9 + 116 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_qtmr.c + fsl_qtmr.c + 0 + 0 + + + 9 + 117 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_rtwdog.c + fsl_rtwdog.c + 0 + 0 + + + 9 + 118 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai.c + fsl_sai.c + 0 + 0 + + + 9 + 119 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai_edma.c + fsl_sai_edma.c + 0 + 0 + + + 9 + 120 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_semc.c + fsl_semc.c + 0 + 0 + + + 9 + 121 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_hp.c + fsl_snvs_hp.c + 0 + 0 + + + 9 + 122 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_lp.c + fsl_snvs_lp.c + 0 + 0 + + + 9 + 123 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif.c + fsl_spdif.c + 0 + 0 + + + 9 + 124 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c + fsl_spdif_edma.c + 0 + 0 + + + 9 + 125 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c + fsl_src.c + 0 + 0 + + + 9 + 126 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c + fsl_trng.c + 0 + 0 + + + 9 + 127 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c + fsl_tsc.c + 0 + 0 + + + 9 + 128 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c + fsl_usdhc.c + 0 + 0 + + + 9 + 129 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c + fsl_wdog.c + 0 + 0 + + + 9 + 130 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c + fsl_xbara.c + 0 + 0 + + + 9 + 131 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c + fsl_xbarb.c + 0 + 0 + + + 9 + 132 + 1 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c + system_MIMXRT1052.c + 0 + 0 + + + 9 + 133 + 2 + 0 + 0 + 0 + ..\Libraries\imxrt1050\devices\MIMXRT1052\arm\startup_MIMXRT1052.s + startup_MIMXRT1052.s + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx b/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx new file mode 100644 index 0000000000..5efaa5332e --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx @@ -0,0 +1,1180 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RT-Thread IMXRT1052 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + MIMXRT1052:M7 + NXP + NXP.iMXRT_DFP.1.0.2 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) + 0 + $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h + + + + + + + + + + $$Device:MIMXRT1052$SVD\MIMXRT1052.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-imxrt + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread-mdk.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x20000 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + SKIP_SYSCLK_INIT, EVK_MCIMXRM, CPU_MIMXRT1052DVL6B, RT_USING_ARM_LIBC, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 + + applications;.;drivers;..\Libraries\imxrt1050\drivers;..\..\..\include;..\..\..\libcpu\arm\cortex-m7;..\..\..\libcpu\arm\common;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\Libraries\imxrt1050\CMSIS\Include;..\Libraries\imxrt1050\devices\MIMXRT1052;..\Libraries\imxrt1050\devices\MIMXRT1052\drivers;..\Libraries\imxrt1050\devices\MIMXRT1052\utilities + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\flexspi_nor.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) + + + + + + + + Applications + + + lcd_init.c + 1 + applications\lcd_init.c + + + main.c + 1 + applications\main.c + + + + + Drivers + + + board.c + 1 + drivers\board.c + + + drv_uart.c + 1 + ..\Libraries\imxrt1050\drivers\drv_uart.c + + + drv_cache.c + 1 + ..\Libraries\imxrt1050\drivers\drv_cache.c + + + drv_sdram.c + 1 + ..\Libraries\imxrt1050\drivers\drv_sdram.c + + + drv_pin.c + 1 + ..\Libraries\imxrt1050\drivers\drv_pin.c + + + drv_rtc.c + 1 + ..\Libraries\imxrt1050\drivers\drv_rtc.c + + + drv_spi_bus.c + 1 + ..\Libraries\imxrt1050\drivers\drv_spi_bus.c + + + drv_i2c.c + 1 + ..\Libraries\imxrt1050\drivers\drv_i2c.c + + + drv_lcd.c + 1 + ..\Libraries\imxrt1050\drivers\drv_lcd.c + + + drv_sdio.c + 1 + ..\Libraries\imxrt1050\drivers\drv_sdio.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + signal.c + 1 + ..\..\..\src\signal.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + CORTEX-M7 + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m7\cpuport.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m7\context_rvds.S + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + Filesystem + + + dfs.c + 1 + ..\..\..\components\dfs\src\dfs.c + + + dfs_file.c + 1 + ..\..\..\components\dfs\src\dfs_file.c + + + dfs_fs.c + 1 + ..\..\..\components\dfs\src\dfs_fs.c + + + dfs_posix.c + 1 + ..\..\..\components\dfs\src\dfs_posix.c + + + devfs.c + 1 + ..\..\..\components\dfs\filesystems\devfs\devfs.c + + + dfs_elm.c + 1 + ..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + ff.c + 1 + ..\..\..\components\dfs\filesystems\elmfat\ff.c + + + ccsbcs.c + 1 + ..\..\..\components\dfs\filesystems\elmfat\option\ccsbcs.c + + + + + DeviceDrivers + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + cputime.c + 1 + ..\..\..\components\drivers\cputime\cputime.c + + + cputime_cortexm.c + 1 + ..\..\..\components\drivers\cputime\cputime_cortexm.c + + + i2c_core.c + 1 + ..\..\..\components\drivers\i2c\i2c_core.c + + + i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\i2c_dev.c + + + i2c-bit-ops.c + 1 + ..\..\..\components\drivers\i2c\i2c-bit-ops.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + rtc.c + 1 + ..\..\..\components\drivers\rtc\rtc.c + + + block_dev.c + 1 + ..\..\..\components\drivers\sdio\block_dev.c + + + mmcsd_core.c + 1 + ..\..\..\components\drivers\sdio\mmcsd_core.c + + + sd.c + 1 + ..\..\..\components\drivers\sdio\sd.c + + + sdio.c + 1 + ..\..\..\components\drivers\sdio\sdio.c + + + mmc.c + 1 + ..\..\..\components\drivers\sdio\mmc.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\src\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\src\workqueue.c + + + + + finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + symbol.c + 1 + ..\..\..\components\finsh\symbol.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + + + + + libc + + + libc.c + 1 + ..\..\..\components\libc\compilers\armlibc\libc.c + + + mem_std.c + 1 + ..\..\..\components\libc\compilers\armlibc\mem_std.c + + + stdio.c + 1 + ..\..\..\components\libc\compilers\armlibc\stdio.c + + + stubs.c + 1 + ..\..\..\components\libc\compilers\armlibc\stubs.c + + + time.c + 1 + ..\..\..\components\libc\compilers\armlibc\time.c + + + + + Libraries + + + fsl_adc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc.c + + + fsl_adc_etc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_adc_etc.c + + + fsl_aipstz.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aipstz.c + + + fsl_aoi.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_aoi.c + + + fsl_bee.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_bee.c + + + fsl_cache.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cache.c + + + fsl_clock.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_clock.c + + + fsl_cmp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_cmp.c + + + fsl_common.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_common.c + + + fsl_csi.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_csi.c + + + fsl_dcdc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcdc.c + + + fsl_dcp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dcp.c + + + fsl_dmamux.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_dmamux.c + + + fsl_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_edma.c + + + fsl_elcdif.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_elcdif.c + + + fsl_enc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enc.c + + + fsl_enet.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_enet.c + + + fsl_ewm.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_ewm.c + + + fsl_flexcan.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexcan.c + + + fsl_flexio.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio.c + + + fsl_flexio_i2c_master.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2c_master.c + + + fsl_flexio_i2s.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s.c + + + fsl_flexio_i2s_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_i2s_edma.c + + + fsl_flexio_spi.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi.c + + + fsl_flexio_spi_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_spi_edma.c + + + fsl_flexio_uart.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart.c + + + fsl_flexio_uart_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexio_uart_edma.c + + + fsl_flexram.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexram.c + + + fsl_flexspi.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_flexspi.c + + + fsl_gpc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpc.c + + + fsl_gpio.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpio.c + + + fsl_gpt.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_gpt.c + + + fsl_kpp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_kpp.c + + + fsl_lpi2c.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c.c + + + fsl_lpi2c_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpi2c_edma.c + + + fsl_lpspi.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi.c + + + fsl_lpspi_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpspi_edma.c + + + fsl_lpuart.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart.c + + + fsl_lpuart_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_lpuart_edma.c + + + fsl_pit.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pit.c + + + fsl_pmu.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pmu.c + + + fsl_pwm.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pwm.c + + + fsl_pxp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_pxp.c + + + fsl_qtmr.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_qtmr.c + + + fsl_rtwdog.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_rtwdog.c + + + fsl_sai.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai.c + + + fsl_sai_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_sai_edma.c + + + fsl_semc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_semc.c + + + fsl_snvs_hp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_hp.c + + + fsl_snvs_lp.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_snvs_lp.c + + + fsl_spdif.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif.c + + + fsl_spdif_edma.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_spdif_edma.c + + + fsl_src.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_src.c + + + fsl_trng.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_trng.c + + + fsl_tsc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_tsc.c + + + fsl_usdhc.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_usdhc.c + + + fsl_wdog.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_wdog.c + + + fsl_xbara.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbara.c + + + fsl_xbarb.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\drivers\fsl_xbarb.c + + + system_MIMXRT1052.c + 1 + ..\Libraries\imxrt1050\devices\MIMXRT1052\system_MIMXRT1052.c + + + startup_MIMXRT1052.s + 2 + ..\Libraries\imxrt1050\devices\MIMXRT1052\arm\startup_MIMXRT1052.s + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h new file mode 100644 index 0000000000..525013e73e --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h @@ -0,0 +1,232 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_CPUTIME +#define RT_USING_CPUTIME_CORTEXM +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +#define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_SPI + +/* Using WiFi */ + + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* ARM CMSIS */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* sample package */ + +/* samples: kernel and components samples */ + + +/* example package: hello */ + +#define SOC_IMXRT1052 +#define BOARD_RT1050_ArchMix +#define BOARD_USING_QSPIFLASH + +/* RT1050 Bsp Config */ + +/* Select uart drivers */ + +#define RT_USING_UART1 + +/* Select spi bus and dev drivers */ + +#define LPSPI_CLK_SOURCE_FROM_PLL3PFD1 +#define LPSPI_CLK_SOURCE 0 +#define LPSPI_CLK_SOURCE_DIVIDER 8 +#define RT_USING_SPIBUS4 +#define LPSPI4_SCK_GPIO_2 +#define LPSPI4_SDO_GPIO_2 +#define LPSPI4_SDI_GPIO_2 + +/* Select iic bus drivers */ + +#define RT_USING_HW_I2C1 +#define HW_I2C1_BADURATE_100kHZ + +/* Select lcd driver */ + +/* Notice: Arch Mix Board para: 480*272 4 4 8 2 40 10 127 45 */ + +#define RT_USING_LCD +#define LCD_WIDTH 480 +#define LCD_HEIGHT 272 +#define LCD_HFP 4 +#define LCD_VFP 4 +#define LCD_HBP 8 +#define LCD_VBP 2 +#define LCD_HSW 40 +#define LCD_VSW 10 +#define LCD_BL_PIN 127 +#define LCD_RST_PIN 45 +#define RT_USING_SDRAM +#define RT_USING_RTC_HP + +#endif diff --git a/bsp/imxrt/imxrt1050-ArchMix/rtconfig.py b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.py new file mode 100644 index 0000000000..1b4257884f --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.py @@ -0,0 +1,144 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/usr/local/Cellar/arm-none-eabi-gcc/7-2017-q4-major/gcc/bin/' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +#BUILD = 'debug' +BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -std=c99 -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread-imxrt-gcc.map,-cref,-u,Reset_Handler -T flexspi_nor.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread-imxrt-mdk.map --scatter ./Libraries/arm/MIMXRT1052xxxxx_flexspi_nor.scf' + + CFLAGS += ' --diag_suppress=66,1296,186' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M7' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + CXXFLAGS = CFLAGS + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M7' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config flexspi_nor.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/imxrt/imxrt1050-ArchMix/template.ewp b/bsp/imxrt/imxrt1050-ArchMix/template.ewp new file mode 100644 index 0000000000..cf4216d8b3 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/template.ewp @@ -0,0 +1,1823 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 21 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 14 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/template.uvoptx b/bsp/imxrt/imxrt1050-ArchMix/template.uvoptx new file mode 100644 index 0000000000..38055496d3 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + RT-Thread IMXRT1052 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 2 + + + + + + + + + + .\flexspi_nor.ini + BIN\CMSIS_AGDI.dll + + + + 0 + JL2CM3 + -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM) + + + 0 + CMSIS_AGDI + -X"" -O974 -S0 -C0 -P00 -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC.FLM -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FCF000 -FN1 -FF0MIMXRT105x_HYPER_256KB_SEC -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\MIMXRT105x_HYPER_256KB_SEC.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/template.uvprojx b/bsp/imxrt/imxrt1050-ArchMix/template.uvprojx new file mode 100644 index 0000000000..f6b254976b --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/template.uvprojx @@ -0,0 +1,399 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + RT-Thread IMXRT1052 + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::ARMCC + + + MIMXRT1052:M7 + NXP + NXP.iMXRT_DFP.1.0.2 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x00060000) IRAM2(0x00000000,0x00020000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0RT1050 -FS060000000 -FL04000000 -FP0($$Device:MIMXRT1052$Flash\RT1050.FLM)) + 0 + $$Device:MIMXRT1052$Device\Include\MIMXRT1052.h + + + + + + + + + + $$Device:MIMXRT1052$SVD\MIMXRT1052.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-imxrt + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread-mdk.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x0 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x20000 + + + + + + 1 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\flexspi_nor.scf + + + + + + + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/SConscript b/bsp/imxrt/imxrt1050-ArchMix/xip/SConscript new file mode 100644 index 0000000000..1b69f9e2e5 --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/SConscript @@ -0,0 +1,23 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +if GetDepend('BOARD_USING_HYPERFLASH'): + cwd = GetCurrentDir() + src = Glob('*.c') + CPPPATH = [cwd] + + if rtconfig.CROSS_TOOL == 'keil': + LINKFLAGS = '--keep=*(.boot_hdr.ivt)' + LINKFLAGS += '--keep=*(.boot_hdr.boot_data)' + LINKFLAGS += '--keep=*(.boot_hdr.dcd_data)' + LINKFLAGS += '--keep=*(.boot_hdr.conf)' + else: + LINKFLAGS = '' + + group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) + Return('group') + +if GetDepend('BOARD_USING_QSPIFLASH'): + group = [] + Return('group') diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.c b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 0000000000..5addfdbfaf --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,139 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexspi_nor_boot.h" + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif + +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + 0x60002000, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif + +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + (FLASH_END-FLASH_BASE), /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; + +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.dcd_data" +#endif +const uint8_t dcd_sdram[1072] = { +/*0000*/ 0xD2, 0x04, 0x30, 0x41, 0xCC, 0x03, 0xAC, 0x04, 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, +/*0010*/ 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, +/*0020*/ 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, +/*0030*/ 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, +/*0040*/ 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, +/*0050*/ 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, +/*0060*/ 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, +/*0070*/ 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, +/*0080*/ 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, +/*0090*/ 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, +/*00a0*/ 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, +/*00b0*/ 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, +/*00c0*/ 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, +/*00d0*/ 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, +/*00e0*/ 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, +/*00f0*/ 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, +/*0100*/ 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, +/*0110*/ 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, +/*0120*/ 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, +/*0130*/ 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, +/*0140*/ 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, +/*0150*/ 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, +/*0160*/ 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, +/*0170*/ 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, +/*0180*/ 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, +/*0190*/ 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, +/*01a0*/ 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, +/*01b0*/ 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, +/*01c0*/ 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, +/*01d0*/ 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, +/*01e0*/ 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, +/*01f0*/ 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, +/*0200*/ 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, +/*0210*/ 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, +/*0220*/ 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, +/*0230*/ 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, +/*0240*/ 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, +/*0250*/ 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, +/*0260*/ 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, +/*0270*/ 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, +/*0280*/ 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, +/*0290*/ 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, +/*02a0*/ 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, +/*02b0*/ 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, +/*02c0*/ 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, +/*02d0*/ 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, +/*02e0*/ 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x01, 0x10, 0xF9, +/*02f0*/ 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, +/*0300*/ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x03, 0x05, 0x24, 0x40, 0x2F, 0x00, 0x0C, 0x06, 0x03, 0x05, 0x24, +/*0310*/ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, +/*0320*/ 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, +/*0330*/ 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, +/*0340*/ 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, +/*0350*/ 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, +/*0360*/ 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, +/*0370*/ 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, +/*0380*/ 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, +/*0390*/ 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, +/*03a0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, +/*03b0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, +/*03c0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, +/*03d0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, +/*03e0*/ 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, +/*03f0*/ 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, +/*0400*/ 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, +/*0410*/ 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, +/*0420*/ 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09, +}; diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.h b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 0000000000..073bf5229b --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,118 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _QUADSPI_BOOT_H_ +#define _QUADSPI_BOOT_H_ + +#include + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +#define IVT_TAG_HEADER (0xD1) /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) + +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) +#define IVT_RSVD (uint32_t)(0x00000000) + + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_VERSION (0x40) +#define DCD_ARRAY_SIZE 1 + +#define FLASH_BASE 0x60000000 +#define FLASH_END 0x7F7FFFFF +#define SCLK 1 + +#define DCD_ADDRESS dcd_sdram +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +extern const uint8_t dcd_sdram[1072]; +extern const BOOT_DATA_T boot_data; + +#endif diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.c b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.c new file mode 100644 index 0000000000..67076dd62f --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.c @@ -0,0 +1,76 @@ +/* + * The Clear BSD License + * Copyright 2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexspi_nor_flash.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(__CC_ARM) || defined(__GNUC__) + __attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.conf" +#endif + +const flexspi_nor_config_t hyperflash_config = +{ + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = (1u << kFlexSpiMiscOffset_DdrModeEnable) | + (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | + (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, +}; diff --git a/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.h b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.h new file mode 100644 index 0000000000..6d3b5269cd --- /dev/null +++ b/bsp/imxrt/imxrt1050-ArchMix/xip/fsl_flexspi_nor_flash.h @@ -0,0 +1,299 @@ +/* + * The Clear BSD License + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FLEXSPI_NOR_FLASH_H__ +#define __FLEXSPI_NOR_FLASH_H__ + +#include +#include +#include "fsl_common.h" + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif // __FLEXSPI_NOR_FLASH_H__