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format code

This commit is contained in:
bigmagic123 2021-05-21 18:39:41 +08:00
parent a5503a4a71
commit d6f5fbcd5b
16 changed files with 65 additions and 70 deletions
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4
bsp/qemu-riscv-virt64/driver/board.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2020, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -55,7 +55,7 @@ void rt_hw_board_init(void)
#endif /* RT_USING_CONSOLE */ #endif /* RT_USING_CONSOLE */
rt_hw_tick_init(); rt_hw_tick_init();
rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END); rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t) RT_HW_HEAP_BEGIN, (rt_ubase_t) RT_HW_HEAP_END);
#ifdef RT_USING_COMPONENTS_INIT #ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init(); rt_components_board_init();
#endif #endif

2
bsp/qemu-riscv-virt64/driver/board.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2020, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

6
bsp/qemu-riscv-virt64/driver/drv_uart.c
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@ -84,7 +84,7 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
} }
static int drv_uart_putc(struct rt_serial_device *serial, char c) static int drv_uart_putc(struct rt_serial_device *serial, char c)
{ {
while ((uart_read_reg(LSR) & LSR_TX_IDLE) == 0); while ((uart_read_reg(LSR) & LSR_TX_IDLE) == 0);
return uart_write_reg(THR, c); return uart_write_reg(THR, c);
} }
@ -143,9 +143,9 @@ int rt_hw_uart_init(void)
RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart); uart);
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart"); rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart");
rt_hw_interrupt_umask(uart->irqno); rt_hw_interrupt_umask(uart->irqno);
} }
return 0; return 0;
} }

2
bsp/qemu-riscv-virt64/driver/io.h
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@ -49,4 +49,4 @@ static inline uint32_t read_reg(
return readl(addr + offset); return readl(addr + offset);
} }
#endif // ARCH_IO_H #endif // ARCH_IO_H

36
bsp/qemu-riscv-virt64/driver/plic.c
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@ -13,14 +13,14 @@
#include "encoding.h" #include "encoding.h"
/* /*
* Each PLIC interrupt source can be assigned a priority by writing * Each PLIC interrupt source can be assigned a priority by writing
* to its 32-bit memory-mapped priority register. * to its 32-bit memory-mapped priority register.
* The QEMU-virt (the same as FU540-C000) supports 7 levels of priority. * The QEMU-virt (the same as FU540-C000) supports 7 levels of priority.
* A priority value of 0 is reserved to mean "never interrupt" and * A priority value of 0 is reserved to mean "never interrupt" and
* effectively disables the interrupt. * effectively disables the interrupt.
* Priority 1 is the lowest active priority, and priority 7 is the highest. * Priority 1 is the lowest active priority, and priority 7 is the highest.
* Ties between global interrupts of the same priority are broken by * Ties between global interrupts of the same priority are broken by
* the Interrupt ID; interrupts with the lowest ID have the highest * the Interrupt ID; interrupts with the lowest ID have the highest
* effective priority. * effective priority.
*/ */
void plic_set_priority(int irq, int priority) void plic_set_priority(int irq, int priority)
@ -29,7 +29,7 @@ void plic_set_priority(int irq, int priority)
} }
/* /*
* Each global interrupt can be enabled by setting the corresponding * Each global interrupt can be enabled by setting the corresponding
* bit in the enables registers. * bit in the enables registers.
*/ */
void plic_irq_enable(int irq) void plic_irq_enable(int irq)
@ -49,7 +49,7 @@ void plic_irq_disable(int irq)
*(uint32_t*)PLIC_ENABLE(hart) = (((*(uint32_t*)PLIC_ENABLE(hart)) & (~(1 << irq)))); *(uint32_t*)PLIC_ENABLE(hart) = (((*(uint32_t*)PLIC_ENABLE(hart)) & (~(1 << irq))));
} }
/* /*
* PLIC will mask all interrupts of a priority less than or equal to threshold. * PLIC will mask all interrupts of a priority less than or equal to threshold.
* Maximum threshold is 7. * Maximum threshold is 7.
* For example, a threshold value of zero permits all interrupts with * For example, a threshold value of zero permits all interrupts with
@ -62,16 +62,16 @@ void plic_set_threshold(int threshold)
*(uint32_t*)PLIC_THRESHOLD(hart) = threshold; *(uint32_t*)PLIC_THRESHOLD(hart) = threshold;
} }
/* /*
* DESCRIPTION: * DESCRIPTION:
* Query the PLIC what interrupt we should serve. * Query the PLIC what interrupt we should serve.
* Perform an interrupt claim by reading the claim register, which * Perform an interrupt claim by reading the claim register, which
* returns the ID of the highest-priority pending interrupt or zero if there * returns the ID of the highest-priority pending interrupt or zero if there
* is no pending interrupt. * is no pending interrupt.
* A successful claim also atomically clears the corresponding pending bit * A successful claim also atomically clears the corresponding pending bit
* on the interrupt source. * on the interrupt source.
* RETURN VALUE: * RETURN VALUE:
* the ID of the highest-priority pending interrupt or zero if there * the ID of the highest-priority pending interrupt or zero if there
* is no pending interrupt. * is no pending interrupt.
*/ */
int plic_claim(void) int plic_claim(void)
@ -81,12 +81,12 @@ int plic_claim(void)
return irq; return irq;
} }
/* /*
* DESCRIPTION: * DESCRIPTION:
* Writing the interrupt ID it received from the claim (irq) to the * Writing the interrupt ID it received from the claim (irq) to the
* complete register would signal the PLIC we've served this IRQ. * complete register would signal the PLIC we've served this IRQ.
* The PLIC does not check whether the completion ID is the same as the * The PLIC does not check whether the completion ID is the same as the
* last claim ID for that target. If the completion ID does not match an * last claim ID for that target. If the completion ID does not match an
* interrupt source that is currently enabled for the target, the completion * interrupt source that is currently enabled for the target, the completion
* is silently ignored. * is silently ignored.
* RETURN VALUE: none * RETURN VALUE: none

4
bsp/qemu-riscv-virt64/driver/plic.h
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@ -15,7 +15,7 @@
/* /*
* This machine puts platform-level interrupt controller (PLIC) here. * This machine puts platform-level interrupt controller (PLIC) here.
* Here only list PLIC registers in Machine mode. * Here only list PLIC registers in Machine mode.
* *
*/ */
#define VIRT_PLIC_BASE 0x0c000000L #define VIRT_PLIC_BASE 0x0c000000L
@ -49,8 +49,6 @@
#define PLIC_PRIORITY(id) (VIRT_PLIC_BASE + PLIC_PRIORITY_OFFSET + (id) * 4) #define PLIC_PRIORITY(id) (VIRT_PLIC_BASE + PLIC_PRIORITY_OFFSET + (id) * 4)
#define PLIC_PENDING(id) (VIRT_PLIC_BASE + PLIC_PENDING_OFFSET + ((id) / 32)) #define PLIC_PENDING(id) (VIRT_PLIC_BASE + PLIC_PENDING_OFFSET + ((id) / 32))
void plic_set_priority(int irq, int priority); void plic_set_priority(int irq, int priority);
void plic_irq_enable(int irq); void plic_irq_enable(int irq);
void plic_irq_disable(int irq); void plic_irq_disable(int irq);

1
libcpu/risc-v/virt64/context_gcc.S
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@ -28,7 +28,6 @@ rt_hw_interrupt_disable:
#endif #endif
ret ret
/* /*
* void rt_hw_interrupt_enable(rt_base_t level); * void rt_hw_interrupt_enable(rt_base_t level);
*/ */

6
libcpu/risc-v/virt64/cpuport.c
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@ -18,17 +18,17 @@
/** /**
* @brief from thread used interrupt context switch * @brief from thread used interrupt context switch
* *
*/ */
volatile rt_ubase_t rt_interrupt_from_thread = 0; volatile rt_ubase_t rt_interrupt_from_thread = 0;
/** /**
* @brief to thread used interrupt context switch * @brief to thread used interrupt context switch
* *
*/ */
volatile rt_ubase_t rt_interrupt_to_thread = 0; volatile rt_ubase_t rt_interrupt_to_thread = 0;
/** /**
* @brief flag to indicate context switch in interrupt or not * @brief flag to indicate context switch in interrupt or not
* *
*/ */
volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;

2
libcpu/risc-v/virt64/cpuport.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

4
libcpu/risc-v/virt64/interrupt.c
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@ -158,7 +158,7 @@ void dump_regs(struct rt_hw_stack_frame *regs)
rt_size_t satp_v = read_csr(satp); rt_size_t satp_v = read_csr(satp);
rt_kprintf("satp = 0x%p\n",satp_v); rt_kprintf("satp = 0x%p\n",satp_v);
const char *mode_str = "Unknown Address Translation/Protection Mode"; const char *mode_str = "Unknown Address Translation/Protection Mode";
switch(__MASKVALUE(satp_v >> 60,__MASK(4))) switch(__MASKVALUE(satp_v >> 60,__MASK(4)))
{ {
case 0: case 0:
@ -188,7 +188,7 @@ void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_st
{ {
case IRQ_M_SOFT: case IRQ_M_SOFT:
{ {
} }
break; break;
case IRQ_M_TIMER: case IRQ_M_TIMER:

2
libcpu/risc-v/virt64/interrupt.h
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@ -24,4 +24,4 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name); void *param, const char *name);
void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_stack_frame *sp); void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_stack_frame *sp);
#endif #endif

2
libcpu/risc-v/virt64/riscv.h
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@ -26,4 +26,4 @@
#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit)) #define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit))
#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit)) #define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit))
#endif #endif

50
libcpu/risc-v/virt64/riscv_io.h
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@ -98,40 +98,40 @@ static inline rt_uint64_t __raw_readq(const volatile void *addr)
/* clang-format off */ /* clang-format off */
#define __io_rbr() do {} while (0) #define __io_rbr() do {} while (0)
#define __io_rar() do {} while (0) #define __io_rar() do {} while (0)
#define __io_rbw() do {} while (0) #define __io_rbw() do {} while (0)
#define __io_raw() do {} while (0) #define __io_raw() do {} while (0)
#define readb_relaxed(c) ({ rt_uint8_t __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; }) #define readb_relaxed(c) ({ rt_uint8_t __v; __io_rbr(); __v = __raw_readb(c); __io_rar(); __v; })
#define readw_relaxed(c) ({ rt_uint16_t __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; }) #define readw_relaxed(c) ({ rt_uint16_t __v; __io_rbr(); __v = __raw_readw(c); __io_rar(); __v; })
#define readl_relaxed(c) ({ rt_uint32_t __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; }) #define readl_relaxed(c) ({ rt_uint32_t __v; __io_rbr(); __v = __raw_readl(c); __io_rar(); __v; })
#define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); }) #define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); })
#define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); }) #define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); })
#define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); }) #define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); })
#if __riscv_xlen != 32 #if __riscv_xlen != 32
#define readq_relaxed(c) ({ rt_uint64_t __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; }) #define readq_relaxed(c) ({ rt_uint64_t __v; __io_rbr(); __v = __raw_readq(c); __io_rar(); __v; })
#define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); }) #define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); })
#endif #endif
#define __io_br() do {} while (0) #define __io_br() do {} while (0)
#define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory"); #define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory");
#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory"); #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory");
#define __io_aw() do {} while (0) #define __io_aw() do {} while (0)
#define readb(c) ({ rt_uint8_t __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; }) #define readb(c) ({ rt_uint8_t __v; __io_br(); __v = __raw_readb(c); __io_ar(); __v; })
#define readw(c) ({ rt_uint16_t __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; }) #define readw(c) ({ rt_uint16_t __v; __io_br(); __v = __raw_readw(c); __io_ar(); __v; })
#define readl(c) ({ rt_uint32_t __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; }) #define readl(c) ({ rt_uint32_t __v; __io_br(); __v = __raw_readl(c); __io_ar(); __v; })
#define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); }) #define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); })
#define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); }) #define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); })
#define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); }) #define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); })
#if __riscv_xlen != 32 #if __riscv_xlen != 32
#define readq(c) ({ rt_uint64_t __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; }) #define readq(c) ({ rt_uint64_t __v; __io_br(); __v = __raw_readq(c); __io_ar(); __v; })
#define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); }) #define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); })
#endif #endif
#endif #endif

2
libcpu/risc-v/virt64/stackframe.h
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@ -152,4 +152,4 @@
.option pop .option pop
.endm .endm
#endif #endif

10
libcpu/risc-v/virt64/tick.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -36,8 +36,7 @@ int tick_isr(void)
#ifdef RISCV_S_MODE #ifdef RISCV_S_MODE
sbi_set_timer(get_ticks() + tick_cycles); sbi_set_timer(get_ticks() + tick_cycles);
#else #else
int id = r_mhartid(); *(uint64_t*)CLINT_MTIMECMP(r_mhartid()) = *(uint64_t*)CLINT_MTIME + tick_cycles;
*(uint64_t*)CLINT_MTIMECMP(id) = *(uint64_t*)CLINT_MTIME + tick_cycles;
#endif #endif
return 0; return 0;
@ -57,14 +56,13 @@ int rt_hw_tick_init(void)
tick_cycles = 40000; tick_cycles = 40000;
/* Set timer */ /* Set timer */
sbi_set_timer(get_ticks() + tick_cycles); sbi_set_timer(get_ticks() + tick_cycles);
/* Enable the Supervisor-Timer bit in SIE */ /* Enable the Supervisor-Timer bit in SIE */
set_csr(sie, SIP_STIP); set_csr(sie, SIP_STIP);
#else #else
clear_csr(mie, MIP_MTIP); clear_csr(mie, MIP_MTIP);
clear_csr(mip, MIP_MTIP); clear_csr(mip, MIP_MTIP);
int id = r_mhartid(); *(uint64_t*)CLINT_MTIMECMP(r_mhartid()) = *(uint64_t*)CLINT_MTIME + interval;
*(uint64_t*)CLINT_MTIMECMP(id) = *(uint64_t*)CLINT_MTIME + interval;
set_csr(mie, MIP_MTIP); set_csr(mie, MIP_MTIP);
#endif #endif
return 0; return 0;

2
libcpu/risc-v/virt64/tick.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *