diff --git a/bsp/renesas/docs/figures/fsp_configure.png b/bsp/renesas/docs/figures/fsp_configure.png
new file mode 100644
index 0000000000..45d2b7a896
Binary files /dev/null and b/bsp/renesas/docs/figures/fsp_configure.png differ
diff --git a/bsp/renesas/docs/figures/mdk_rasc.png b/bsp/renesas/docs/figures/mdk_rasc.png
new file mode 100644
index 0000000000..aeb52c942b
Binary files /dev/null and b/bsp/renesas/docs/figures/mdk_rasc.png differ
diff --git a/bsp/renesas/ebf_qi_min_6m5/README.md b/bsp/renesas/ebf_qi_min_6m5/README.md
index 65348aa15d..f0a1c7e044 100644
--- a/bsp/renesas/ebf_qi_min_6m5/README.md
+++ b/bsp/renesas/ebf_qi_min_6m5/README.md
@@ -134,6 +134,15 @@ void hal_entry(void)
1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp),请使用 FSP 4.4.0 版本
2. 请查看文档:[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
+目前仓库 bsp 默认使能最小体量配置,用户可通过如下步骤使能 env 外设配置:
+
+1. 在 bsp 目录下打开 env 工具,使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件,选择上方导航栏的 `Software Components`配置,打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮,该操作会自动查找当前电脑环境下安装的 fsp 版本,选择指定版本后进入 fsp。
+ ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现,已经存在了一些已经配置完成的外设,此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+ ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env,使能所需的外设配置后保存退出即可。
+
**ENV 配置**
- 如何使用 ENV 工具:[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_sdhi.c b/bsp/renesas/libraries/HAL_Drivers/drv_sdhi.c
index 9390be8ac7..fc88a307af 100644
--- a/bsp/renesas/libraries/HAL_Drivers/drv_sdhi.c
+++ b/bsp/renesas/libraries/HAL_Drivers/drv_sdhi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -503,7 +503,14 @@ struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des)
int rt_hw_sdhi_init(void)
{
+#if defined(BSP_USING_SDHI0)
sdhi.instance = &g_sdmmc0;
+#elif defined(BSP_USING_SDHI1)
+ sdhi.instance = &g_sdmmc1;
+#else
+#error "please defined the g_sdmmc handle"
+#endif
+
sdhi.instance->p_api->open(sdhi.instance->p_ctrl, sdhi.instance->p_cfg);
host = sdio_host_create(&sdhi);
if (host == RT_NULL)
diff --git a/bsp/renesas/ra2l1-cpk/README.md b/bsp/renesas/ra2l1-cpk/README.md
index 463811b840..ba01049006 100644
--- a/bsp/renesas/ra2l1-cpk/README.md
+++ b/bsp/renesas/ra2l1-cpk/README.md
@@ -138,6 +138,15 @@ void hal_entry(void)
3. 如何将 **板级支持包**添加到 FSP 中,请参考文档[如何导入板级支持包](https://www2.renesas.cn/cn/zh/document/gde/1596896?language=zh&r=1596841)
4. 请查看文档:[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
+目前仓库 bsp 默认使能最小体量配置,用户可通过如下步骤使能 env 外设配置:
+
+1. 在 bsp 目录下打开 env 工具,使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件,选择上方导航栏的 `Software Components`配置,打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮,该操作会自动查找当前电脑环境下安装的 fsp 版本,选择指定版本后进入 fsp。
+ ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现,已经存在了一些已经配置完成的外设,此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+ ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env,使能所需的外设配置后保存退出即可。
+
**ENV 配置**
- 如何使用 ENV 工具:[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
@@ -150,7 +159,6 @@ void hal_entry(void)
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
-
## FAQ
### 使用 MDK 的 DEBUG 时如果遇到提示 “Error: Flash Download failed Cortex-M23” 怎么办?
diff --git a/bsp/renesas/ra4m2-eco/README.md b/bsp/renesas/ra4m2-eco/README.md
index db154aeea0..a9f349da29 100644
--- a/bsp/renesas/ra4m2-eco/README.md
+++ b/bsp/renesas/ra4m2-eco/README.md
@@ -130,7 +130,18 @@ void hal_entry(void)
- [RA4M2数据手册](https://bbs.elecfans.com/forum.php?mod=attachment&aid=MTIwMDQxNnxjOTJiOTgyOHwxNjcwNDY2MTg2fDU5NTQxMXwyMzEyNjc4)
**FSP 配置**
+
请查看 [RA-Eco-RA4M2-100PIN开发板资料](https://bbs.elecfans.com/jishu_2312678_1_1.html) 及官网和bsp/renesas/docs中的相关文档
+
+目前仓库 bsp 默认使能最小体量配置,用户可通过如下步骤使能 env 外设配置:
+
+1. 在 bsp 目录下打开 env 工具,使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件,选择上方导航栏的 `Software Components`配置,打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮,该操作会自动查找当前电脑环境下安装的 fsp 版本,选择指定版本后进入 fsp。
+ ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现,已经存在了一些已经配置完成的外设,此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+ ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env,使能所需的外设配置后保存退出即可。
+
**ENV 配置**
- 如何使用 ENV 工具:[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
@@ -143,7 +154,6 @@ void hal_entry(void)
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
-
## FAQ
### 使用 MDK 的 DEBUG 时如果遇到提示 “Error: Flash Download failed Cortex-M33” 怎么办?
diff --git a/bsp/renesas/ra4m2-eco/docs/pictures/fsp_configure.png b/bsp/renesas/ra4m2-eco/docs/pictures/fsp_configure.png
new file mode 100644
index 0000000000..45d2b7a896
Binary files /dev/null and b/bsp/renesas/ra4m2-eco/docs/pictures/fsp_configure.png differ
diff --git a/bsp/renesas/ra4m2-eco/docs/pictures/mdk_rasc.png b/bsp/renesas/ra4m2-eco/docs/pictures/mdk_rasc.png
new file mode 100644
index 0000000000..aeb52c942b
Binary files /dev/null and b/bsp/renesas/ra4m2-eco/docs/pictures/mdk_rasc.png differ
diff --git a/bsp/renesas/ra6m3-ek/README.md b/bsp/renesas/ra6m3-ek/README.md
index bed0e309e7..1b39034704 100644
--- a/bsp/renesas/ra6m3-ek/README.md
+++ b/bsp/renesas/ra6m3-ek/README.md
@@ -138,6 +138,15 @@ void hal_entry(void)
3. 如何将 **”EK-RA6M3板级支持包“**添加到 FSP 中,请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
4. 请查看文档:[使用 FSP 配置外设驱动](../docs/RA系列使用FSP配置外设驱动.md),在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
+目前仓库 bsp 默认使能最小体量配置,用户可通过如下步骤使能 env 外设配置:
+
+1. 在 bsp 目录下打开 env 工具,使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件,选择上方导航栏的 `Software Components`配置,打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮,该操作会自动查找当前电脑环境下安装的 fsp 版本,选择指定版本后进入 fsp。
+ ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现,已经存在了一些已经配置完成的外设,此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+ ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env,使能所需的外设配置后保存退出即可。
+
**ENV 配置**
- 如何使用 ENV 工具:[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
diff --git a/bsp/renesas/ra6m3-ek/board/Kconfig b/bsp/renesas/ra6m3-ek/board/Kconfig
index 293f0cf1aa..55f01122e5 100644
--- a/bsp/renesas/ra6m3-ek/board/Kconfig
+++ b/bsp/renesas/ra6m3-ek/board/Kconfig
@@ -9,6 +9,50 @@ menu "Hardware Drivers Config"
menu "Onboard Peripheral Drivers"
+ menuconfig BSP_USING_FS
+ bool "Enable File System"
+ select RT_USING_DFS
+ default n
+
+ if BSP_USING_FS
+ config BSP_USING_SDCARD_FATFS
+ bool "Enable SDCARD (FATFS)"
+ select BSP_USING_SPI
+ select BSP_USING_SPI1
+ select RT_USING_SPI_MSD
+ select RT_USING_DFS_ELMFAT
+ default n
+ endif
+
+ config BSP_USING_SPI_LCD
+ bool "Enable SPI LCD"
+ select BSP_USING_GPIO
+ select BSP_USING_SPI
+ select BSP_USING_SPI0
+ default n
+
+ menuconfig BSP_USING_LVGL
+ bool "Enable LVGL for LCD"
+ select PKG_USING_LVGL
+ default n
+ if BSP_USING_LVGL
+ config BSP_USING_LCD_ILI9431
+ bool "Enable LVGL for LCD_ILI9431"
+ select PKG_USING_ILI9341
+ select BSP_USING_SPI_LCD
+ default n
+
+ config BSP_USING_LCD_RGB
+ bool "Enable LVGL for LCD_RGB565"
+ select BSP_USING_LCD
+ default n
+
+ config BSP_USING_LVGL_DEMO
+ bool "Enable LVGL demo"
+ select PKG_USING_LV_MUSIC_DEMO
+ default y
+ endif
+
endmenu
menu "On-chip Peripheral Drivers"
@@ -82,21 +126,6 @@ menu "Hardware Drivers Config"
endif
endif
- menuconfig BSP_USING_FS
- bool "Enable File System"
- select RT_USING_DFS
- default n
-
- if BSP_USING_FS
- config BSP_USING_SDCARD_FATFS
- bool "Enable SDCARD (FATFS)"
- select BSP_USING_SPI
- select BSP_USING_SPI1
- select RT_USING_SPI_MSD
- select RT_USING_DFS_ELMFAT
- default n
- endif
-
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
@@ -120,11 +149,6 @@ menu "Hardware Drivers Config"
default n
endif
- config BSP_USING_LCD
- bool "Enable LCD"
- select BSP_USING_GPIO
- default n
-
menuconfig BSP_USING_SCI_SPI
bool "Enable SCI SPI BUS"
default n
@@ -160,13 +184,6 @@ menu "Hardware Drivers Config"
default n
endif
- config BSP_USING_SPI_LCD
- bool "Enable SPI LCD"
- select BSP_USING_GPIO
- select BSP_USING_SPI
- select BSP_USING_SPI0
- default n
-
config BSP_USING_ETH
bool "Enable Ethernet"
select RT_USING_SAL
@@ -174,28 +191,10 @@ menu "Hardware Drivers Config"
select RT_USING_NETDEV
default n
- menuconfig BSP_USING_LVGL
- bool "Enable LVGL for LCD"
- select PKG_USING_LVGL
+ config BSP_USING_LCD
+ bool "Enable LCD"
+ select BSP_USING_GPIO
default n
- if BSP_USING_LVGL
- config BSP_USING_LCD_ILI9431
- bool "Enable LVGL for LCD_ILI9431"
- select PKG_USING_ILI9341
- select BSP_USING_SPI_LCD
- default n
- config BSP_USING_LCD_RGB
- bool "Enable LVGL for LCD_RGB565"
- select BSP_USING_LCD
- default n
- endif
-
- if BSP_USING_LVGL
- config BSP_USING_LVGL_DEMO
- bool "Enable LVGL demo"
- select PKG_USING_LV_MUSIC_DEMO
- default y
- endif
endmenu
diff --git a/bsp/renesas/ra6m3-hmi-board/.config b/bsp/renesas/ra6m3-hmi-board/.config
index ba9b331d6b..b3d109b7a4 100644
--- a/bsp/renesas/ra6m3-hmi-board/.config
+++ b/bsp/renesas/ra6m3-hmi-board/.config
@@ -9,6 +9,7 @@
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_AMP is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_CPUS_NR=1
@@ -21,6 +22,7 @@ CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
@@ -38,7 +40,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_USING_DEBUG=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
-CONFIG_RT_DEBUGING_INIT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
#
# Inter-Thread communication
@@ -69,11 +71,13 @@ CONFIG_RT_USING_HEAP=y
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREDSAFE_PRINTF is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart9"
CONFIG_RT_VER_NUM=0x50100
# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# CONFIG_RT_USING_CACHE is not set
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
@@ -210,6 +214,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
#
# Utilities
#
@@ -222,11 +232,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
-#
-# Memory management
-#
-# CONFIG_RT_USING_MEMBLOCK is not set
-
#
# RT-Thread Utestcases
#
@@ -272,6 +277,16 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CYW43012 WiFi
#
# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
@@ -293,7 +308,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
-# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -315,6 +329,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
@@ -335,6 +350,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_WOL is not set
# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
#
# security packages
@@ -535,6 +551,9 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_MLIBC is not set
# CONFIG_PKG_USING_TASK_MSG_BUS is not set
# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
#
# peripheral libraries and drivers
@@ -701,6 +720,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_BT_ECB02C is not set
# CONFIG_PKG_USING_UAT is not set
# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
#
@@ -715,6 +738,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
#
# Signal Processing and Control Algorithm Packages
@@ -756,12 +780,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
@@ -799,6 +825,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
@@ -806,13 +833,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -857,7 +884,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -896,7 +923,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -919,7 +945,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -927,7 +953,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -940,6 +966,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
#
# Display
@@ -981,11 +1008,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
@@ -1014,6 +1041,7 @@ CONFIG_SOC_SERIES_R7FA6M3=y
# CONFIG_SOC_SERIES_R7FA2L1 is not set
# CONFIG_SOC_SERIES_R7FA6M5 is not set
# CONFIG_SOC_SERIES_R7FA4M2 is not set
+# CONFIG_SOC_SERIES_R7FA8M85 is not set
#
# Hardware Drivers Config
@@ -1023,6 +1051,10 @@ CONFIG_SOC_R7FA6M4AF=y
#
# Onboard Peripheral Drivers
#
+# CONFIG_BSP_USING_ARDUINO is not set
+# CONFIG_BSP_USING_FS is not set
+# CONFIG_BSP_USING_SPI_LCD is not set
+# CONFIG_BSP_USING_LVGL is not set
#
# On-chip Peripheral Drivers
@@ -1041,17 +1073,16 @@ CONFIG_BSP_UART9_TX_BUFSIZE=0
# CONFIG_BSP_USING_SCI_SPI is not set
# CONFIG_BSP_USING_SCI is not set
# CONFIG_BSP_USING_SPI is not set
-# CONFIG_BSP_USING_FS is not set
-# CONFIG_BSP_USING_SDHI is not set
+# CONFIG_BSP_USING_SOFT_I2C is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_DAC is not set
# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_SDHI is not set
# CONFIG_BSP_USING_CAN is not set
-# CONFIG_BSP_USING_LCD is not set
-# CONFIG_BSP_USING_SPI_LCD is not set
# CONFIG_BSP_USING_G2D is not set
# CONFIG_BSP_USING_JPEG is not set
# CONFIG_BSP_USING_ETH is not set
-# CONFIG_BSP_USING_LVGL is not set
-# CONFIG_BSP_USING_LVGL_DEMO is not set
+# CONFIG_BSP_USING_LCD is not set
#
# Board extended module Drivers
diff --git a/bsp/renesas/ra6m3-hmi-board/.settings/standalone.prefs b/bsp/renesas/ra6m3-hmi-board/.settings/standalone.prefs
index f1d840075d..34f2625e03 100644
--- a/bsp/renesas/ra6m3-hmi-board/.settings/standalone.prefs
+++ b/bsp/renesas/ra6m3-hmi-board/.settings/standalone.prefs
@@ -1,24 +1,43 @@
-#Wed Jan 10 09:43:46 CST 2024
+#Thu Feb 01 19:29:48 CST 2024
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/all=143358381,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|3427620923,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|2743353138,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sdhi\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_glcdc\#\#\#\#3.5.0/all=2184024064,ra/fsp/inc/api/r_display_api.h|2697709197,ra/fsp/inc/instances/r_glcdc.h|652452323,ra/fsp/src/r_glcdc/r_glcdc.c
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_drw\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_adc\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.sdmmc_on_sdmmc.772252884=false
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|1728953905,ra/fsp/inc/fsp_features.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|1939984091,ra/fsp/inc/api/r_ioport_api.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|2425160085,ra/fsp/inc/api/bsp_api.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|546480625,ra/fsp/inc/fsp_common_api.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|3297195641,ra/fsp/inc/fsp_version.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#3.5.0/all=2886639616,ra/fsp/inc/instances/r_gpt.h|1958999550,ra/fsp/src/r_gpt/r_gpt.c|232390045,ra/fsp/inc/api/r_timer_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_jpeg\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/all=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dmac\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_adc\#\#\#\#3.5.0/all=1675086128,ra/fsp/inc/api/r_adc_api.h|4250819551,ra/fsp/inc/instances/r_adc.h|1515334001,ra/fsp/inc/api/r_elc_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|377989633,ra/fsp/src/r_adc/r_adc.c
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.drw.2023623840=false
+com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_phy\#\#\#\#3.5.0/all=1059783364,ra/fsp/inc/instances/r_ether_phy.h|4014538643,ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c|451576276,ra/fsp/src/r_ether_phy/r_ether_phy.c|809828733,ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c|180607401,ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c|2050444946,ra/fsp/inc/api/r_ether_phy_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/all=143358381,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|2743353138,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h|3427620923,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether_phy\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_glcdc\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_drw\#\#\#\#3.5.0/all=3233980366,ra/fsp/src/r_drw/r_drw_base.h|1769767553,ra/fsp/src/r_drw/r_drw_irq.c|954903398,ra/fsp/src/r_drw/r_drw_memory.c|2504224105,ra/fsp/src/r_drw/r_drw_base.c
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.552817864=false
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|2208590403,ra/fsp/inc/instances/r_ioport.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|2425160085,ra/fsp/inc/api/bsp_api.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|3297195641,ra/fsp/inc/fsp_version.h|546480625,ra/fsp/inc/fsp_common_api.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|1728953905,ra/fsp/inc/fsp_features.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ether\#\#\#\#3.5.0/all=1270768113,ra/fsp/inc/api/r_ether_api.h|1142959831,ra/fsp/inc/instances/r_ether.h|3906530552,ra/fsp/src/r_ether/r_ether.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFB\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#3.5.0/libraries=
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#3.5.0/all=1958999550,ra/fsp/src/r_gpt/r_gpt.c|2886639616,ra/fsp/inc/instances/r_gpt.h|232390045,ra/fsp/inc/api/r_timer_api.h
-com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.ether_on_ether.803249625=false
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/all=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_adc\#\#\#\#3.5.0/all=1675086128,ra/fsp/inc/api/r_adc_api.h|1515334001,ra/fsp/inc/api/r_elc_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|4250819551,ra/fsp/inc/instances/r_adc.h|377989633,ra/fsp/src/r_adc/r_adc.c
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=2208590403,ra/fsp/inc/instances/r_ioport.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/libraries=
-com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1610456547,ra/fsp/inc/api/r_transfer_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h|3916852077,ra/fsp/inc/api/r_uart_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#TES\#\#all\#\#dave2d\#\#\#\#3.8.0+fsp.3.5.0/all=2215077823,ra/tes/dave2d/src/dave_rbuffer.c|3704715329,ra/tes/dave2d/src/dave_memory.c|3149640059,ra/tes/dave2d/src/dave_memory.h|1272314146,ra/tes/dave2d/src/dave_utility.h|1667194484,ra/tes/dave2d/src/dave_texture.c|19256155,ra/tes/dave2d/src/dave_rbuffer.h|854854709,ra/tes/dave2d/src/dave_utility.c|2705060082,ra/tes/dave2d/src/dave_wedge.c|3240215282,ra/tes/dave2d/src/dave_wedge.h|3259479650,ra/tes/dave2d/inc/dave_types.h|3336375023,ra/tes/dave2d/inc/dave_driver.h|664191450,ra/tes/dave2d/src/dave_base.c|1880348197,ra/tes/dave2d/src/dave_box.c|4274014154,ra/tes/dave2d/inc/dave_base.h|505727753,ra/tes/dave2d/src/dave_circle.h|2339698747,ra/tes/dave2d/src/dave_driver.c|1842111830,ra/tes/dave2d/src/dave_circle.c|2550235696,ra/tes/dave2d/src/dave_64bitoperation.c|3002603095,ra/tes/dave2d/src/dave_texture.h|3061592116,ra/tes/dave2d/src/dave_polyline.c|1870326063,ra/tes/dave2d/src/dave_line.h|3157839062,ra/tes/dave2d/src/dave_polyline.h|1157276490,ra/tes/dave2d/src/dave_box.h|2824134536,ra/tes/dave2d/src/dave_context.h|3457567489,ra/tes/dave2d/src/dave_dlist.h|1070173993,ra/tes/dave2d/src/dave_line.c|2044860670,ra/tes/dave2d/src/dave_context.c|650027296,ra/tes/dave2d/src/dave_dlist.c|780382921,ra/tes/dave2d/inc/dave_errorcodes.h|326743887,ra/tes/dave2d/src/dave_pattern.c|1058031483,ra/tes/dave2d/src/dave_hardware.c|3811113047,ra/tes/dave2d/src/dave_registermap.h|2548764085,ra/tes/dave2d/src/dave_pattern.h|1138885174,ra/tes/dave2d/src/dave_hardware.h|113917492,ra/tes/dave2d/src/dave_render.c|635745031,ra/tes/dave2d/src/dave_perfcount.c|2658601565,ra/tes/dave2d/src/dave_intern.h|1572823813,ra/tes/dave2d/src/dave_errorcodes.c|1996099915,ra/tes/dave2d/src/dave_render.h|2458077439,ra/tes/dave2d/src/dave_triangle.c|736824288,ra/tes/dave2d/src/dave_viewport.c|2967595566,ra/tes/dave2d/src/dave_quad.c|1797619041,ra/tes/dave2d/src/dave_blit.c|3700209682,ra/tes/dave2d/src/dave_triangle.h|1596456334,ra/tes/dave2d/src/dave_math.c|1305118771,ra/tes/dave2d/src/dave_quad.h|957747704,ra/tes/dave2d/src/dave_curve.c|2723427531,ra/tes/dave2d/src/dave_curve.h|2697296305,ra/tes/dave2d/src/dave_edge.h|841632015,ra/tes/dave2d/src/dave_viewport.h|1742818937,ra/tes/dave2d/src/dave_edge.c|1024774572,ra/tes/dave2d/inc/dave_math.h|4022437848,ra/tes/dave2d/src/dave_triarray.h|1181118735,ra/tes/dave2d/src/dave_gradient.c|2742308643,ra/tes/dave2d/src/dave_gradient.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1889256766,ra/fsp/inc/instances/r_sci_uart.h|3916852077,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.606654632=false
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dmac\#\#\#\#3.5.0/all=1279195077,ra/fsp/src/r_dmac/r_dmac.c|1610456547,ra/fsp/inc/api/r_transfer_api.h|4244470293,ra/fsp/inc/instances/r_dmac.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#TES\#\#all\#\#dave2d\#\#\#\#3.8.0+fsp.3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_jpeg\#\#\#\#3.5.0/all=2385517940,ra/fsp/src/r_jpeg/r_jpeg.c|2329302167,ra/fsp/inc/api/r_jpeg_api.h|2387419434,ra/fsp/inc/instances/r_jpeg.h
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sdhi\#\#\#\#3.5.0/all=48432700,ra/fsp/src/r_sdhi/r_sdhi.c|2842545360,ra/fsp/inc/instances/r_sdhi.h|1057256313,ra/fsp/src/r_sdhi/r_sdhi_private.h|1515334001,ra/fsp/inc/api/r_elc_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h|612015131,ra/fsp/inc/api/r_sdmmc_api.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=
diff --git a/bsp/renesas/ra6m3-hmi-board/README.md b/bsp/renesas/ra6m3-hmi-board/README.md
index c8a6c3e4df..0e062235e7 100644
--- a/bsp/renesas/ra6m3-hmi-board/README.md
+++ b/bsp/renesas/ra6m3-hmi-board/README.md
@@ -146,6 +146,19 @@ The steps are as follows:
3. Enter the `pkgs --update` command to update the software package.
4. Enter the `scons --target=mdk5` command to regenerate the project.
+**FSP Configuration**
+
+* How to Use FSP: [Configuring Peripheral Drivers for RA Series Using FSP](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)
+
+The current repository's BSP is configured with the minimum footprint enabled by default. Users can enable peripheral configurations through the following steps:
+
+1. Open the `env` tool in the BSP directory and use the `scons --target=mdk5` command to generate an MDK project.
+2. Open the `project.uvprojx` file in the BSP directory, select the `Software Components` configuration in the top navigation bar, and open the configuration button next to `RA Configuration` under `Flex Software`. This operation will automatically detect the installed FSP version on the current computer. After selecting the specified version, enter FSP.
+ ![](../docs/figures/mdk_rasc.png)
+3. Upon entering FSP, pre-configured peripherals are already present. Click the `Generate Project Content` button to generate the required driver files.
+ ![](../docs/figures/fsp_configure.png)
+4. Return to `env`, enable the necessary peripheral configurations, save, and exit.
+
## Contribute the Code
If you’re interested in the HMI-Board and have some cool projects you’d like to share with everyone, we’d love for you to contribute your code! You can check out [how to contribute to RT-Thread’s code](https://www.rt-thread.io/contribution.html). Let’s make something awesome together!
\ No newline at end of file
diff --git a/bsp/renesas/ra6m3-hmi-board/README_ZH.md b/bsp/renesas/ra6m3-hmi-board/README_ZH.md
index 8425590253..0e7af87312 100644
--- a/bsp/renesas/ra6m3-hmi-board/README_ZH.md
+++ b/bsp/renesas/ra6m3-hmi-board/README_ZH.md
@@ -148,6 +148,19 @@ void hal_entry(void)
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
+**FSP配置**
+
+* 如何使用 FSP:[RA系列使用 FSP 配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)
+
+目前仓库 bsp 默认使能最小体量配置,用户可通过如下步骤使能 env 外设配置:
+
+1. 在 bsp 目录下打开 env 工具,使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件,选择上方导航栏的 `Software Components`配置,打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮,该操作会自动查找当前电脑环境下安装的 fsp 版本,选择指定版本后进入 fsp。
+ ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现,已经存在了一些已经配置完成的外设,此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+ ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env,使能所需的外设配置后保存退出即可。
+
## 联系人信息
在使用过程中若您有任何的想法和建议,建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
diff --git a/bsp/renesas/ra6m3-hmi-board/board/Kconfig b/bsp/renesas/ra6m3-hmi-board/board/Kconfig
index 7db806896e..8e4c8186e0 100644
--- a/bsp/renesas/ra6m3-hmi-board/board/Kconfig
+++ b/bsp/renesas/ra6m3-hmi-board/board/Kconfig
@@ -25,7 +25,81 @@ menu "Hardware Drivers Config"
imply RTDUINO_USING_SERVO
imply RTDUINO_USING_WIRE
default n
-
+
+ menuconfig BSP_USING_FS
+ bool "Enable filesystem"
+ default n
+ if BSP_USING_FS
+ config BSP_USING_SDCARD_FS
+ bool "Enable SDCARD filesystem"
+ select BSP_USING_SDHI
+ select BSP_USING_SDHI1
+ select RT_USING_DFS_ELMFAT
+ default n
+ config BSP_USING_SPICARD_FS
+ bool "Enable SPI FLASH filesystem"
+ select BSP_USING_SPI
+ select BSP_USING_SCI_SPI6
+ select RT_USING_SPI_MSD
+ select RT_USING_DFS_ELMFAT
+ default n
+ endif
+
+ config BSP_USING_SPI_LCD
+ bool "Enable SPI LCD"
+ select BSP_USING_GPIO
+ select BSP_USING_SPI
+ select BSP_USING_SPI0
+ default n
+
+ menuconfig BSP_USING_LVGL
+ bool "Enable LVGL for LCD"
+ select PKG_USING_LVGL
+ default n
+ if BSP_USING_LVGL
+ config BSP_USING_LCD_ILI9431
+ bool "Enable LVGL for LCD_ILI9431"
+ select PKG_USING_ILI9341
+ select BSP_USING_SPI_LCD
+ default n
+ config BSP_USING_LCD_RGB
+ bool "Enable LVGL for LCD_RGB565"
+ select BSP_USING_LCD
+ select RT_USING_TOUCH
+ select RT_TOUCH_PIN_IRQ
+ default n
+ if BSP_USING_LCD_RGB
+ config BSP_USING_TOUCH
+ bool "Enable Touch GT911"
+ select BSP_USING_SOFT_I2C
+ select BSP_USING_I2C0
+ default y
+ endif
+
+ menuconfig BSP_USING_LVGL_DEMO
+ bool "Enable LVGL demo for LCD"
+ if BSP_USING_LVGL_DEMO
+ choice
+ prompt "choice lvgl demo"
+ default BSP_USING_LVGL_MUSIC_DEMO
+
+ config BSP_USING_LVGL_MUSIC_DEMO
+ bool "Enable LVGL music demo"
+ select BSP_USING_G2D
+ select PKG_USING_LV_MUSIC_DEMO
+
+ config BSP_USING_LVGL_VIDEO_DEMO
+ bool "Enable LVGL video demo"
+ select BSP_USING_G2D
+ select BSP_USING_JPEG
+ select BSP_USING_FS
+ select BSP_USING_SDCARD_FS
+ endchoice
+ endif
+ endif
+
+
+
endmenu
menu "On-chip Peripheral Drivers"
@@ -506,37 +580,6 @@ menu "Hardware Drivers Config"
default n
endif
- menuconfig BSP_USING_FS
- bool "Enable filesystem"
- default n
- if BSP_USING_FS
- config BSP_USING_SDCARD_FS
- bool "Enable SDCARD filesystem"
- select BSP_USING_SDHI
- select RT_USING_DFS_ELMFAT
- default n
- config BSP_USING_SPICARD_FS
- bool "Enable SPI FLASH filesystem"
- select BSP_USING_SPI
- select BSP_USING_SCI_SPI6
- select RT_USING_SPI_MSD
- select RT_USING_DFS_ELMFAT
- default n
- endif
-
- menuconfig BSP_USING_SDHI
- bool "Enable SDHI"
- default n
- select RT_USING_SDIO
- select RT_USING_DFS
- select RT_LIBC_USING_FILEIO
- select RT_USING_POSIX_DEVIO
- if BSP_USING_SDHI
- config SDHI_USING_1_BIT
- bool "Use 1-bit Mode(4-bit when disable)"
- default y
- endif
-
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
@@ -556,6 +599,32 @@ menu "Hardware Drivers Config"
endif
+ menuconfig BSP_USING_SDHI
+ bool "Enable SDHI"
+ default n
+ select RT_USING_SDIO
+ select RT_USING_DFS
+ select RT_LIBC_USING_FILEIO
+ select RT_USING_POSIX_DEVIO
+ if BSP_USING_SDHI
+ menuconfig BSP_USING_SDHI0
+ bool "Enable SDHI0"
+ default n
+ if BSP_USING_SDHI0
+ config SDHI_USING_1_BIT
+ bool "Use 1-bit Mode(4-bit when disable)"
+ default y
+ endif
+
+ menuconfig BSP_USING_SDHI1
+ bool "Enable SDHI1"
+ default n
+ if BSP_USING_SDHI1
+ config SDHI_USING_1_BIT
+ bool "Use 1-bit Mode(4-bit when disable)"
+ default y
+ endif
+ endif
menuconfig BSP_USING_CAN
bool "Enable CAN"
@@ -567,18 +636,6 @@ menu "Hardware Drivers Config"
default n
endif
- config BSP_USING_LCD
- bool "Enable LCD"
- select BSP_USING_GPIO
- default n
-
- config BSP_USING_SPI_LCD
- bool "Enable SPI LCD"
- select BSP_USING_GPIO
- select BSP_USING_SPI
- select BSP_USING_SPI0
- default n
-
config BSP_USING_G2D
bool "Enable G2D"
default n
@@ -594,39 +651,10 @@ menu "Hardware Drivers Config"
select RT_USING_NETDEV
default n
- menuconfig BSP_USING_LVGL
- bool "Enable LVGL for LCD"
- select PKG_USING_LVGL
+ config BSP_USING_LCD
+ bool "Enable LCD"
+ select BSP_USING_GPIO
default n
- if BSP_USING_LVGL
- config BSP_USING_LCD_ILI9431
- bool "Enable LVGL for LCD_ILI9431"
- select PKG_USING_ILI9341
- select BSP_USING_SPI_LCD
- default n
- config BSP_USING_LCD_RGB
- bool "Enable LVGL for LCD_RGB565"
- select BSP_USING_LCD
- default n
- endif
-
- menuconfig BSP_USING_LVGL_DEMO
- bool "Enable LVGL demo for LCD"
- if BSP_USING_LVGL_DEMO
- choice
- prompt "choice lvgl demo"
- default BSP_USING_LVGL_MUSIC_DEMO
-
- config BSP_USING_LVGL_MUSIC_DEMO
- bool "Enable LVGL music demo"
- select PKG_USING_LV_MUSIC_DEMO
-
- config BSP_USING_LVGL_VIDEO_DEMO
- bool "Enable LVGL video demo"
- select BSP_USING_G2D
- select BSP_USING_JPEG
- endchoice
- endif
endmenu
diff --git a/bsp/renesas/ra6m3-hmi-board/buildinfo.gpdsc b/bsp/renesas/ra6m3-hmi-board/buildinfo.gpdsc
index 53e32c454d..c1dc7dfc09 100644
--- a/bsp/renesas/ra6m3-hmi-board/buildinfo.gpdsc
+++ b/bsp/renesas/ra6m3-hmi-board/buildinfo.gpdsc
@@ -22,6 +22,7 @@
+
@@ -58,8 +59,13 @@
+
+
+
+
+
@@ -67,66 +73,122 @@
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
-
-
-
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -140,9 +202,16 @@
+
+
+
+
+
+
+
diff --git a/bsp/renesas/ra6m3-hmi-board/configuration.xml b/bsp/renesas/ra6m3-hmi-board/configuration.xml
index 681297d6dd..13558297fa 100644
--- a/bsp/renesas/ra6m3-hmi-board/configuration.xml
+++ b/bsp/renesas/ra6m3-hmi-board/configuration.xml
@@ -173,6 +173,38 @@
General PWM Timer
Renesas.RA.3.5.0.pack
+
+ TES DAVE 2D Drawing Engine
+ TES.Dave2D.3.8.0+fsp.3.5.0.pack
+
+
+ Direct Memory Access Controller
+ Renesas.RA.3.5.0.pack
+
+
+ TES D/AVE 2D Port
+ Renesas.RA.3.5.0.pack
+
+
+ Ethernet PHY
+ Renesas.RA.3.5.0.pack
+
+
+ Ethernet
+ Renesas.RA.3.5.0.pack
+
+
+ Graphics LCD Controller
+ Renesas.RA.3.5.0.pack
+
+
+ JPEG Codec
+ Renesas.RA.3.5.0.pack
+
+
+ SD/MMC Host Interface
+ Renesas.RA.3.5.0.pack
+
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diff --git a/bsp/renesas/ra6m3-hmi-board/ra/SConscript b/bsp/renesas/ra6m3-hmi-board/ra/SConscript
index 52e96ac900..294776d305 100644
--- a/bsp/renesas/ra6m3-hmi-board/ra/SConscript
+++ b/bsp/renesas/ra6m3-hmi-board/ra/SConscript
@@ -22,5 +22,9 @@ elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
+if GetDepend('BSP_USING_G2D'):
+ src += Glob(cwd + '/tes/dave2d/src/*.c')
+ CPPPATH += [cwd + '/tes/dave2d/inc']
+
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
diff --git a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_adc_api.h b/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_adc_api.h
deleted file mode 100644
index d22d1ef4b4..0000000000
--- a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_adc_api.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
- * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-#ifndef R_ADC_API_H
-#define R_ADC_API_H
-
-/*******************************************************************************************************************//**
- * @ingroup RENESAS_INTERFACES
- * @defgroup ADC_API ADC Interface
- * @brief Interface for A/D Converters.
- *
- * @section ADC_API_SUMMARY Summary
- * The ADC interface provides standard ADC functionality including one-shot mode (single scan), continuous scan and
- * group scan. It also allows configuration of hardware and software triggers for starting scans. After each conversion
- * an interrupt can be triggered, and if a callback function is provided, the call back is invoked with the
- * appropriate event information.
- *
- * Implemented by:
- * @ref ADC
- *
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-
-/* Includes board and MCU related header files. */
-#include "bsp_api.h"
-#include "r_elc_api.h"
-#include "r_transfer_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/**********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/*****************************************************************************
- * Typedef definitions
- ******************************************************************************/
-
-/** ADC operation mode definitions */
-typedef enum e_adc_mode
-{
- ADC_MODE_SINGLE_SCAN = 0, ///< Single scan - one or more channels
- ADC_MODE_GROUP_SCAN = 1, ///< Two trigger sources to trigger scan for two groups which contain one or more channels
- ADC_MODE_CONTINUOUS_SCAN = 2, ///< Continuous scan - one or more channels
-} adc_mode_t;
-
-/** ADC data resolution definitions */
-typedef enum e_adc_resolution
-{
- ADC_RESOLUTION_12_BIT = 0, ///< 12 bit resolution
- ADC_RESOLUTION_10_BIT = 1, ///< 10 bit resolution
- ADC_RESOLUTION_8_BIT = 2, ///< 8 bit resolution
- ADC_RESOLUTION_14_BIT = 3, ///< 14 bit resolution
- ADC_RESOLUTION_16_BIT = 4, ///< 16 bit resolution
- ADC_RESOLUTION_24_BIT = 5, ///< 24 bit resolution
-} adc_resolution_t;
-
-/** ADC data alignment definitions */
-typedef enum e_adc_alignment
-{
- ADC_ALIGNMENT_RIGHT = 0, ///< Data alignment right
- ADC_ALIGNMENT_LEFT = 1 ///< Data alignment left
-} adc_alignment_t;
-
-/** ADC trigger mode definitions */
-typedef enum e_adc_trigger
-{
- ADC_TRIGGER_SOFTWARE = 0, ///< Software trigger; not for group modes
- ADC_TRIGGER_SYNC_ELC = 2, ///< Synchronous trigger via ELC
- ADC_TRIGGER_ASYNC_EXTERNAL = 3, ///< External asynchronous trigger; not for group modes
-} adc_trigger_t;
-
-/** ADC callback event definitions */
-typedef enum e_adc_event
-{
- ADC_EVENT_SCAN_COMPLETE, ///< Normal/Group A scan complete
- ADC_EVENT_SCAN_COMPLETE_GROUP_B, ///< Group B scan complete
- ADC_EVENT_CALIBRATION_COMPLETE, ///< Calibration complete
- ADC_EVENT_CONVERSION_COMPLETE, ///< Conversion complete
- ADC_EVENT_CALIBRATION_REQUEST, ///< Calibration requested
- ADC_EVENT_CONVERSION_ERROR, ///< Scan error
- ADC_EVENT_OVERFLOW, ///< Overflow occurred
- ADC_EVENT_LIMIT_CLIP, ///< Limiter clipping occurred
- ADC_EVENT_FIFO_READ_REQUEST, ///< FIFO read requested
- ADC_EVENT_FIFO_OVERFLOW, ///< FIFO overflow occurred
- ADC_EVENT_WINDOW_COMPARE_A, ///< Window A comparison condition met
- ADC_EVENT_WINDOW_COMPARE_B, ///< Window B comparison condition met
-} adc_event_t;
-
-#ifndef BSP_OVERRIDE_ADC_CHANNEL_T
-
-/** ADC channels */
-typedef enum e_adc_channel
-{
- ADC_CHANNEL_0 = 0, ///< ADC channel 0
- ADC_CHANNEL_1 = 1, ///< ADC channel 1
- ADC_CHANNEL_2 = 2, ///< ADC channel 2
- ADC_CHANNEL_3 = 3, ///< ADC channel 3
- ADC_CHANNEL_4 = 4, ///< ADC channel 4
- ADC_CHANNEL_5 = 5, ///< ADC channel 5
- ADC_CHANNEL_6 = 6, ///< ADC channel 6
- ADC_CHANNEL_7 = 7, ///< ADC channel 7
- ADC_CHANNEL_8 = 8, ///< ADC channel 8
- ADC_CHANNEL_9 = 9, ///< ADC channel 9
- ADC_CHANNEL_10 = 10, ///< ADC channel 10
- ADC_CHANNEL_11 = 11, ///< ADC channel 11
- ADC_CHANNEL_12 = 12, ///< ADC channel 12
- ADC_CHANNEL_13 = 13, ///< ADC channel 13
- ADC_CHANNEL_14 = 14, ///< ADC channel 14
- ADC_CHANNEL_15 = 15, ///< ADC channel 15
- ADC_CHANNEL_16 = 16, ///< ADC channel 16
- ADC_CHANNEL_17 = 17, ///< ADC channel 17
- ADC_CHANNEL_18 = 18, ///< ADC channel 18
- ADC_CHANNEL_19 = 19, ///< ADC channel 19
- ADC_CHANNEL_20 = 20, ///< ADC channel 20
- ADC_CHANNEL_21 = 21, ///< ADC channel 21
- ADC_CHANNEL_22 = 22, ///< ADC channel 22
- ADC_CHANNEL_23 = 23, ///< ADC channel 23
- ADC_CHANNEL_24 = 24, ///< ADC channel 24
- ADC_CHANNEL_25 = 25, ///< ADC channel 25
- ADC_CHANNEL_26 = 26, ///< ADC channel 26
- ADC_CHANNEL_27 = 27, ///< ADC channel 27
- ADC_CHANNEL_28 = 28, ///< ADC channel 28
- ADC_CHANNEL_DUPLEX_A = 50, ///< Data duplexing register A
- ADC_CHANNEL_DUPLEX_B = 51, ///< Data duplexing register B
- ADC_CHANNEL_DUPLEX = -4, ///< Data duplexing register
- ADC_CHANNEL_TEMPERATURE = -3, ///< Temperature sensor output
- ADC_CHANNEL_VOLT = -2, ///< Internal reference voltage
-} adc_channel_t;
-
-#endif
-
-typedef enum e_adc_group_id
-{
- ADC_GROUP_ID_0 = 0, ///< Group ID 0
- ADC_GROUP_ID_1 = 1, ///< Group ID 1
- ADC_GROUP_ID_2 = 2, ///< Group ID 2
- ADC_GROUP_ID_3 = 3, ///< Group ID 3
- ADC_GROUP_ID_4 = 4, ///< Group ID 4
- ADC_GROUP_ID_5 = 5, ///< Group ID 5
- ADC_GROUP_ID_6 = 6, ///< Group ID 6
- ADC_GROUP_ID_7 = 7, ///< Group ID 7
- ADC_GROUP_ID_8 = 8, ///< Group ID 8
-} adc_group_id_t;
-
-typedef enum e_adc_group_mask
-{
- ADC_GROUP_MASK_NONE = 0x000, ///< Group Mask Unknown or None
- ADC_GROUP_MASK_0 = 0x001, ///< Group Mask 0
- ADC_GROUP_MASK_1 = 0x002, ///< Group Mask 1
- ADC_GROUP_MASK_2 = 0x004, ///< Group Mask 2
- ADC_GROUP_MASK_3 = 0x008, ///< Group Mask 3
- ADC_GROUP_MASK_4 = 0x010, ///< Group Mask 4
- ADC_GROUP_MASK_5 = 0x020, ///< Group Mask 5
- ADC_GROUP_MASK_6 = 0x040, ///< Group Mask 6
- ADC_GROUP_MASK_7 = 0x080, ///< Group Mask 7
- ADC_GROUP_MASK_8 = 0x100, ///< Group Mask 8
- ADC_GROUP_MASK_ALL = 0x1FF, ///< All Groups
-} adc_group_mask_t;
-
-/** ADC states. */
-typedef enum e_adc_state
-{
- ADC_STATE_IDLE = 0, ///< ADC is idle
- ADC_STATE_SCAN_IN_PROGRESS = 1, ///< ADC scan in progress
-} adc_state_t;
-
-/** ADC status. */
-typedef struct st_adc_status
-{
- adc_state_t state; ///< Current state
-} adc_status_t;
-
-/** ADC callback arguments definitions */
-typedef struct st_adc_callback_args
-{
- uint16_t unit; ///< ADC device in use
- adc_event_t event; ///< ADC callback event
- void const * p_context; ///< Placeholder for user data
- adc_channel_t channel; ///< Channel of conversion result. Only valid for r_adc ADC_EVENT_CONVERSION_COMPLETE
- uint64_t channel_mask; ///< Channel mask for conversion result. Only valid for r_adc_b
- adc_group_mask_t group_mask; ///< Group Mask
-} adc_callback_args_t;
-
-/** ADC Information Structure for Transfer Interface */
-typedef struct st_adc_info
-{
- __I void * p_address; ///< The address to start reading the data from
- uint32_t length; ///< The total number of transfers to read
-
- transfer_size_t transfer_size; ///< The size of each transfer
- elc_peripheral_t elc_peripheral; ///< Name of the peripheral in the ELC list
- elc_event_t elc_event; ///< Name of the ELC event for the peripheral
- uint32_t calibration_data; ///< Temperature sensor calibration data (0xFFFFFFFF if unsupported) for reference voltage
- int16_t slope_microvolts; ///< Temperature sensor slope in microvolts/degrees C
- bool calibration_ongoing; ///< Calibration is in progress.
-} adc_info_t;
-
-/** ADC general configuration */
-typedef struct st_adc_cfg
-{
- uint16_t unit; ///< ADC unit to be used
- adc_mode_t mode; ///< ADC operation mode
- adc_resolution_t resolution; ///< ADC resolution
- adc_alignment_t alignment; ///< Specify left or right alignment; ignored if addition used
- adc_trigger_t trigger; ///< Default and Group A trigger source
- IRQn_Type scan_end_irq; ///< Scan end IRQ number
- IRQn_Type scan_end_b_irq; ///< Scan end group B IRQ number
- uint8_t scan_end_ipl; ///< Scan end interrupt priority
- uint8_t scan_end_b_ipl; ///< Scan end group B interrupt priority
- void (* p_callback)(adc_callback_args_t * p_args); ///< Callback function; set to NULL for none
- void const * p_context; ///< Placeholder for user data. Passed to the user callback in @ref adc_callback_args_t.
- void const * p_extend; ///< Extension parameter for hardware specific settings
-} adc_cfg_t;
-
-/** ADC control block. Allocate using driver instance control structure from driver instance header file. */
-typedef void adc_ctrl_t;
-
-/** ADC functions implemented at the HAL layer will follow this API. */
-typedef struct st_adc_api
-{
- /** Initialize ADC Unit; apply power, set the operational mode, trigger sources, interrupt priority,
- * and configurations common to all channels and sensors.
- * @par Implemented as
- * - @ref R_ADC_Open()
- * - @ref R_ADC_B_Open()
- * - @ref R_SDADC_Open()
- *
- * @pre Configure peripheral clocks, ADC pins and IRQs prior to calling this function.
- * @param[in] p_ctrl Pointer to control handle structure
- * @param[in] p_cfg Pointer to configuration structure
- */
- fsp_err_t (* open)(adc_ctrl_t * const p_ctrl, adc_cfg_t const * const p_cfg);
-
- /** Configure the scan including the channels, groups, and scan triggers to be used for the unit that
- * was initialized in the open call. Some configurations are not supported for all implementations.
- * See implementation for details.
- * @par Implemented as
- * - @ref R_ADC_ScanCfg()
- * - @ref R_ADC_B_ScanCfg()
- * - @ref R_SDADC_ScanCfg()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- * @param[in] p_extend See implementation for details
- */
- fsp_err_t (* scanCfg)(adc_ctrl_t * const p_ctrl, void const * const p_extend);
-
- /** Start the scan (in case of a software trigger), or enable the hardware trigger.
- * @par Implemented as
- * - @ref R_ADC_ScanStart()
- * - @ref R_SDADC_ScanStart()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- */
- fsp_err_t (* scanStart)(adc_ctrl_t * const p_ctrl);
-
- /** Start the scan group (in case of a software trigger), or enable the hardware trigger.
- * @par Implemented as
- * - @ref R_ADC_B_ScanGroupStart()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- * @param[in] group_mask Mask of groups to start
- */
- fsp_err_t (* scanGroupStart)(adc_ctrl_t * p_ctrl, adc_group_mask_t group_mask);
-
- /** Stop the ADC scan (in case of a software trigger), or disable the hardware trigger.
- * @par Implemented as
- * - @ref R_ADC_ScanStop()
- * - @ref R_SDADC_ScanStop()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- */
- fsp_err_t (* scanStop)(adc_ctrl_t * const p_ctrl);
-
- /** Check scan status.
- * @par Implemented as
- * - @ref R_ADC_StatusGet()
- * - @ref R_ADC_B_StatusGet()
- * - @ref R_SDADC_StatusGet()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- * @param[out] p_status Pointer to store current status in
- */
- fsp_err_t (* scanStatusGet)(adc_ctrl_t * const p_ctrl, adc_status_t * p_status);
-
- /** Read ADC conversion result.
- * @par Implemented as
- * - @ref R_ADC_Read()
- * - @ref R_ADC_B_Read()
- * - @ref R_SDADC_Read()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t)
- * @param[in] p_data Pointer to variable to load value into.
- */
- fsp_err_t (* read)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data);
-
- /** Read ADC conversion result into a 32-bit word.
- * @par Implemented as
- * - @ref R_ADC_Read32()
- * - @ref R_ADC_B_Read32()
- * - @ref R_SDADC_Read32()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t)
- * @param[in] p_data Pointer to variable to load value into.
- */
- fsp_err_t (* read32)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data);
-
- /** Calibrate ADC or associated PGA (programmable gain amplifier). The driver may require implementation specific
- * arguments to the p_extend input. Not supported for all implementations. See implementation for details.
- * @par Implemented as
- * - @ref R_ADC_Calibrate()
- * - @ref R_ADC_B_Calibrate()
- * - @ref R_SDADC_Calibrate()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- * @param[in] p_extend Pointer to implementation specific arguments
- */
- fsp_err_t (* calibrate)(adc_ctrl_t * const p_ctrl, void const * p_extend);
-
- /** Set offset for input PGA configured for differential input. Not supported for all implementations.
- * See implementation for details.
- * @par Implemented as
- * - @ref R_SDADC_OffsetSet()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- * @param[in] reg_id ADC channel to read (see enumeration adc_channel_t)
- * @param[in] offset See implementation for details.
- */
- fsp_err_t (* offsetSet)(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t const offset);
-
- /**
- * Specify callback function and optional context pointer and working memory pointer.
- * @par Implemented as
- * - @ref R_ADC_CallbackSet()
- * - @ref R_ADC_B_CallbackSet()
- *
- * @param[in] p_ctrl Pointer to the ADC control block.
- * @param[in] p_callback Callback function
- * @param[in] p_context Pointer to send to callback function
- * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
- * Callback arguments allocated here are only valid during the callback.
- */
- fsp_err_t (* callbackSet)(adc_ctrl_t * const p_api_ctrl, void (* p_callback)(adc_callback_args_t *),
- void const * const p_context, adc_callback_args_t * const p_callback_memory);
-
- /** Close the specified ADC unit by ending any scan in progress, disabling interrupts, and removing power to the
- * specified A/D unit.
- * @par Implemented as
- * - @ref R_ADC_Close()
- * - @ref R_ADC_B_Close()
- * - @ref R_SDADC_Close()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- */
- fsp_err_t (* close)(adc_ctrl_t * const p_ctrl);
-
- /** Return the ADC data register address of the first (lowest number) channel and the total number of bytes
- * to be read in order for the DTC/DMAC to read the conversion results of all configured channels.
- * Return the temperature sensor calibration and slope data.
- * @par Implemented as
- * - @ref R_ADC_InfoGet()
- * - @ref R_ADC_B_InfoGet()
- * - @ref R_SDADC_InfoGet()
- *
- * @param[in] p_ctrl Pointer to control handle structure
- * @param[out] p_adc_info Pointer to ADC information structure
- */
- fsp_err_t (* infoGet)(adc_ctrl_t * const p_ctrl, adc_info_t * const p_adc_info);
-} adc_api_t;
-
-/** This structure encompasses everything that is needed to use an instance of this interface. */
-typedef struct st_adc_instance
-{
- adc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
- adc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
- void const * p_channel_cfg; ///< Pointer to the channel configuration structure for this instance
- adc_api_t const * p_api; ///< Pointer to the API structure for this instance
-} adc_instance_t;
-
-/*******************************************************************************************************************//**
- * @} (end defgroup ADC_API)
- **********************************************************************************************************************/
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-#endif
diff --git a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_elc_api.h b/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_elc_api.h
deleted file mode 100644
index 89861e49da..0000000000
--- a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_elc_api.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
- * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @ingroup RENESAS_INTERFACES
- * @defgroup ELC_API ELC Interface
- * @brief Interface for the Event Link Controller.
- *
- *
- *
- * @{
- **********************************************************************************************************************/
-
-#ifndef R_ELC_API_H
-#define R_ELC_API_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-
-/* Register definitions, common services and error codes. */
-#include "bsp_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/**********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-#ifndef ELC_PERIPHERAL_NUM
- #define ELC_PERIPHERAL_NUM (23U)
-#endif
-
-/**********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-#ifndef BSP_OVERRIDE_ELC_PERIPHERAL_T
-
-/** Possible peripherals to be linked to event signals (not all available on all MCUs) */
-typedef enum e_elc_peripheral
-{
- ELC_PERIPHERAL_GPT_A = (0),
- ELC_PERIPHERAL_GPT_B = (1),
- ELC_PERIPHERAL_GPT_C = (2),
- ELC_PERIPHERAL_GPT_D = (3),
- ELC_PERIPHERAL_GPT_E = (4),
- ELC_PERIPHERAL_GPT_F = (5),
- ELC_PERIPHERAL_GPT_G = (6),
- ELC_PERIPHERAL_GPT_H = (7),
- ELC_PERIPHERAL_ADC0 = (8),
- ELC_PERIPHERAL_ADC0_B = (9),
- ELC_PERIPHERAL_ADC1 = (10),
- ELC_PERIPHERAL_ADC1_B = (11),
- ELC_PERIPHERAL_DAC0 = (12),
- ELC_PERIPHERAL_DAC1 = (13),
- ELC_PERIPHERAL_IOPORT1 = (14),
- ELC_PERIPHERAL_IOPORT2 = (15),
- ELC_PERIPHERAL_IOPORT3 = (16),
- ELC_PERIPHERAL_IOPORT4 = (17),
- ELC_PERIPHERAL_CTSU = (18),
- ELC_PERIPHERAL_DA8_0 = (19),
- ELC_PERIPHERAL_DA8_1 = (20),
- ELC_PERIPHERAL_SDADC0 = (22),
-} elc_peripheral_t;
-
-#endif
-
-/** ELC control block. Allocate an instance specific control block to pass into the ELC API calls.
- * @par Implemented as
- * - elc_instance_ctrl_t
- */
-typedef void elc_ctrl_t;
-
-/** Main configuration structure for the Event Link Controller */
-typedef struct st_elc_cfg
-{
- elc_event_t const link[ELC_PERIPHERAL_NUM]; ///< Event link register (ELSR) settings
-} elc_cfg_t;
-
-/** Software event number */
-typedef enum e_elc_software_event
-{
- ELC_SOFTWARE_EVENT_0, ///< Software event 0
- ELC_SOFTWARE_EVENT_1, ///< Software event 1
-} elc_software_event_t;
-
-/** ELC driver structure. General ELC functions implemented at the HAL layer follow this API. */
-typedef struct st_elc_api
-{
- /** Initialize all links in the Event Link Controller.
- * @par Implemented as
- * - @ref R_ELC_Open()
- *
- * @param[in] p_ctrl Pointer to control structure.
- * @param[in] p_cfg Pointer to configuration structure.
- **/
- fsp_err_t (* open)(elc_ctrl_t * const p_ctrl, elc_cfg_t const * const p_cfg);
-
- /** Disable all links in the Event Link Controller and close the API.
- * @par Implemented as
- * - @ref R_ELC_Close()
- *
- * @param[in] p_ctrl Pointer to control structure.
- **/
- fsp_err_t (* close)(elc_ctrl_t * const p_ctrl);
-
- /** Generate a software event in the Event Link Controller.
- * @par Implemented as
- * - @ref R_ELC_SoftwareEventGenerate()
- *
- * @param[in] p_ctrl Pointer to control structure.
- * @param[in] eventNum Software event number to be generated.
- **/
- fsp_err_t (* softwareEventGenerate)(elc_ctrl_t * const p_ctrl, elc_software_event_t event_num);
-
- /** Create a single event link.
- * @par Implemented as
- * - @ref R_ELC_LinkSet()
- *
- * @param[in] p_ctrl Pointer to control structure.
- * @param[in] peripheral The peripheral block that will receive the event signal.
- * @param[in] signal The event signal.
- **/
- fsp_err_t (* linkSet)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal);
-
- /** Break an event link.
- * @par Implemented as
- * - @ref R_ELC_LinkBreak()
- *
- * @param[in] p_ctrl Pointer to control structure.
- * @param[in] peripheral The peripheral that should no longer be linked.
- **/
- fsp_err_t (* linkBreak)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral);
-
- /** Enable the operation of the Event Link Controller.
- * @par Implemented as
- * - @ref R_ELC_Enable()
- *
- * @param[in] p_ctrl Pointer to control structure.
- **/
- fsp_err_t (* enable)(elc_ctrl_t * const p_ctrl);
-
- /** Disable the operation of the Event Link Controller.
- * @par Implemented as
- * - @ref R_ELC_Disable()
- *
- * @param[in] p_ctrl Pointer to control structure.
- **/
- fsp_err_t (* disable)(elc_ctrl_t * const p_ctrl);
-} elc_api_t;
-
-/** This structure encompasses everything that is needed to use an instance of this interface. */
-typedef struct st_elc_instance
-{
- elc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
- elc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
- elc_api_t const * p_api; ///< Pointer to the API structure for this instance
-} elc_instance_t;
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif
-
-/*******************************************************************************************************************//**
- * @} (end addtogroup ELC_API)
- **********************************************************************************************************************/
diff --git a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_timer_api.h b/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_timer_api.h
deleted file mode 100644
index 2cbd3b4860..0000000000
--- a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/api/r_timer_api.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
- * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-#ifndef R_TIMER_API_H
-#define R_TIMER_API_H
-
-/*******************************************************************************************************************//**
- * @defgroup TIMER_API Timer Interface
- * @ingroup RENESAS_INTERFACES
- * @brief Interface for timer functions.
- *
- * @section TIMER_API_SUMMARY Summary
- * The general timer interface provides standard timer functionality including periodic mode, one-shot mode, PWM output,
- * and free-running timer mode. After each timer cycle (overflow or underflow), an interrupt can be triggered.
- *
- * If an instance supports output compare mode, it is provided in the extension configuration
- * timer_on__cfg_t defined in r_.h.
- *
- * Implemented by:
- * - @ref GPT
- * - @ref AGT
- *
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-
-/* Includes board and MCU related header files. */
-#include "bsp_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/**********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/* Leading zeroes removed to avoid coding standard violation. */
-
-/**********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-/** Events that can trigger a callback function */
-typedef enum e_timer_event
-{
- TIMER_EVENT_CYCLE_END, ///< Requested timer delay has expired or timer has wrapped around
- TIMER_EVENT_CREST = TIMER_EVENT_CYCLE_END, ///< Timer crest event (counter is at a maximum, triangle-wave PWM only)
- TIMER_EVENT_CAPTURE_A, ///< A capture has occurred on signal A
- TIMER_EVENT_CAPTURE_B, ///< A capture has occurred on signal B
- TIMER_EVENT_TROUGH, ///< Timer trough event (counter is 0, triangle-wave PWM only
-} timer_event_t;
-
-/** Timer variant types. */
-typedef enum e_timer_variant
-{
- TIMER_VARIANT_32_BIT, ///< 32-bit timer
- TIMER_VARIANT_16_BIT ///< 16-bit timer
-} timer_variant_t;
-
-/** Callback function parameter data */
-typedef struct st_timer_callback_args
-{
- /** Placeholder for user data. Set in @ref timer_api_t::open function in @ref timer_cfg_t. */
- void const * p_context;
- timer_event_t event; ///< The event can be used to identify what caused the callback.
-
- /** Most recent capture, only valid if event is TIMER_EVENT_CAPTURE_A or TIMER_EVENT_CAPTURE_B. */
- uint32_t capture;
-} timer_callback_args_t;
-
-/** Timer control block. Allocate an instance specific control block to pass into the timer API calls.
- * @par Implemented as
- * - gpt_instance_ctrl_t
- * - agt_instance_ctrl_t
- */
-typedef void timer_ctrl_t;
-
-/** Possible status values returned by @ref timer_api_t::statusGet. */
-typedef enum e_timer_state
-{
- TIMER_STATE_STOPPED = 0, ///< Timer is stopped
- TIMER_STATE_COUNTING = 1, ///< Timer is running
-} timer_state_t;
-
-/** Timer operational modes */
-typedef enum e_timer_mode
-{
- TIMER_MODE_PERIODIC, ///< Timer restarts after period elapses.
- TIMER_MODE_ONE_SHOT, ///< Timer stops after period elapses.
- TIMER_MODE_PWM, ///< Timer generates saw-wave PWM output.
- TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM = 4U, ///< Timer generates symmetric triangle-wave PWM output.
- TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM = 5U, ///< Timer generates asymmetric triangle-wave PWM output.
-
- /**
- * Timer generates Asymmetric Triangle-wave PWM output. In PWM mode 3, the duty cycle does
- * not need to be updated at each tough/crest interrupt. Instead, the trough and crest duty cycle values can be
- * set once and only need to be updated when the application needs to change the duty cycle.
- */
- TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 = 6U,
-} timer_mode_t;
-
-/** Direction of timer count */
-typedef enum e_timer_direction
-{
- TIMER_DIRECTION_DOWN = 0, ///< Timer count goes up
- TIMER_DIRECTION_UP = 1 ///< Timer count goes down
-} timer_direction_t;
-
-/** PCLK divisors */
-typedef enum e_timer_source_div
-{
- TIMER_SOURCE_DIV_1 = 0, ///< Timer clock source divided by 1
- TIMER_SOURCE_DIV_2 = 1, ///< Timer clock source divided by 2
- TIMER_SOURCE_DIV_4 = 2, ///< Timer clock source divided by 4
- TIMER_SOURCE_DIV_8 = 3, ///< Timer clock source divided by 8
- TIMER_SOURCE_DIV_16 = 4, ///< Timer clock source divided by 16
- TIMER_SOURCE_DIV_32 = 5, ///< Timer clock source divided by 32
- TIMER_SOURCE_DIV_64 = 6, ///< Timer clock source divided by 64
- TIMER_SOURCE_DIV_128 = 7, ///< Timer clock source divided by 128
- TIMER_SOURCE_DIV_256 = 8, ///< Timer clock source divided by 256
- TIMER_SOURCE_DIV_512 = 9, ///< Timer clock source divided by 512
- TIMER_SOURCE_DIV_1024 = 10, ///< Timer clock source divided by 1024
-} timer_source_div_t;
-
-/** Timer information structure to store various information for a timer resource */
-typedef struct st_timer_info
-{
- timer_direction_t count_direction; ///< Clock counting direction of the timer.
- uint32_t clock_frequency; ///< Clock frequency of the timer counter.
-
- /** Period in raw timer counts.
- * @note For triangle wave PWM modes, the full period is double this value.
- */
- uint32_t period_counts;
-} timer_info_t;
-
-/** Current timer status. */
-typedef struct st_timer_status
-{
- uint32_t counter; ///< Current counter value
- timer_state_t state; ///< Current timer state (running or stopped)
-} timer_status_t;
-
-/** User configuration structure, used in open function */
-typedef struct st_timer_cfg
-{
- timer_mode_t mode; ///< Select enumerated value from @ref timer_mode_t
-
- /* Period in raw timer counts.
- * @note For triangle wave PWM modes, enter the period of half the triangle wave, or half the desired period.
- */
- uint32_t period_counts; ///< Period in raw timer counts
- timer_source_div_t source_div; ///< Source clock divider
- uint32_t duty_cycle_counts; ///< Duty cycle in counts
-
- /** Select a channel corresponding to the channel number of the hardware. */
- uint8_t channel;
- uint8_t cycle_end_ipl; ///< Cycle end interrupt priority
- IRQn_Type cycle_end_irq; ///< Cycle end interrupt
-
- /** Callback provided when a timer ISR occurs. Set to NULL for no CPU interrupt. */
- void (* p_callback)(timer_callback_args_t * p_args);
-
- /** Placeholder for user data. Passed to the user callback in @ref timer_callback_args_t. */
- void const * p_context;
- void const * p_extend; ///< Extension parameter for hardware specific settings.
-} timer_cfg_t;
-
-/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */
-typedef struct st_timer_api
-{
- /** Initial configuration.
- * @par Implemented as
- * - @ref R_GPT_Open()
- * - @ref R_AGT_Open()
- *
- * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
- * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user.
- */
- fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg);
-
- /** Start the counter.
- * @par Implemented as
- * - @ref R_GPT_Start()
- * - @ref R_AGT_Start()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- */
- fsp_err_t (* start)(timer_ctrl_t * const p_ctrl);
-
- /** Stop the counter.
- * @par Implemented as
- * - @ref R_GPT_Stop()
- * - @ref R_AGT_Stop()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- */
- fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl);
-
- /** Reset the counter to the initial value.
- * @par Implemented as
- * - @ref R_GPT_Reset()
- * - @ref R_AGT_Reset()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- */
- fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl);
-
- /** Enables input capture.
- * @par Implemented as
- * - @ref R_GPT_Enable()
- * - @ref R_AGT_Enable()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- */
- fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl);
-
- /** Disables input capture.
- * @par Implemented as
- * - @ref R_GPT_Disable()
- * - @ref R_AGT_Disable()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- */
- fsp_err_t (* disable)(timer_ctrl_t * const p_ctrl);
-
- /** Set the time until the timer expires. See implementation for details of period update timing.
- *
- * @par Implemented as
- * - @ref R_GPT_PeriodSet()
- * - @ref R_AGT_PeriodSet()
- *
- * @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in
- * @ref timer_api_t::open.
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- * @param[in] p_period Time until timer should expire.
- */
- fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period);
-
- /** Sets the number of counts for the pin level to be high. If the timer is counting, the updated duty cycle is
- * reflected after the next timer expiration.
- *
- * @par Implemented as
- * - @ref R_GPT_DutyCycleSet()
- * - @ref R_AGT_DutyCycleSet()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- * @param[in] duty_cycle_counts Time until duty cycle should expire.
- * @param[in] pin Which output pin to update. See implementation for details.
- */
- fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin);
-
- /** Stores timer information in p_info.
- * @par Implemented as
- * - @ref R_GPT_InfoGet()
- * - @ref R_AGT_InfoGet()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- * @param[out] p_info Collection of information for this timer.
- */
- fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info);
-
- /** Get the current counter value and timer state and store it in p_status.
- * @par Implemented as
- * - @ref R_GPT_StatusGet()
- * - @ref R_AGT_StatusGet()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- * @param[out] p_status Current status of this timer.
- */
- fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status);
-
- /** Specify callback function and optional context pointer and working memory pointer.
- * @par Implemented as
- * - @ref R_GPT_CallbackSet()
- * - @ref R_AGT_CallbackSet()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- * @param[in] p_callback Callback function to register
- * @param[in] p_context Pointer to send to callback function
- * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
- * Callback arguments allocated here are only valid during the callback.
- */
- fsp_err_t (* callbackSet)(timer_ctrl_t * const p_api_ctrl, void (* p_callback)(timer_callback_args_t *),
- void const * const p_context, timer_callback_args_t * const p_callback_memory);
-
- /** Allows driver to be reconfigured and may reduce power consumption.
- * @par Implemented as
- * - @ref R_GPT_Close()
- * - @ref R_AGT_Close()
- *
- * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer.
- */
- fsp_err_t (* close)(timer_ctrl_t * const p_ctrl);
-} timer_api_t;
-
-/** This structure encompasses everything that is needed to use an instance of this interface. */
-typedef struct st_timer_instance
-{
- timer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
- timer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
- timer_api_t const * p_api; ///< Pointer to the API structure for this instance
-} timer_instance_t;
-
-/*******************************************************************************************************************//**
- * @} (end defgroup TIMER_API)
- **********************************************************************************************************************/
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif
diff --git a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_adc.h b/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_adc.h
deleted file mode 100644
index 7b56107cee..0000000000
--- a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_adc.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
- * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-#ifndef R_ADC_H
-#define R_ADC_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include
-
-/* Fixed width integer support. */
-#include
-
-/* bool support */
-#include
-#include "bsp_api.h"
-#include "r_adc_cfg.h"
-#include "r_adc_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/*******************************************************************************************************************//**
- * @addtogroup ADC
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/* Typical values that can be used to modify the sample states.
- * The minimum sample state count value is either 6 or 7 depending on the clock ratios.
- * It is fixed to 7 based on the fact that at the lowest ADC conversion clock supported (1 MHz)
- * this extra state will lead to at worst a "1 microsecond" increase in conversion time.
- * At 60 MHz the extra sample state will add 16.7 ns to the conversion time.
- */
-#define ADC_SAMPLE_STATE_COUNT_MIN (7U)
-#define ADC_SAMPLE_STATE_COUNT_MAX (255U)
-
-/* Typical values that can be used for the sample and hold counts for the channels 0-2*/
-/* Minimum sample and hold states */
-#define ADC_SAMPLE_STATE_HOLD_COUNT_MIN (4U)
-
-/* Default sample and hold states */
-#define ADC_SAMPLE_STATE_HOLD_COUNT_DEFAULT (24U)
-
-/** For ADC Scan configuration adc_channel_cfg_t::scan_mask, adc_channel_cfg_t::scan_mask_group_b,
- * adc_channel_cfg_t::add_mask and adc_channel_cfg_t::sample_hold_mask.
- * Use bitwise OR to combine these masks for desired channels and sensors. */
-typedef enum e_adc_mask
-{
- ADC_MASK_OFF = (0U), ///< No channels selected
- ADC_MASK_CHANNEL_0 = (1U << 0U), ///< Channel 0 mask
- ADC_MASK_CHANNEL_1 = (1U << 1U), ///< Channel 1 mask
- ADC_MASK_CHANNEL_2 = (1U << 2U), ///< Channel 2 mask
- ADC_MASK_CHANNEL_3 = (1U << 3U), ///< Channel 3 mask
- ADC_MASK_CHANNEL_4 = (1U << 4U), ///< Channel 4 mask
- ADC_MASK_CHANNEL_5 = (1U << 5U), ///< Channel 5 mask
- ADC_MASK_CHANNEL_6 = (1U << 6U), ///< Channel 6 mask
- ADC_MASK_CHANNEL_7 = (1U << 7U), ///< Channel 7 mask
- ADC_MASK_CHANNEL_8 = (1U << 8U), ///< Channel 8 mask
- ADC_MASK_CHANNEL_9 = (1U << 9U), ///< Channel 9 mask
- ADC_MASK_CHANNEL_10 = (1U << 10U), ///< Channel 10 mask
- ADC_MASK_CHANNEL_11 = (1U << 11U), ///< Channel 11 mask
- ADC_MASK_CHANNEL_12 = (1U << 12U), ///< Channel 12 mask
- ADC_MASK_CHANNEL_13 = (1U << 13U), ///< Channel 13 mask
- ADC_MASK_CHANNEL_14 = (1U << 14U), ///< Channel 14 mask
- ADC_MASK_CHANNEL_15 = (1U << 15U), ///< Channel 15 mask
- ADC_MASK_CHANNEL_16 = (1U << 16U), ///< Channel 16 mask
- ADC_MASK_CHANNEL_17 = (1U << 17U), ///< Channel 17 mask
- ADC_MASK_CHANNEL_18 = (1U << 18U), ///< Channel 18 mask
- ADC_MASK_CHANNEL_19 = (1U << 19U), ///< Channel 19 mask
- ADC_MASK_CHANNEL_20 = (1U << 20U), ///< Channel 20 mask
- ADC_MASK_CHANNEL_21 = (1U << 21U), ///< Channel 21 mask
- ADC_MASK_CHANNEL_22 = (1U << 22U), ///< Channel 22 mask
- ADC_MASK_CHANNEL_23 = (1U << 23U), ///< Channel 23 mask
- ADC_MASK_CHANNEL_24 = (1U << 24U), ///< Channel 24 mask
- ADC_MASK_CHANNEL_25 = (1U << 25U), ///< Channel 25 mask
- ADC_MASK_CHANNEL_26 = (1U << 26U), ///< Channel 26 mask
- ADC_MASK_CHANNEL_27 = (1U << 27U), ///< Channel 27 mask
- ADC_MASK_TEMPERATURE = (1U << 28UL), ///< Temperature sensor channel mask
- ADC_MASK_VOLT = (1U << 29UL), ///< Voltage reference channel mask
- ADC_MASK_SENSORS = (ADC_MASK_TEMPERATURE | ADC_MASK_VOLT), ///< All sensor channel mask
-} adc_mask_t;
-
-/** ADC data sample addition and averaging options */
-typedef enum e_adc_add
-{
- ADC_ADD_OFF = 0, ///< Addition turned off for channels/sensors
- ADC_ADD_TWO = 1, ///< Add two samples
- ADC_ADD_THREE = 2, ///< Add three samples
- ADC_ADD_FOUR = 3, ///< Add four samples
- ADC_ADD_SIXTEEN = 5, ///< Add sixteen samples
- ADC_ADD_AVERAGE_TWO = 0x81, ///< Average two samples
- ADC_ADD_AVERAGE_FOUR = 0x83, ///< Average four samples
- ADC_ADD_AVERAGE_EIGHT = 0x84, ///< Average eight samples
- ADC_ADD_AVERAGE_SIXTEEN = 0x85, ///< Add sixteen samples
-} adc_add_t;
-
-/** ADC clear after read definitions */
-typedef enum e_adc_clear
-{
- ADC_CLEAR_AFTER_READ_OFF = 0, ///< Clear after read off
- ADC_CLEAR_AFTER_READ_ON = 1 ///< Clear after read on
-} adc_clear_t;
-
-/* VREF configuration options, not all options are available on all MCUs. If the MCU does not have VREFAMPCNT or
- * ADHVREFCNT. */
-typedef enum e_adc_vref_control
-{
- /* Available selections on MCUs with VREFAMPCNT.
- * Reference Table 32.12 "VREFADC output voltage control list" in the RA2A1 manual R01UH0888EJ0100.*/
-
- ADC_VREF_CONTROL_VREFH = 0, ///< VREFAMPCNT reset value. VREFADC Output voltage is Hi-Z
- ADC_VREF_CONTROL_1_5V_OUTPUT = 25, ///< BGR turn ON. VREFADC Output voltage is 1.5 V
- ADC_VREF_CONTROL_2_0V_OUTPUT = 29, ///< BGR turn ON. VREFADC Output voltage is 2.0 V
- ADC_VREF_CONTROL_2_5V_OUTPUT = 31, ///< BGR turn ON. VREFADC Output voltage is 2.5 V
-
- /* Available selections on MCUs with ADHVREFCNT.
- * Reference Section 35.2.31 "A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT)"
- * in the RA4M1 manual R01UH0887EJ0100.*/
-
- ADC_VREF_CONTROL_AVCC0_AVSS0 = 0x0, ///< High potential is AVCC0, low potential is AVSS0
- ADC_VREF_CONTROL_VREFH0_AVSS0 = 0x1, ///< High potential is VREFH0, low potential is AVSS0
-
- /** High potential is internal reference voltage, low potential is AVSS0. When the high potential is set to the
- * internal reference voltage, wait 5 us after R_ADC_Open() to start an ADC measurement. */
- ADC_VREF_CONTROL_IVREF_AVSS0 = 0x2,
- ADC_VREF_CONTROL_AVCC0_VREFL0 = 0x10, ///< High potential is AVCC0, low potential is VREFL0
- ADC_VREF_CONTROL_VREFH0_VREFL0 = 0x11, ///< High potential is VREFH0, low potential is VREFL0
-
- /** High potential is internal reference voltage, low potential is VREFL0. When the high potential is set to the
- * internal reference voltage, wait 5 us after R_ADC_Open() to start an ADC measurement. */
- ADC_VREF_CONTROL_IVREF_VREFL0 = 0x12,
-} adc_vref_control_t;
-
-/** ADC sample state registers */
-typedef enum e_adc_sample_state_reg
-{
- ADC_SAMPLE_STATE_CHANNEL_0 = 0, ///< Sample state register channel 0
- ADC_SAMPLE_STATE_CHANNEL_1, ///< Sample state register channel 1
- ADC_SAMPLE_STATE_CHANNEL_2, ///< Sample state register channel 2
- ADC_SAMPLE_STATE_CHANNEL_3, ///< Sample state register channel 3
- ADC_SAMPLE_STATE_CHANNEL_4, ///< Sample state register channel 4
- ADC_SAMPLE_STATE_CHANNEL_5, ///< Sample state register channel 5
- ADC_SAMPLE_STATE_CHANNEL_6, ///< Sample state register channel 6
- ADC_SAMPLE_STATE_CHANNEL_7, ///< Sample state register channel 7
- ADC_SAMPLE_STATE_CHANNEL_8, ///< Sample state register channel 8
- ADC_SAMPLE_STATE_CHANNEL_9, ///< Sample state register channel 9
- ADC_SAMPLE_STATE_CHANNEL_10, ///< Sample state register channel 10
- ADC_SAMPLE_STATE_CHANNEL_11, ///< Sample state register channel 11
- ADC_SAMPLE_STATE_CHANNEL_12, ///< Sample state register channel 12
- ADC_SAMPLE_STATE_CHANNEL_13, ///< Sample state register channel 13
- ADC_SAMPLE_STATE_CHANNEL_14, ///< Sample state register channel 14
- ADC_SAMPLE_STATE_CHANNEL_15, ///< Sample state register channel 15
- ADC_SAMPLE_STATE_CHANNEL_16_TO_31 = -3, ///< Sample state register channel 16 to 31
-} adc_sample_state_reg_t;
-
-/** ADC comparison settings */
-typedef enum e_adc_compare_cfg
-{
- ADC_COMPARE_CFG_EVENT_OUTPUT_OR = 0,
- ADC_COMPARE_CFG_EVENT_OUTPUT_XOR = 1,
- ADC_COMPARE_CFG_EVENT_OUTPUT_AND = 2,
- ADC_COMPARE_CFG_A_ENABLE = R_ADC0_ADCMPCR_CMPAE_Msk | R_ADC0_ADCMPCR_CMPAIE_Msk,
- ADC_COMPARE_CFG_B_ENABLE = R_ADC0_ADCMPCR_CMPBE_Msk | R_ADC0_ADCMPCR_CMPBIE_Msk,
- ADC_COMPARE_CFG_WINDOW_ENABLE = R_ADC0_ADCMPCR_WCMPE_Msk,
-} adc_compare_cfg_t;
-
-/** ADC Window B channel */
-typedef enum e_adc_window_b_channel
-{
- ADC_WINDOW_B_CHANNEL_0 = 0,
- ADC_WINDOW_B_CHANNEL_1,
- ADC_WINDOW_B_CHANNEL_2,
- ADC_WINDOW_B_CHANNEL_3,
- ADC_WINDOW_B_CHANNEL_4,
- ADC_WINDOW_B_CHANNEL_5,
- ADC_WINDOW_B_CHANNEL_6,
- ADC_WINDOW_B_CHANNEL_7,
- ADC_WINDOW_B_CHANNEL_8,
- ADC_WINDOW_B_CHANNEL_9,
- ADC_WINDOW_B_CHANNEL_10,
- ADC_WINDOW_B_CHANNEL_11,
- ADC_WINDOW_B_CHANNEL_12,
- ADC_WINDOW_B_CHANNEL_13,
- ADC_WINDOW_B_CHANNEL_14,
- ADC_WINDOW_B_CHANNEL_15,
- ADC_WINDOW_B_CHANNEL_16,
- ADC_WINDOW_B_CHANNEL_17,
- ADC_WINDOW_B_CHANNEL_18,
- ADC_WINDOW_B_CHANNEL_19,
- ADC_WINDOW_B_CHANNEL_20,
- ADC_WINDOW_B_CHANNEL_21,
- ADC_WINDOW_B_CHANNEL_22,
- ADC_WINDOW_B_CHANNEL_23,
- ADC_WINDOW_B_CHANNEL_24,
- ADC_WINDOW_B_CHANNEL_25,
- ADC_WINDOW_B_CHANNEL_26,
- ADC_WINDOW_B_CHANNEL_27,
- ADC_WINDOW_B_CHANNEL_TEMPERATURE = 32,
- ADC_WINDOW_B_CHANNEL_VOLT = 33,
-} adc_window_b_channel_t;
-
-/** ADC Window B comparison mode */
-typedef enum e_adc_window_b_mode
-{
- ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE = 0,
- ADC_WINDOW_B_MODE_GREATER_THAN_OR_INSIDE = R_ADC0_ADCMPBNSR_CMPLB_Msk,
-} adc_window_b_mode_t;
-
-/** ADC action for group A interrupts group B scan.
- * This enumeration is used to specify the priority between Group A and B in group mode. */
-typedef enum e_adc_group_a
-{
- ADC_GROUP_A_PRIORITY_OFF = 0, ///< Group A ignored and does not interrupt ongoing group B scan
- ADC_GROUP_A_GROUP_B_WAIT_FOR_TRIGGER = 1, ///< Group A interrupts Group B(single scan) which restarts at next Group B trigger
- ADC_GROUP_A_GROUP_B_RESTART_SCAN = 3, ///< Group A interrupts Group B(single scan) which restarts immediately after Group A scan is complete
- ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN = 0x8001, ///< Group A interrupts Group B(continuous scan) which continues scanning without a new Group B trigger
-} adc_group_a_t;
-
-/** ADC double-trigger mode definitions */
-typedef enum e_adc_double_trigger
-{
- ADC_DOUBLE_TRIGGER_DISABLED = 0, ///< Double-triggering disabled
- ADC_DOUBLE_TRIGGER_ENABLED = 1, ///< Double-triggering enabled
- ADC_DOUBLE_TRIGGER_ENABLED_EXTENDED = 2, ///< Double-triggering enabled on both ADC ELC events
-} adc_double_trigger_t;
-
-/** ADC sample state configuration */
-typedef struct st_adc_sample_state
-{
- adc_sample_state_reg_t reg_id; ///< Sample state register ID
- uint8_t num_states; ///< Number of sampling states for conversion. Ch16-20/21 use the same value.
-} adc_sample_state_t;
-
-/** ADC Window Compare configuration */
-typedef struct st_adc_window_cfg
-{
- uint32_t compare_mask; ///< Channel mask to compare with Window A
- uint32_t compare_mode_mask; ///< Per-channel condition mask for Window A
- adc_compare_cfg_t compare_cfg; ///< Window Compare configuration
- uint16_t compare_ref_low; ///< Window A lower reference value
- uint16_t compare_ref_high; ///< Window A upper reference value
- uint16_t compare_b_ref_low; ///< Window B lower reference value
- uint16_t compare_b_ref_high; ///< Window A upper reference value
- adc_window_b_channel_t compare_b_channel; ///< Window B channel
- adc_window_b_mode_t compare_b_mode; ///< Window B condition setting
-} adc_window_cfg_t;
-
-/** Extended configuration structure for ADC. */
-typedef struct st_adc_extended_cfg
-{
- adc_add_t add_average_count; ///< Add or average samples
- adc_clear_t clearing; ///< Clear after read
- adc_trigger_t trigger_group_b; ///< Group B trigger source; valid only for group mode
- adc_double_trigger_t double_trigger_mode; ///< Double-trigger mode setting
- adc_vref_control_t adc_vref_control; ///< VREFADC output voltage control
- uint8_t enable_adbuf; ///< Enable ADC Ring Buffer, Valid only to use along with DMAC transfer
- IRQn_Type window_a_irq; ///< IRQ number for Window Compare A interrupts
- IRQn_Type window_b_irq; ///< IRQ number for Window Compare B interrupts
- uint8_t window_a_ipl; ///< Priority for Window Compare A interrupts
- uint8_t window_b_ipl; ///< Priority for Window Compare B interrupts
-} adc_extended_cfg_t;
-
-/** ADC channel(s) configuration */
-typedef struct st_adc_channel_cfg
-{
- uint32_t scan_mask; ///< Channels/bits: bit 0 is ch0; bit 15 is ch15.
- uint32_t scan_mask_group_b; ///< Valid for group modes.
- uint32_t add_mask; ///< Valid if add enabled in Open().
- adc_window_cfg_t * p_window_cfg; ///< Pointer to Window Compare configuration
- adc_group_a_t priority_group_a; ///< Valid for group modes.
- uint8_t sample_hold_mask; ///< Channels/bits 0-2.
- uint8_t sample_hold_states; ///< Number of states to be used for sample and hold. Affects channels 0-2.
-} adc_channel_cfg_t;
-
-/* Sample and hold Channel mask. Sample and hold is only available for channel 0,1,2*/
-#define ADC_SAMPLE_HOLD_CHANNELS (0x07U)
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-/** ADC instance control block. DO NOT INITIALIZE. Initialized in @ref adc_api_t::open(). */
-typedef struct
-{
- R_ADC0_Type * p_reg; // Base register for this unit
- adc_cfg_t const * p_cfg;
- uint32_t opened; // Boolean to verify that the Unit has been initialized
- uint32_t initialized; // Initialized status of ADC
- uint32_t scan_mask; // Scan mask used for Normal scan
- uint16_t scan_start_adcsr;
-
- void (* p_callback)(adc_callback_args_t *); // Pointer to callback that is called when an adc_event_t occurs.
- adc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
-
- /* Pointer to context to be passed into callback function */
- void const * p_context;
-} adc_instance_ctrl_t;
-
-/**********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/** @cond INC_HEADER_DEFS_SEC */
-/** Interface Structure for user access */
-extern const adc_api_t g_adc_on_adc;
-
-/** @endcond */
-
-/***********************************************************************************************************************
- * Public APIs
- **********************************************************************************************************************/
-fsp_err_t R_ADC_Open(adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg);
-fsp_err_t R_ADC_ScanCfg(adc_ctrl_t * p_ctrl, void const * const p_channel_cfg);
-fsp_err_t R_ADC_InfoGet(adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info);
-fsp_err_t R_ADC_ScanStart(adc_ctrl_t * p_ctrl);
-fsp_err_t R_ADC_ScanGroupStart(adc_ctrl_t * p_ctrl, adc_group_mask_t group_id);
-fsp_err_t R_ADC_ScanStop(adc_ctrl_t * p_ctrl);
-fsp_err_t R_ADC_StatusGet(adc_ctrl_t * p_ctrl, adc_status_t * p_status);
-fsp_err_t R_ADC_Read(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data);
-fsp_err_t R_ADC_Read32(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data);
-fsp_err_t R_ADC_SampleStateCountSet(adc_ctrl_t * p_ctrl, adc_sample_state_t * p_sample);
-fsp_err_t R_ADC_Close(adc_ctrl_t * p_ctrl);
-fsp_err_t R_ADC_OffsetSet(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset);
-fsp_err_t R_ADC_Calibrate(adc_ctrl_t * const p_ctrl, void const * p_extend);
-fsp_err_t R_ADC_CallbackSet(adc_ctrl_t * const p_api_ctrl,
- void ( * p_callback)(adc_callback_args_t *),
- void const * const p_context,
- adc_callback_args_t * const p_callback_memory);
-
-/*******************************************************************************************************************//**
- * @} (end defgroup ADC)
- **********************************************************************************************************************/
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif
diff --git a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_glcdc.h b/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_glcdc.h
deleted file mode 100644
index eb58dd547a..0000000000
--- a/bsp/renesas/ra6m3-hmi-board/ra/fsp/inc/instances/r_glcdc.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
- * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * @addtogroup GLCDC
- * @{
- **********************************************************************************************************************/
-
-#ifndef R_GLCDC_H
-#define R_GLCDC_H
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "bsp_api.h"
-#include "r_display_api.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-/** Display control block. DO NOT INITIALIZE. */
-typedef struct st_glcdc_instance_ctrl
-{
- display_state_t state; // Status of GLCDC module
-
- /* Parameters to Event processing for display devices */
- void (* p_callback)(display_callback_args_t * p_args); // Pointer to callback function
- void const * p_context; // Pointer to the higher level device context
- const display_cfg_t * p_cfg; // Pointer to initial configurations
-} glcdc_instance_ctrl_t;
-
-/** Clock source select */
-typedef enum e_glcdc_clk_src
-{
- GLCDC_CLK_SRC_INTERNAL, ///< Internal
- GLCDC_CLK_SRC_EXTERNAL, ///< External
-} glcdc_clk_src_t;
-
-/** Clock frequency division ratio */
-typedef enum e_glcdc_panel_clk_div
-{
- GLCDC_PANEL_CLK_DIVISOR_1 = 1, ///< Division Ratio 1/1
- GLCDC_PANEL_CLK_DIVISOR_2 = 2, ///< Division Ratio 1/2
- GLCDC_PANEL_CLK_DIVISOR_3 = 3, ///< Division Ratio 1/3
- GLCDC_PANEL_CLK_DIVISOR_4 = 4, ///< Division Ratio 1/4
- GLCDC_PANEL_CLK_DIVISOR_5 = 5, ///< Division Ratio 1/5
- GLCDC_PANEL_CLK_DIVISOR_6 = 6, ///< Division Ratio 1/6
- GLCDC_PANEL_CLK_DIVISOR_7 = 7, ///< Division Ratio 1/7
- GLCDC_PANEL_CLK_DIVISOR_8 = 8, ///< Division Ratio 1/8
- GLCDC_PANEL_CLK_DIVISOR_9 = 9, ///< Division Ratio 1/9
- GLCDC_PANEL_CLK_DIVISOR_12 = 12, ///< Division Ratio 1/12
- GLCDC_PANEL_CLK_DIVISOR_16 = 16, ///< Division Ratio 1/16
- GLCDC_PANEL_CLK_DIVISOR_24 = 24, ///< Division Ratio 1/24
- GLCDC_PANEL_CLK_DIVISOR_32 = 32, ///< Division Ratio 1/32
-} glcdc_panel_clk_div_t;
-
-/** LCD TCON output pin select */
-typedef enum e_glcdc_tcon_pin
-{
- GLCDC_TCON_PIN_NONE = -1, ///< No output
- GLCDC_TCON_PIN_0, ///< LCD_TCON0
- GLCDC_TCON_PIN_1, ///< LCD_TCON1
- GLCDC_TCON_PIN_2, ///< LCD_TCON2
- GLCDC_TCON_PIN_3, ///< LCD_TCON3
-} glcdc_tcon_pin_t;
-
-/** Bus Arbitration setting */
-typedef enum e_glcdc_bus_arbitraion
-{
- GLCDC_BUS_ARBITRATION_ROUNDROBIN, ///< Round robin
- GLCDC_BUS_ARBITRATION_FIX_PRIORITY ///< Fixed
-} glcdc_bus_arbitration_t;
-
-/** Correction circuit sequence control */
-typedef enum e_glcdc_correction_proc_order
-{
- GLCDC_CORRECTION_PROC_ORDER_BRIGHTNESS_CONTRAST2GAMMA, ///< Brightness -> contrast -> gamma correction
- GLCDC_CORRECTION_PROC_ORDER_GAMMA2BRIGHTNESS_CONTRAST ///< Gamma correction -> brightness -> contrast
-} glcdc_correction_proc_order_t;
-
-/** Timing signals for driving the LCD panel */
-typedef enum e_glcdc_tcon_signal_select
-{
- GLCDC_TCON_SIGNAL_SELECT_STVA_VS = 0, ///< STVA/VS
- GLCDC_TCON_SIGNAL_SELECT_STVB_VE = 1, ///< STVB/VE
- GLCDC_TCON_SIGNAL_SELECT_STHA_HS = 2, ///< STH/SP/HS
- GLCDC_TCON_SIGNAL_SELECT_STHB_HE = 3, ///< STB/LP/HE
- GLCDC_TCON_SIGNAL_SELECT_DE = 7 ///< DE
-} glcdc_tcon_signal_select_t;
-
-/** Clock phase adjustment for serial RGB output */
-typedef enum e_glcdc_clut_plane
-{
- GLCDC_CLUT_PLANE_0 = 0, ///< GLCDC CLUT plane 0
- GLCDC_CLUT_PLANE_1 = 1, ///< GLCDC CLUT plane 1
-} glcdc_clut_plane_t;
-
-/** Dithering mode */
-typedef enum e_glcdc_dithering_mode
-{
- GLCDC_DITHERING_MODE_TRUNCATE = 0, ///< No dithering (truncate)
- GLCDC_DITHERING_MODE_ROUND_OFF = 1, ///< Dithering with round off
- GLCDC_DITHERING_MODE_2X2PATTERN = 2, ///< Dithering with 2x2 pattern
- GLCDC_DITHERING_MODE_SETTING_MAX
-} glcdc_dithering_mode_t;
-
-/** Dithering mode */
-typedef enum e_glcdc_dithering_pattern
-{
- GLCDC_DITHERING_PATTERN_00 = 0, ///< 2x2 pattern '00'
- GLCDC_DITHERING_PATTERN_01 = 1, ///< 2x2 pattern '01'
- GLCDC_DITHERING_PATTERN_10 = 2, ///< 2x2 pattern '10'
- GLCDC_DITHERING_PATTERN_11 = 3, ///< 2x2 pattern '11'
-} glcdc_dithering_pattern_t;
-
-/** Output interface format */
-typedef enum e_glcdc_input_interface_format
-{
- GLCDC_INPUT_INTERFACE_FORMAT_RGB565 = 0, ///< Input interface format RGB565
- GLCDC_INPUT_INTERFACE_FORMAT_RGB888 = 1, ///< Input interface format RGB888
- GLCDC_INPUT_INTERFACE_FORMAT_ARGB1555 = 2, ///< Input interface format ARGB1555
- GLCDC_INPUT_INTERFACE_FORMAT_ARGB4444 = 3, ///< Input interface format ARGB4444
- GLCDC_INPUT_INTERFACE_FORMAT_ARGB8888 = 4, ///< Input interface format ARGB8888
- GLCDC_INPUT_INTERFACE_FORMAT_CLUT8 = 5, ///< Input interface format CLUT8
- GLCDC_INPUT_INTERFACE_FORMAT_CLUT4 = 6, ///< Input interface format CLUT4
- GLCDC_INPUT_INTERFACE_FORMAT_CLUT1 = 7, ///< Input interface format CLUT1
-} glcdc_input_interface_format_t;
-
-/** Output interface format */
-typedef enum e_glcdc_output_interface_format
-{
- GLCDC_OUTPUT_INTERFACE_FORMAT_RGB888 = 0, ///< Output interface format RGB888
- GLCDC_OUTPUT_INTERFACE_FORMAT_RGB666 = 1, ///< Output interface format RGB666
- GLCDC_OUTPUT_INTERFACE_FORMAT_RGB565 = 2, ///< Output interface format RGB565
- GLCDC_OUTPUT_INTERFACE_FORMAT_SERIAL_RGB = 3, ///< Output interface format Serial RGB
-} glcdc_output_interface_format_t;
-
-/** Dithering output format */
-typedef enum e_glcdc_dithering_output_format
-{
- GLCDC_DITHERING_OUTPUT_FORMAT_RGB888 = 0, ///< Dithering output format RGB888
- GLCDC_DITHERING_OUTPUT_FORMAT_RGB666 = 1, ///< Dithering output format RGB666
- GLCDC_DITHERING_OUTPUT_FORMAT_RGB565 = 2, ///< Dithering output format RGB565
-} glcdc_dithering_output_format_t;
-
-/** GLCDC hardware specific configuration */
-typedef struct st_glcdc_extended_cfg
-{
- glcdc_tcon_pin_t tcon_hsync; ///< GLCDC TCON output pin select
- glcdc_tcon_pin_t tcon_vsync; ///< GLCDC TCON output pin select
- glcdc_tcon_pin_t tcon_de; ///< GLCDC TCON output pin select
- glcdc_correction_proc_order_t correction_proc_order; ///< Correction control route select
- glcdc_clk_src_t clksrc; ///< Clock Source selection
- glcdc_panel_clk_div_t clock_div_ratio; ///< Clock divide ratio for dot clock
- glcdc_dithering_mode_t dithering_mode; ///< Dithering mode
- glcdc_dithering_pattern_t dithering_pattern_A; ///< Dithering pattern A
- glcdc_dithering_pattern_t dithering_pattern_B; ///< Dithering pattern B
- glcdc_dithering_pattern_t dithering_pattern_C; ///< Dithering pattern C
- glcdc_dithering_pattern_t dithering_pattern_D; ///< Dithering pattern D
-} glcdc_extended_cfg_t;
-
-/* GLCDC hardware specific control block */
-typedef struct st_glcdc_ctrl
-{
- display_coordinate_t back_porch; ///< Zero coordinate for graphics plane(Back porch end)
- uint16_t hsize; ///< Horizontal pixel size in a line
- uint16_t vsize; ///< Vertical pixel size in a frame
- void * p_context; ///< Pointer to the function level device context
- // (e.g. display_ctrl_t type data)
-} glcdc_ctrl_t;
-
-/**********************************************************************************************************************
- * Exported global variables
- **********************************************************************************************************************/
-
-/* @cond INC_HEADER_DEFS_SEC */
-/* Filled in Interface API structure for this Instance. */
-extern const display_api_t g_display_on_glcdc;
-
-/* @endcond */
-
-/**********************************************************************************************************************
- * Public APIs
- **********************************************************************************************************************/
-
-fsp_err_t R_GLCDC_Open(display_ctrl_t * const p_api_ctrl, display_cfg_t const * const p_cfg);
-fsp_err_t R_GLCDC_Close(display_ctrl_t * const p_api_ctrl);
-fsp_err_t R_GLCDC_Start(display_ctrl_t * const p_api_ctrl);
-fsp_err_t R_GLCDC_Stop(display_ctrl_t * const p_api_ctrl);
-fsp_err_t R_GLCDC_LayerChange(display_ctrl_t const * const p_api_ctrl,
- display_runtime_cfg_t const * const p_cfg,
- display_frame_layer_t layer);
-fsp_err_t R_GLCDC_BufferChange(display_ctrl_t const * const p_api_ctrl,
- uint8_t * const framebuffer,
- display_frame_layer_t layer);
-
-#if GLCDC_CFG_COLOR_CORRECTION_ENABLE
-fsp_err_t R_GLCDC_ColorCorrection(display_ctrl_t const * const p_api_ctrl,
- display_correction_t const * const p_correction);
-
-#endif
-
-fsp_err_t R_GLCDC_ClutUpdate(display_ctrl_t const * const p_api_ctrl,
- display_clut_cfg_t const * const p_clut_cfg,
- display_frame_layer_t layer);
-fsp_err_t R_GLCDC_ClutEdit(display_ctrl_t const * const p_api_ctrl,
- display_frame_layer_t layer,
- uint8_t index,
- uint32_t color);
-fsp_err_t R_GLCDC_StatusGet(display_ctrl_t const * const p_api_ctrl, display_status_t * const status);
-
-/*******************************************************************************************************************//**
- * @} (end defgroup GLCDC)
- **********************************************************************************************************************/
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif
diff --git a/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_adc/r_adc.c b/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_adc/r_adc.c
deleted file mode 100644
index f4ad098fc8..0000000000
--- a/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_adc/r_adc.c
+++ /dev/null
@@ -1,1802 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
- * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes , "Project Includes"
- **********************************************************************************************************************/
-
-#include "bsp_api.h"
-
-/* Configuration for this package. */
-#include "r_adc_cfg.h"
-
-/* Private header file for this package. */
-#include "r_adc.h"
-
-/**********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-#define ADC_PRV_USEC_PER_SEC (1000000U)
-#define ADC_PRV_MIN_ADCLK_HZ (1000000U)
-#define ADC_MAX_CALIBRATION_CLOCKS_MILLISECS (780U)
-
-#define ADC_PRV_HZ_PER_KHZ (1000U)
-
-#define ADC_SHIFT_LEFT_ALIGNED_32_BIT (16U)
-
-#define ADC_OPEN (0x52414443U)
-
-#define ADC_ADADC_AVEE_BIT (0x80U)
-
-/* Sample and hold bypass applies to these channels. */
-#define ADC_MASK_SAMPLE_HOLD_BYPASS_CHANNELS (0x7U)
-
-/* Sample and hold bypass starts at bit 8. */
-#define ADC_MASK_SAMPLE_HOLD_BYPASS_SHIFT (8U)
-
-/* Value for ADPGADCR0 to disable PGA */
-#define ADC_ADPGADCR0_DISABLE_PGA (0x0000)
-
-/* Value for ADPGACR to disable PGA */
-#define ADC_ADPGACR_DISABLE_PGA (0x9999)
-
-/* Position of ADCALEXE to start calibration-CALEXE bit */
-#define ADC_ADCALEXE_SET_CALEXE (0x80U)
-
-/* Position of ADCALEXE calibration-CALMON bit */
-#define ADC_ADCALEXE_CALIBRATION_STATUS (0x40U)
-
-/* Value of ADICR with interrupt at end of calibration */
-#define ADC_ADICR_CALIBRATION_INTERRUPT_ENABLED (0x03U)
-
-/* Value of ADICR with no interrupt at end of calibration */
-#define ADC_ADICR_CALIBRATION_INTERRUPT_DISABLED (0x00U)
-
-/* Stabilization time when BGR is enabled */
-#define ADC_BGR_STABILIZATION_DELAY_US (150U)
-
-/* Bit set in adc_vref_control if the internal voltage reference is used for VREFH. */
-#define ADC_PRV_ADHVREFCNT_VREF_INTERNAL_BIT_1 (1U << 1)
-
-#define ADC_PRV_ADCSR_ADST_TRGE_MASK (R_ADC0_ADCSR_ADST_Msk | R_ADC0_ADCSR_TRGE_Msk)
-#define ADC_PRV_ADCSR_CLEAR_ADST_TRGE (~ADC_PRV_ADCSR_ADST_TRGE_MASK)
-
-#define ADC_PRV_TSCR_TSN_ENABLE (R_TSN_CTRL_TSCR_TSEN_Msk | R_TSN_CTRL_TSCR_TSOE_Msk)
-
-#define ADC_PRV_ADBUF_ENABLED (1U)
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-/** Defines the registers settings for the ADC synchronous ELC trigger. */
-typedef enum e_adc_elc_trigger
-{
- ADC_ELC_TRIGGER_EXTERNAL = (0x00U),
- ADC_ELC_TRIGGER = (0x09U),
- ADC_ELC_TRIGGER_GROUP_B = (0x0AU),
- ADC_ELC_TRIGGER_BOTH = (0x0BU),
- ADC_ELC_TRIGGER_DISABLED = (0x3FU)
-} adc_elc_trigger_t;
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef void (BSP_CMSE_NONSECURE_CALL * adc_prv_ns_callback)(adc_callback_args_t * p_args);
-#elif defined(__GNUC__)
-typedef BSP_CMSE_NONSECURE_CALL void (*volatile adc_prv_ns_callback)(adc_callback_args_t * p_args);
-#endif
-
-/***********************************************************************************************************************
- * Private global variables and functions
- **********************************************************************************************************************/
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-static fsp_err_t r_adc_open_cfg_check(adc_cfg_t const * const p_cfg);
-static fsp_err_t r_adc_open_cfg_resolution_check(adc_cfg_t const * const p_cfg);
-static fsp_err_t r_adc_sample_state_cfg_check(adc_instance_ctrl_t * p_instance_ctrl, adc_sample_state_t * p_sample);
-
-static fsp_err_t r_adc_scan_cfg_check_sample_hold(adc_instance_ctrl_t * const p_instance_ctrl,
- adc_channel_cfg_t const * const p_channel_cfg);
-
-static fsp_err_t r_adc_scan_cfg_check_sensors(adc_instance_ctrl_t * const p_instance_ctrl,
- adc_channel_cfg_t const * const p_channel_cfg);
-
-#endif
-
-static void r_adc_open_sub(adc_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg);
-
-static void r_adc_sensor_cfg(adc_instance_ctrl_t * const p_instance_ctrl,
- adc_channel_cfg_t const * const p_channel_cfg);
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
-static fsp_err_t r_adc_scan_cfg_check(adc_instance_ctrl_t * const p_instance_ctrl,
- adc_channel_cfg_t const * const p_channel_cfg);
-
-#endif
-
-static void r_adc_scan_cfg(adc_instance_ctrl_t * const p_instance_ctrl,
- adc_channel_cfg_t const * const p_channel_cfg);
-static void r_adc_sensor_sample_state_calculation(uint32_t * const p_sample_states);
-void adc_scan_end_b_isr(void);
-void adc_scan_end_isr(void);
-void adc_window_compare_isr(void);
-static void r_adc_irq_enable(IRQn_Type irq, uint8_t ipl, void * p_context);
-static void r_adc_irq_disable(IRQn_Type irq);
-static int32_t r_adc_lowest_channel_get(uint32_t adc_mask);
-static void r_adc_scan_end_common_isr(adc_event_t event);
-
-/** Look-up table for ADSTRGR values */
-static const uint32_t adc_elc_trigger_lut[] =
-{
- [ADC_DOUBLE_TRIGGER_DISABLED] = (ADC_ELC_TRIGGER << R_ADC0_ADSTRGR_TRSA_Pos) + ADC_ELC_TRIGGER_GROUP_B,
- [ADC_DOUBLE_TRIGGER_ENABLED] = (ADC_ELC_TRIGGER << R_ADC0_ADSTRGR_TRSA_Pos) + ADC_ELC_TRIGGER_GROUP_B,
- [ADC_DOUBLE_TRIGGER_ENABLED_EXTENDED] = (ADC_ELC_TRIGGER_BOTH << R_ADC0_ADSTRGR_TRSA_Pos) +
- ADC_ELC_TRIGGER_DISABLED,
-};
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
-/** Mask of valid channels on this MCU. */
-static const uint32_t g_adc_valid_channels[] =
-{
- BSP_FEATURE_ADC_UNIT_0_CHANNELS,
- #if BSP_FEATURE_ADC_UNIT_1_CHANNELS
- BSP_FEATURE_ADC_UNIT_1_CHANNELS
- #endif
-};
-#endif
-
-/***********************************************************************************************************************
- * Global Variables
- **********************************************************************************************************************/
-
-/** ADC Implementation of ADC. */
-const adc_api_t g_adc_on_adc =
-{
- .open = R_ADC_Open,
- .scanCfg = R_ADC_ScanCfg,
- .infoGet = R_ADC_InfoGet,
- .scanStart = R_ADC_ScanStart,
- .scanGroupStart = R_ADC_ScanGroupStart,
- .scanStop = R_ADC_ScanStop,
- .scanStatusGet = R_ADC_StatusGet,
- .read = R_ADC_Read,
- .read32 = R_ADC_Read32,
- .close = R_ADC_Close,
- .calibrate = R_ADC_Calibrate,
- .offsetSet = R_ADC_OffsetSet,
- .callbackSet = R_ADC_CallbackSet,
-};
-
-/*******************************************************************************************************************//**
- * @addtogroup ADC
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Sets the operational mode, trigger sources, interrupt priority, and configurations for the peripheral as a whole.
- * If interrupt is enabled, the function registers a callback function pointer for notifying the user whenever a scan
- * has completed.
- *
- * @retval FSP_SUCCESS Module is ready for use.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_ALREADY_OPEN The instance control structure has already been opened.
- * @retval FSP_ERR_IRQ_BSP_DISABLED A callback is provided, but the interrupt is not enabled.
- * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested unit does not exist on this MCU.
- * @retval FSP_ERR_INVALID_HW_CONDITION The ADC clock must be at least 1 MHz
- **********************************************************************************************************************/
-fsp_err_t R_ADC_Open (adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg)
-{
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
-
- /* Perform parameter checking */
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
- /* Verify the pointers are valid */
- FSP_ASSERT(NULL != p_instance_ctrl);
-
- /* Verify the configuration parameters are valid */
- fsp_err_t err = r_adc_open_cfg_check(p_cfg);
- FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-
- /* Check for valid argument values for options that are unique to the IP */
- err = r_adc_open_cfg_resolution_check(p_cfg);
- FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-
- /* Verify this unit has not already been initialized */
- FSP_ERROR_RETURN(ADC_OPEN != p_instance_ctrl->opened, FSP_ERR_ALREADY_OPEN);
-
- /* If a callback is used, then make sure an interrupt is enabled */
- adc_extended_cfg_t const * p_extend = (adc_extended_cfg_t const *) p_cfg->p_extend;
- if (NULL != p_cfg->p_callback)
- {
- FSP_ERROR_RETURN((p_cfg->scan_end_irq >= 0) || (p_extend->window_a_irq >= 0) || (p_extend->window_b_irq >= 0),
- FSP_ERR_IRQ_BSP_DISABLED);
-
- /* Group B interrupts are never required since group B can be configured in continuous scan mode when group A
- * has priority over group B. */
- }
-
-#else
- adc_extended_cfg_t const * p_extend = (adc_extended_cfg_t const *) p_cfg->p_extend;
-#endif
-
- /* Save configurations. */
- p_instance_ctrl->p_cfg = p_cfg;
- p_instance_ctrl->p_callback = p_cfg->p_callback;
- p_instance_ctrl->p_context = p_cfg->p_context;
- p_instance_ctrl->p_callback_memory = NULL;
-
- /* Calculate the register base address. */
- uint32_t address_gap = (uint32_t) R_ADC1 - (uint32_t) R_ADC0;
- p_instance_ctrl->p_reg = (R_ADC0_Type *) ((uint32_t) R_ADC0 + (address_gap * p_cfg->unit));
-
- /* Initialize the hardware based on the configuration. */
- r_adc_open_sub(p_instance_ctrl, p_cfg);
-
- /* Enable interrupts */
- r_adc_irq_enable(p_cfg->scan_end_irq, p_cfg->scan_end_ipl, p_instance_ctrl);
- r_adc_irq_enable(p_cfg->scan_end_b_irq, p_cfg->scan_end_b_ipl, p_instance_ctrl);
- r_adc_irq_enable(p_extend->window_a_irq, p_extend->window_a_ipl, p_instance_ctrl);
- r_adc_irq_enable(p_extend->window_b_irq, p_extend->window_b_ipl, p_instance_ctrl);
-
- /* Invalid scan mask (initialized for later). */
- p_instance_ctrl->scan_mask = 0U;
-
- /* Mark driver as opened by initializing it to "RADC" in its ASCII equivalent for this unit. */
- p_instance_ctrl->opened = ADC_OPEN;
-
- /* Return the error code */
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Configures the ADC scan parameters. Channel specific settings are set in this function. Pass a pointer to
- * @ref adc_channel_cfg_t to p_channel_cfg.
- *
- * @note This starts group B scans if adc_channel_cfg_t::priority_group_a is set to ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN.
- *
- * @retval FSP_SUCCESS Channel specific settings applied.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_ScanCfg (adc_ctrl_t * p_ctrl, void const * const p_channel_cfg)
-{
- adc_channel_cfg_t const * p_adc_channel_cfg = (adc_channel_cfg_t const *) p_channel_cfg;
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
- fsp_err_t err = FSP_SUCCESS;
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ASSERT(NULL != p_adc_channel_cfg);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN);
-
- err = r_adc_scan_cfg_check(p_instance_ctrl, p_adc_channel_cfg);
- FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-#endif
-
- /* Configure the hardware based on the configuration */
- r_adc_scan_cfg(p_instance_ctrl, p_adc_channel_cfg);
-
- /* Save the scan mask locally; this is required for the infoGet function. */
- p_instance_ctrl->scan_mask = p_adc_channel_cfg->scan_mask;
-
- /* Return the error code */
- return err;
-}
-
-/*******************************************************************************************************************//**
- * Updates the user callback and has option of providing memory for callback structure.
- * Implements adc_api_t::callbackSet
- *
- * @retval FSP_SUCCESS Callback updated successfully.
- * @retval FSP_ERR_ASSERTION A required pointer is NULL.
- * @retval FSP_ERR_NOT_OPEN The control block has not been opened.
- * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_CallbackSet (adc_ctrl_t * const p_api_ctrl,
- void ( * p_callback)(adc_callback_args_t *),
- void const * const p_context,
- adc_callback_args_t * const p_callback_memory)
-{
- adc_instance_ctrl_t * p_ctrl = (adc_instance_ctrl_t *) p_api_ctrl;
-
-#if (ADC_CFG_PARAM_CHECKING_ENABLE)
- FSP_ASSERT(p_ctrl);
- FSP_ASSERT(p_callback);
- FSP_ERROR_RETURN(ADC_OPEN == p_ctrl->opened, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Store callback and context */
-
-#if BSP_TZ_SECURE_BUILD
-
- /* Get security state of p_callback */
- bool callback_is_secure =
- (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE));
-
- #if ADC_CFG_PARAM_CHECKING_ENABLE
-
- /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */
- adc_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory,
- CMSE_AU_NONSECURE);
- FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY);
- #endif
-
- p_ctrl->p_callback = callback_is_secure ? p_callback :
- (void (*)(adc_callback_args_t *))cmse_nsfptr_create(p_callback);
-#else
- p_ctrl->p_callback = p_callback;
-#endif
-
- p_ctrl->p_context = p_context;
- p_ctrl->p_callback_memory = p_callback_memory;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Starts a software scan or enables the hardware trigger for a scan depending on how the triggers were configured in
- * the R_ADC_Open call. If the unit was configured for ELC or external hardware triggering, then this function allows
- * the trigger signal to get to the ADC unit. The function is not able to control the generation of the trigger itself.
- * If the unit was configured for software triggering, then this function starts the software triggered scan.
- *
- * @pre Call R_ADC_ScanCfg after R_ADC_Open before starting a scan.
- *
- * @pre On MCUs that support calibration, call R_ADC_Calibrate and wait for calibration to complete before starting
- * a scan.
- *
- * @retval FSP_SUCCESS Scan started (software trigger) or hardware triggers enabled.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized.
- * @retval FSP_ERR_IN_USE Another scan is still in progress (software trigger).
- **********************************************************************************************************************/
-fsp_err_t R_ADC_ScanStart (adc_ctrl_t * p_ctrl)
-{
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
-
- /* Perform parameter checking */
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
- /* Verify the pointers are valid */
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED);
- if (ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN != p_instance_ctrl->p_reg->ADGSPCR)
- {
- FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->ADCSR_b.ADST, FSP_ERR_IN_USE);
- }
-#endif
-
- /* Enable hardware trigger or start software scan depending on mode. */
- p_instance_ctrl->p_reg->ADCSR = p_instance_ctrl->scan_start_adcsr;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * @ref adc_api_t::scanStart is not supported on the ADCH. Use scanStart instead.
- *
- * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_ScanGroupStart (adc_ctrl_t * p_ctrl, adc_group_mask_t group_id)
-{
- FSP_PARAMETER_NOT_USED(p_ctrl);
- FSP_PARAMETER_NOT_USED(group_id);
-
- /* Return the unsupported error. */
- return FSP_ERR_UNSUPPORTED;
-}
-
-/*******************************************************************************************************************//**
- * Stops the software scan or disables the unit from being triggered by the hardware trigger (ELC or external) based on
- * what type of trigger the unit was configured for in the R_ADC_Open function. Stopping a hardware triggered scan via
- * this function does not abort an ongoing scan, but prevents the next scan from occurring. Stopping a software
- * triggered scan aborts an ongoing scan.
- *
- * @retval FSP_SUCCESS Scan stopped (software trigger) or hardware triggers disabled.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_ScanStop (adc_ctrl_t * p_ctrl)
-{
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
-
- /* Perform parameter checking */
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
- /* Verify the pointers are valid */
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED);
-#endif
-
- /* Disable hardware trigger or stop software scan depending on mode. */
- p_instance_ctrl->p_reg->ADCSR = 0U;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Provides the status of any scan process that was started, including scans started by ELC or external triggers and
- * calibration scans on MCUs that support calibration.
- *
- * @retval FSP_SUCCESS Module status stored in the provided pointer p_status
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_StatusGet (adc_ctrl_t * p_ctrl, adc_status_t * p_status)
-{
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ASSERT(NULL != p_status);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Read the status of the ADST bit. ADST is set when a scan is in progress, including calibration scans. */
- p_status->state = (adc_state_t) p_instance_ctrl->p_reg->ADCSR_b.ADST;
-
- /* Return the error code */
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Reads conversion results from a single channel or sensor.
- *
- * @retval FSP_SUCCESS Data read into provided p_data.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_Read (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data)
-{
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
-
- /* Perform parameter checking. */
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
- /* Verify the pointers are valid */
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ASSERT(NULL != p_data);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED);
-
- /* Verify that the channel is valid for this MCU */
- if ((reg_id >= ADC_CHANNEL_0) && ((uint32_t) reg_id <= 31U))
- {
- uint32_t requested_channel_mask = (1U << (uint32_t) reg_id);
- FSP_ASSERT(0 != (requested_channel_mask & g_adc_valid_channels[p_instance_ctrl->p_cfg->unit]));
- }
- else
- {
- FSP_ASSERT((reg_id == ADC_CHANNEL_TEMPERATURE) || (reg_id == ADC_CHANNEL_VOLT) ||
- (reg_id == ADC_CHANNEL_DUPLEX) || (reg_id == ADC_CHANNEL_DUPLEX_A) ||
- (reg_id == ADC_CHANNEL_DUPLEX_B));
- }
-
- /* Data is not available to be read from ADDRn registers when ADBUF is enabled. Read API cannot be used with ADBUF enabled. */
- adc_extended_cfg_t * p_extend = (adc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
- FSP_ASSERT(1U != p_extend->enable_adbuf);
-#endif
-
- /* Read the data from the requested ADC conversion register and return it */
- *p_data = p_instance_ctrl->p_reg->ADDR[reg_id];
-
- /* Return the error code */
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Reads conversion results from a single channel or sensor register into a 32-bit result.
- *
- * @retval FSP_SUCCESS Data read into provided p_data.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_Read32 (adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data)
-{
- uint16_t result = 0U;
- uint32_t result_32 = 0U;
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_data);
-#endif
-
- fsp_err_t err = R_ADC_Read(p_ctrl, reg_id, &result);
- FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-
- result_32 = result;
-
- /* Left shift the result into the upper 16 bits if the unit is configured for left alignment. */
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
- if (ADC_ALIGNMENT_LEFT == p_instance_ctrl->p_cfg->alignment)
- {
- result_32 <<= ADC_SHIFT_LEFT_ALIGNED_32_BIT;
- }
-
- *p_data = result_32;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Sets the sample state count for individual channels. This only needs to be set for special use cases. Normally, use
- * the default values out of reset.
- *
- * @note The sample states for the temperature and voltage sensor are set in R_ADC_ScanCfg.
- *
- * @retval FSP_SUCCESS Sample state count updated.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_INITIALIZED Unit is not initialized.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_SampleStateCountSet (adc_ctrl_t * p_ctrl, adc_sample_state_t * p_sample)
-{
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
- fsp_err_t err = FSP_SUCCESS;
-
- /* Perform parameter checking */
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
- /* Verify the pointers are valid */
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ASSERT(NULL != p_sample);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->initialized, FSP_ERR_NOT_INITIALIZED);
-
- /* Verify arguments are legal */
- err = r_adc_sample_state_cfg_check(p_instance_ctrl, p_sample);
- if (FSP_SUCCESS != err)
- {
- return err;
- }
-#endif
-
- /* Set the sample state count for the specified register */
- p_instance_ctrl->p_reg->ADSSTR[p_sample->reg_id] = p_sample->num_states;
-
- /* Return the error code */
- return err;
-}
-
-/*******************************************************************************************************************//**
- * Returns the address of the lowest number configured channel and the total number of bytes to be read in order to
- * read the results of the configured channels and return the ELC Event name. If no channels are configured, then a
- * length of 0 is returned.
- *
- * Also provides the temperature sensor slope and the calibration data for the sensor if available on this MCU.
- * Otherwise, invalid calibration data of 0xFFFFFFFF will be returned.
- *
- * @note In group mode, information is returned for group A only. Calculating information for group B is not currently
- * supported.
- *
- * @retval FSP_SUCCESS Information stored in p_adc_info.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_InfoGet (adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info)
-{
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
- fsp_err_t err = FSP_SUCCESS;
- uint32_t adc_mask = 0;
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ASSERT(NULL != p_adc_info);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Retrieve the scan mask of active channels from the control structure */
- adc_mask = p_instance_ctrl->scan_mask;
-
- /* If at least one channel is configured, determine the highest and lowest configured channels. */
- if (adc_mask != 0U)
- {
- /* Determine the lowest channel that is configured. The lowest sensor is the temperature sensor, at -3 from
- * channel 0. To get all channels in register order, shift up by 3, then add in the sensors in the bottom
- * 2 bits. */
- uint32_t adc_mask_in_order = adc_mask & ~(uint32_t) ADC_MASK_SENSORS;
- adc_mask_in_order <<= 3U;
- adc_mask_in_order |= adc_mask >> 28U;
- int32_t lowest_channel = r_adc_lowest_channel_get(adc_mask_in_order);
- p_adc_info->p_address = &p_instance_ctrl->p_reg->ADDR[lowest_channel - 3];
-
- /* Determine the highest channel that is configured. */
- int32_t highest_channel = 31 - __CLZ(adc_mask_in_order);
-
- /* Determine the size of data that must be read to read all the channels between and including the
- * highest and lowest channels.*/
- p_adc_info->length = (uint32_t) ((highest_channel - lowest_channel) + 1);
- }
- else
- {
- /* If no channels are configured, set the return length 0. */
- p_adc_info->length = 0U;
- }
-
- p_adc_info->transfer_size = TRANSFER_SIZE_2_BYTE;
-
-#if BSP_FEATURE_ADC_UNIT_1_CHANNELS
-
- /* Specify the peripheral name in the ELC list */
- p_adc_info->elc_event =
- (elc_event_t) ((uint32_t) ELC_EVENT_ADC0_SCAN_END +
- (p_instance_ctrl->p_cfg->unit *
- ((uint32_t) ELC_EVENT_ADC1_SCAN_END - (uint32_t) ELC_EVENT_ADC0_SCAN_END)));
-#else
- p_adc_info->elc_event = ELC_EVENT_ADC0_SCAN_END;
-#endif
-
- p_adc_info->elc_peripheral = (elc_peripheral_t) (ELC_PERIPHERAL_ADC0 + (2U * p_instance_ctrl->p_cfg->unit));
-
- /* Set Temp Sensor calibration data to invalid value */
- p_adc_info->calibration_data = UINT32_MAX;
-
- /* If calibration register is available, retrieve it from the MCU */
-#if 1U == BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE
- #if 1U == BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE
-
- /* Read into memory. */
- uint32_t data = R_TSN_CAL->TSCDR;
-
- /* Read the temperature calibration data from ROM. */
- p_adc_info->calibration_data = (data & BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK);
- #else
-
- /* Read into memory to prevent compiler warning when performing "|" on volatile register data. */
- uint32_t high = R_TSN->TSCDRH;
- uint32_t low = R_TSN->TSCDRL;
-
- /* Read the calibration data from ROM and shift to fit into result variable. */
- p_adc_info->calibration_data = ((high << 8) | low);
- #endif
-#endif
-
- /* Provide the previously retrieved slope information */
- p_adc_info->slope_microvolts = BSP_FEATURE_ADC_TSN_SLOPE;
-
- return err;
-}
-
-/*******************************************************************************************************************//**
- * This function ends any scan in progress, disables interrupts, and removes power to the A/D peripheral.
- *
- * @retval FSP_SUCCESS Module closed.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_Close (adc_ctrl_t * p_ctrl)
-{
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Mark driver as closed */
- p_instance_ctrl->opened = 0U;
- p_instance_ctrl->initialized = 0U;
-
- /* Disable interrupts. */
- adc_extended_cfg_t * p_extend = (adc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
- r_adc_irq_disable(p_instance_ctrl->p_cfg->scan_end_irq);
- r_adc_irq_disable(p_instance_ctrl->p_cfg->scan_end_b_irq);
- r_adc_irq_disable(p_extend->window_a_irq);
- r_adc_irq_disable(p_extend->window_b_irq);
-
- /* Disable triggers. */
- p_instance_ctrl->p_reg->ADSTRGR = 0U;
-
- /* Stop the ADC. */
- p_instance_ctrl->p_reg->ADCSR = 0U;
-
-#if BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG
-
- /* Disable sample and hold before entering module stop state to reduce power consumption (reference section 47.6.8
- * "Available Functions and Register Settings of AN000 to AN002, AN007, AN100 to AN102, and AN107" in the RA6M3
- * manual R01UH0886EJ0100. */
- p_instance_ctrl->p_reg->ADSHCR = 0U;
-#endif
-
-#if BSP_FEATURE_ADC_HAS_VREFAMPCNT
-
- /* If VREFADC is selected as the high-potential reference voltage revert it to reduce power consumption. */
- p_instance_ctrl->p_reg->VREFAMPCNT = 0U;
-#endif
-
- R_BSP_MODULE_STOP(FSP_IP_ADC, p_instance_ctrl->p_cfg->unit);
-
- /* Return the error code */
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Initiates calibration of the ADC on MCUs that require calibration. This function must be called before starting
- * a scan on MCUs that require calibration.
- *
- * Calibration is complete when the callback is called with ADC_EVENT_CALIBRATION_COMPLETE or when R_ADC_StatusGet
- * returns ADC_STATUS_IDLE. Reference Figure 32.35 "Software flow and operation example of calibration operation."
- * in the RA2A1 manual R01UH0888EJ0100.
- *
- * ADC calibration time: 12 PCLKB + 774,930 ADCLK. (Reference Table 32.16 "Required calibration time (shown
- * as the number of ADCLK and PCLKB cycles)" in the RA2A1 manual R01UH0888EJ0100. The lowest supported ADCLK
- * is 1MHz.
- *
- * Calibration will take a minimum of 24 milliseconds at 32 MHz PCLKB and ADCLK. This wait could take up to 780
- * milliseconds for a 1 MHz PCLKD (ADCLK).
- *
- * @param[in] p_ctrl Pointer to the instance control structure
- * @param[in] p_extend Unused argument. Pass NULL.
- *
- * @retval FSP_SUCCESS Calibration successfully initiated.
- * @retval FSP_ERR_INVALID_HW_CONDITION A scan is in progress or hardware triggers are enabled.
- * @retval FSP_ERR_UNSUPPORTED Calibration not supported on this MCU.
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_NOT_OPEN Unit is not open.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_Calibrate (adc_ctrl_t * const p_ctrl, void const * p_extend)
-{
- FSP_PARAMETER_NOT_USED(p_extend);
-
-#if BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) p_ctrl;
- #if ADC_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_ctrl);
- FSP_ERROR_RETURN(ADC_OPEN == p_instance_ctrl->opened, FSP_ERR_NOT_OPEN);
- #endif
-
- /* ADC Calibration can only happen if there is no ongoing scan and if the scan trigger is disabled */
- FSP_ERROR_RETURN(!(p_instance_ctrl->p_reg->ADCSR & ADC_PRV_ADCSR_ADST_TRGE_MASK), FSP_ERR_INVALID_HW_CONDITION);
-
- /* Set the normal mode interrupt request to occur when calibration is complete */
- p_instance_ctrl->p_reg->ADICR = ADC_ADICR_CALIBRATION_INTERRUPT_ENABLED;
-
- /* Initiate calibration */
- p_instance_ctrl->p_reg->ADCALEXE = ADC_ADCALEXE_SET_CALEXE;
-
- return FSP_SUCCESS;
-#else
- FSP_PARAMETER_NOT_USED(p_ctrl);
- FSP_ERROR_LOG(FSP_ERR_UNSUPPORTED);
-
- return FSP_ERR_UNSUPPORTED;
-#endif
-}
-
-/*******************************************************************************************************************//**
- * @ref adc_api_t::offsetSet is not supported on the ADC.
- *
- * @retval FSP_ERR_UNSUPPORTED Function not supported in this implementation.
- **********************************************************************************************************************/
-fsp_err_t R_ADC_OffsetSet (adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset)
-{
- FSP_PARAMETER_NOT_USED(p_ctrl);
- FSP_PARAMETER_NOT_USED(reg_id);
- FSP_PARAMETER_NOT_USED(offset);
-
- /* Return the unsupported error. */
- return FSP_ERR_UNSUPPORTED;
-}
-
-/*******************************************************************************************************************//**
- * @} (end addtogroup ADC)
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Private Functions
- **********************************************************************************************************************/
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
-/*******************************************************************************************************************//**
- * Checks the sample state configuration.
- *
- * @param[in] p_instance_ctrl Pointer to instance control structure
- * @param[in] p_sample Pointer to sample state configuration
- *
- * @retval FSP_SUCCESS No configuration errors detected
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- **********************************************************************************************************************/
-static fsp_err_t r_adc_sample_state_cfg_check (adc_instance_ctrl_t * p_instance_ctrl, adc_sample_state_t * p_sample)
-{
- /* Used to prevent compiler warning */
- FSP_PARAMETER_NOT_USED(p_instance_ctrl);
-
- adc_sample_state_reg_t reg_id = p_sample->reg_id;
-
- /* Verify the requested channel exists on the MCU. */
- if (reg_id >= ADC_SAMPLE_STATE_CHANNEL_0)
- {
- uint32_t requested_channel_mask = (1U << (uint32_t) reg_id);
- FSP_ASSERT(0 != (requested_channel_mask & g_adc_valid_channels[p_instance_ctrl->p_cfg->unit]));
- }
-
- /* Verify the requested sample states is not less than the minimum. */
- FSP_ASSERT(p_sample->num_states >= ADC_SAMPLE_STATE_COUNT_MIN);
-
- return FSP_SUCCESS;
-}
-
-#endif
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
-/*******************************************************************************************************************//**
- * Validates the configuration arguments for illegal combinations or options.
- *
- * @param[in] p_cfg Pointer to configuration structure
- *
- * @retval FSP_SUCCESS No configuration errors detected
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT ADC unit not present on this MCU
- * @retval FSP_ERR_INVALID_HW_CONDITION The ADC clock must be at least 1 MHz
- **********************************************************************************************************************/
-static fsp_err_t r_adc_open_cfg_check (adc_cfg_t const * const p_cfg)
-{
- FSP_ASSERT(NULL != p_cfg);
-
- /* Verify the unit exists on the MCU. */
- FSP_ERROR_RETURN(((1U << p_cfg->unit) & BSP_FEATURE_ADC_VALID_UNIT_MASK), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
-
- /* Verify the ADC clock frequency is at least 1 MHz (reference "Frequency" row of table "60.5 ADC12
- * Characteristics" in the RA6M3 manual R01UH0886EJ0100. The maximum frequency is the maximum frequency supported
- * by the ADCLK, so it is not verified here. */
- uint32_t freq_hz = R_FSP_SystemClockHzGet(BSP_FEATURE_ADC_CLOCK_SOURCE);
- FSP_ERROR_RETURN(freq_hz >= ADC_PRV_MIN_ADCLK_HZ, FSP_ERR_INVALID_HW_CONDITION);
-
- /* Check for valid argument values for addition/averaging. Reference section 47.2.10 "A/D-Converted Value
- * Addition/Average Count Select Register (ADADC)" in the RA6M3 manual R01UH0886EJ0100 and section 32.2.11
- * "A/D-Converted Value Average Count Select Register (ADADC)" in the RA2A1 manual R01UH0888EJ0100. */
- adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_cfg->p_extend;
- if (ADC_ADD_OFF != p_cfg_extend->add_average_count)
- {
- #if BSP_FEATURE_ADC_ADDITION_SUPPORTED
-
- /* The ADC12 and ADC14 do not support averaging 8 or 16 samples. */
- FSP_ASSERT(p_cfg_extend->add_average_count <= ADC_ADD_AVERAGE_FOUR);
- #else
-
- /* The ADC16 supports averaging only, it does not support addition. */
- FSP_ASSERT(0U != (ADC_ADADC_AVEE_BIT & p_cfg_extend->add_average_count));
- #endif
- }
-
- /* If 16 time addition is used only 12 bit accuracy can be selected. Reference Note 1 of section 47.2.10
- * "A/D-Converted Value Addition/Average Count Select Register (ADADC)" in the RA6M3 manual R01UH0886EJ0100. */
- if (ADC_ADD_SIXTEEN == p_cfg_extend->add_average_count)
- {
- FSP_ASSERT(ADC_RESOLUTION_12_BIT == p_cfg->resolution);
- }
-
- /* Only synchronous triggers (ELC) allowed in group scan mode (reference TRSA documentation in section 47.2.12
- * "A/D Conversion Start Trigger Select Register (ADSTRGR)" in the RA6M3 manual R01UH0886EJ0100. */
- if ((ADC_MODE_GROUP_SCAN == p_cfg->mode) || (ADC_DOUBLE_TRIGGER_DISABLED != p_cfg_extend->double_trigger_mode))
- {
- FSP_ASSERT(ADC_TRIGGER_SYNC_ELC == p_cfg->trigger);
-
- if ((ADC_MODE_GROUP_SCAN == p_cfg->mode))
- {
- FSP_ASSERT(ADC_TRIGGER_SYNC_ELC == p_cfg_extend->trigger_group_b);
- }
- }
-
- return FSP_SUCCESS;
-}
-
-#endif
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
-/*******************************************************************************************************************//**
- * This function validates the resolution configuration arguments for illegal combinations or options.
- *
- * @param[in] p_cfg Pointer to configuration structure
- *
- * @retval FSP_SUCCESS No configuration errors detected
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- **********************************************************************************************************************/
-static fsp_err_t r_adc_open_cfg_resolution_check (adc_cfg_t const * const p_cfg)
-{
- #if 12U == BSP_FEATURE_ADC_MAX_RESOLUTION_BITS
- #if BSP_FEATURE_ADC_HAS_ADCER_ADPRC
-
- /* Resolution options for ADC12 (reference section 47.2.11 "A/D Control Extended Register (ADCER)" in the RA6M3
- * manual R01UH0886EJ0100. */
- FSP_ASSERT((ADC_RESOLUTION_12_BIT == p_cfg->resolution) ||
- (ADC_RESOLUTION_10_BIT == p_cfg->resolution) ||
- (ADC_RESOLUTION_8_BIT == p_cfg->resolution));
- #else
- FSP_ASSERT(ADC_RESOLUTION_12_BIT == p_cfg->resolution);
- #endif
- #endif
-
- #if 14U == BSP_FEATURE_ADC_MAX_RESOLUTION_BITS
-
- /* Resolution options for ADC14 (reference section 35.2.11 "A/D Control Extended Register (ADCER)" in the RA4M1
- * manual R01UH0886EJ0100. */
- FSP_ASSERT((ADC_RESOLUTION_12_BIT == p_cfg->resolution) ||
- (ADC_RESOLUTION_14_BIT == p_cfg->resolution));
- #endif
-
- #if 16U == BSP_FEATURE_ADC_MAX_RESOLUTION_BITS
-
- /* ADC16 only offers 16-bit resolution (reference Table 32.1 "ADC16 specifications (1 of 2)" in the RA2A1 manual
- * R01UH0888EJ0100. */
- FSP_ASSERT(ADC_RESOLUTION_16_BIT == p_cfg->resolution);
- #endif
-
- return FSP_SUCCESS;
-}
-
-#endif
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
-/*******************************************************************************************************************//**
- * Checks the sample and hold arguments
- *
- * @param[in] p_instance_ctrl Pointer to instance control block
- * @param[in] p_channel_cfg Pointer to channel configuration
- *
- * @retval FSP_SUCCESS No configuration errors detected
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- **********************************************************************************************************************/
-static fsp_err_t r_adc_scan_cfg_check_sample_hold (adc_instance_ctrl_t * const p_instance_ctrl,
- adc_channel_cfg_t const * const p_channel_cfg)
-{
- #if !BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG
-
- /* If the MCU does not have sample and hold, verify the sample and hold feature is not used. */
- FSP_ASSERT(0U == p_channel_cfg->sample_hold_mask);
- FSP_PARAMETER_NOT_USED(p_instance_ctrl);
- #else
- if (0U != p_channel_cfg->sample_hold_mask)
- {
- /* Sample and Hold channels can only be 0, 1, 2 and must have at least minimum state count specified (reference
- * section 47.2.15 "A/D Sample and Hold Circuit Control Register (ADSHCR)" in the RA6M3 manual
- * R01UH0886EJ0100. */
- FSP_ASSERT(p_channel_cfg->sample_hold_mask <= ADC_SAMPLE_HOLD_CHANNELS);
- FSP_ASSERT(p_channel_cfg->sample_hold_states >= ADC_SAMPLE_STATE_HOLD_COUNT_MIN);
-
- uint32_t b_mask = p_channel_cfg->sample_hold_mask & p_channel_cfg->scan_mask_group_b;
- if (ADC_MODE_GROUP_SCAN == p_instance_ctrl->p_cfg->mode)
- {
- if (ADC_GROUP_A_PRIORITY_OFF != p_channel_cfg->priority_group_a)
- {
- /* Sample and hold channels cannot be in GroupB if GroupA priority enabled. (reference SHANS[2:0] bits
- * in section 47.2.15 "A/D Sample and Hold Circuit Control Register (ADSHCR)" in the RA6M3 manual
- * R01UH0886EJ0100.*/
- FSP_ASSERT(0 == b_mask);
- }
- }
- }
- #endif
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Enforces constraints on Window Compare function usage per section 47.3.5.3 "Constraints on the compare function" in
- * the RA6M3 User's Manual (R01UH0886EJ0100)
- *
- * @param[in] p_window_cfg Pointer to window compare configuration
- *
- * @retval FSP_SUCCESS No configuration errors detected
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- **********************************************************************************************************************/
-static fsp_err_t r_adc_scan_cfg_check_window_compare (adc_window_cfg_t const * const p_window_cfg)
-{
- if (p_window_cfg)
- {
- uint32_t compare_cfg = p_window_cfg->compare_cfg;
- if (0U != compare_cfg)
- {
- if ((compare_cfg & R_ADC0_ADCMPCR_CMPAE_Msk) && (compare_cfg & R_ADC0_ADCMPCR_CMPBE_Msk))
- {
- /* Ensure channels selected for Window A do not conflict with Window B */
- uint32_t compare_b_ch = p_window_cfg->compare_b_channel;
- compare_b_ch -= compare_b_ch > 31 ? 4 : 0;
- FSP_ASSERT(!(p_window_cfg->compare_mask & (uint32_t) (1 << compare_b_ch)));
- }
-
- if (compare_cfg & R_ADC0_ADCMPCR_WCMPE_Msk)
- {
- /* Ensure lower reference values are less than or equal to the high reference values */
- FSP_ASSERT((p_window_cfg->compare_ref_low <= p_window_cfg->compare_ref_high) &&
- (p_window_cfg->compare_b_ref_low <= p_window_cfg->compare_b_ref_high));
- }
- }
- }
-
- return FSP_SUCCESS;
-}
-
-#endif
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
-/*******************************************************************************************************************//**
- * This function checks the Temperature and Voltage sensor arguments
- *
- * @param[in] p_instance_ctrl Pointer to instance control block
- * @param[in] p_channel_cfg Pointer to channel configuration
- *
- * @retval FSP_SUCCESS No configuration errors detected
- * @retval FSP_ERR_ASSERTION Sensor configuration has been selected for Group B on an MCU which does not allow
- * Group B configuration or sensor is used in Normal/Group A with the double trigger
- * not enabled or MCU does not allow both the sensors to be used simultaneously
- **********************************************************************************************************************/
-static fsp_err_t r_adc_scan_cfg_check_sensors (adc_instance_ctrl_t * const p_instance_ctrl,
- adc_channel_cfg_t const * const p_channel_cfg)
-{
- /* Some MCUs have nothing to check here. */
- FSP_PARAMETER_NOT_USED(p_channel_cfg);
-
- #if !BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED
-
- /* Sensors are not supported in Group B in some MCUs. Reference section 32.2.14 "A/D Conversion Extended Input
- * Control Register (ADEXICR)" of the RA2A1 manual R01UH0888EJ0100. */
- FSP_ASSERT(0U == (p_channel_cfg->scan_mask_group_b & ADC_MASK_SENSORS));
- #endif
-
- #if BSP_FEATURE_ADC_SENSORS_EXCLUSIVE
- uint32_t sensor_mask = p_channel_cfg->scan_mask & ADC_MASK_SENSORS;
- if (0U != sensor_mask)
- {
- /* If the temperature sensor or the internal voltage reference is used, then none of the channels can be used
- * at the same time. The temperature sensor and the internal voltage reference can only be used in single scan
- * mode. Reference TSSA and OCSA bits in section 35.2.13 "A/D Conversion Extended Input Control Register
- * (ADEXICR)" of the RA4M1 manual R01UH0887EJ0100. */
- FSP_ASSERT(ADC_MASK_SENSORS != sensor_mask);
- FSP_ASSERT(p_channel_cfg->scan_mask == sensor_mask);
- FSP_ASSERT(ADC_MODE_SINGLE_SCAN == p_instance_ctrl->p_cfg->mode);
- }
- #endif
-
- /* When using double-trigger modes the sensors must not be configured or used in Group A. */
- adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend;
- if (ADC_DOUBLE_TRIGGER_DISABLED != p_cfg_extend->double_trigger_mode)
- {
- FSP_ASSERT(0U == (p_channel_cfg->scan_mask & ADC_MASK_SENSORS));
- }
-
- return FSP_SUCCESS;
-}
-
-#endif
-
-/*******************************************************************************************************************//**
- * The Open function applies power to the A/D peripheral, sets the operational mode, trigger sources, and
- * configurations common to all channels and sensors.
- *
- * @param[in] p_instance_ctrl Pointer to instance control block
- * @param[in] p_cfg Pointer to configuration structure
- **********************************************************************************************************************/
-static void r_adc_open_sub (adc_instance_ctrl_t * const p_instance_ctrl, adc_cfg_t const * const p_cfg)
-{
- adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_cfg->p_extend;
-
- /* Determine the value for ADCSR:
- * * The configured mode is set in ADCSR.ADCS.
- * * ADCSR.GBADIE is always set by this driver. It will only trigger an interrupt in group mode if the group B
- * interrupt is enabled.
- * * If double-trigger mode is selected ADCSR.DBLANS is set to the chosen double-trigger scan channel and
- * ADCSR.DBLE is set to 1; otherwise, both are set to 0.
- * * The configured trigger mode is set in ADCSR.EXTRG and ADCSR.TRGE.
- * * The value to set in ADCSR to start a scan is stored in the control structure. ADCSR.ADST is set in
- * R_ADC_ScanStart if software trigger mode is used.
- */
- uint32_t adcsr = (uint32_t) (p_cfg->mode << R_ADC0_ADCSR_ADCS_Pos);
- adcsr |= (uint32_t) (R_ADC0_ADCSR_GBADIE_Msk);
- adcsr |= ((uint32_t) p_cfg->trigger << R_ADC0_ADCSR_EXTRG_Pos);
-
- if (ADC_DOUBLE_TRIGGER_DISABLED != p_cfg_extend->double_trigger_mode)
- {
- adcsr |= R_ADC0_ADCSR_TRGE_Msk | R_ADC0_ADCSR_DBLE_Msk;
- }
- else if (ADC_TRIGGER_SOFTWARE == p_cfg->trigger)
- {
- adcsr |= R_ADC0_ADCSR_ADST_Msk;
- }
- else
- {
- /* Do nothing. */
- }
-
- p_instance_ctrl->scan_start_adcsr = (uint16_t) adcsr;
-
- /* The default value for ADSTRGR is 0 out of reset. Update it only if the ADC is triggered on ELC events. */
- uint32_t adstrgr = 0U;
- if (ADC_TRIGGER_SYNC_ELC == p_cfg->trigger)
- {
- /* Set ADSTRGR per the following:
- * Extended double-trigger mode:
- * - Normal (Group A): ELC_PERIPHERAL_ADCn and ELC_PERIPHERAL_ADCn_B
- * - Group B: None
- * All other modes:
- * - Normal (Group A): ELC_PERIPHERAL_ADCn
- * - Group B: ELC_PERIPHERAL_ADCn_B
- */
- adstrgr = adc_elc_trigger_lut[p_cfg_extend->double_trigger_mode];
- }
-
- /* Determine the value for ADCER:
- * * The resolution is set as configured in ADCER.ADPRC (on MCUs that have this bitfield).
- * * The alignment is set as configured in ADCER.ADFMT (on MCUs that have this bitfield).
- * * The clearing option is set as configured in ADCER.ACE.
- * * Always select data range of 0 - 32767 in ADCER.INV (on MCUs that have this bitfield).
- * * Always disable self-diagnosis (unsupported in this module).
- */
- uint32_t adcer = 0U;
-#if BSP_FEATURE_ADC_HAS_ADCER_ADPRC
- adcer |= (uint32_t) p_cfg->resolution << R_ADC0_ADCER_ADPRC_Pos;
-#endif
-#if BSP_FEATURE_ADC_HAS_ADCER_ADRFMT
- adcer |= (uint32_t) p_cfg->alignment << R_ADC0_ADCER_ADRFMT_Pos;
-#endif
- adcer |= (uint32_t) p_cfg_extend->clearing << R_ADC0_ADCER_ACE_Pos;
-
-#if BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE
- adcer |= 1U << R_ADC0_ADCER_ADINV_Pos;
-#endif
-
- /* Determine the value for ADADC:
- * * The addition/averaging modes are set as configured in ADADC.ADC and ADADC.AVEE.
- * * On MCUs that do not have the ADADC.AVEE bit (addition not supported), the ADADC.AVEE bit is cleared.
- */
- uint32_t adadc = p_cfg_extend->add_average_count;
-#if !BSP_FEATURE_ADC_ADDITION_SUPPORTED
- adadc &= ~ADC_ADADC_AVEE_BIT;
-#endif
-
- /* Apply clock to peripheral. */
- R_BSP_MODULE_START(FSP_IP_ADC, p_cfg->unit);
-
- /* Set the predetermined values for ADCSR, ADSTRGR, ADCER, and ADADC without setting ADCSR.ADST or ADCSR.TRGE.
- * ADCSR.ADST or ADCSR.TRGE are set as configured in R_ADC_ScanStart. */
- p_instance_ctrl->p_reg->ADCSR = (uint16_t) (adcsr & ADC_PRV_ADCSR_CLEAR_ADST_TRGE);
- p_instance_ctrl->p_reg->ADSTRGR = (uint16_t) adstrgr;
- p_instance_ctrl->p_reg->ADCER = (uint16_t) adcer;
- p_instance_ctrl->p_reg->ADADC = (uint8_t) adadc;
-
-#if BSP_FEATURE_ADC_HAS_PGA
-
- /* Disable the unused ADC PGA feature (on MCUs where it is available) since the feature is enabled out of reset on
- * some MCUs and disabled on others and affects the operation of the normal ADC channels that are multiplexed with
- * the PGA. */
- p_instance_ctrl->p_reg->ADPGADCR0 = ADC_ADPGADCR0_DISABLE_PGA;
- p_instance_ctrl->p_reg->ADPGACR = ADC_ADPGACR_DISABLE_PGA;
-#endif
-
-#if BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE
-
- /* Use ADC in single-ended mode. */
- p_instance_ctrl->p_reg->ADANIM = 0U;
-#endif
-
-#if BSP_FEATURE_ADC_HAS_VREFAMPCNT
-
- /* If VREFADC is selected as the high-potential reference voltage. */
- if (ADC_VREF_CONTROL_VREFH != p_cfg_extend->adc_vref_control)
- {
- /* Configure Reference Voltage controls
- * Reference section "32.6 Selecting Reference Voltage" in the RA2A1 manual R01UH0888EJ0100. */
- p_instance_ctrl->p_reg->VREFAMPCNT =
- (uint8_t) (p_cfg_extend->adc_vref_control &
- (R_ADC0_VREFAMPCNT_BGREN_Msk | R_ADC0_VREFAMPCNT_VREFADCG_Msk));
-
- R_BSP_SoftwareDelay(ADC_BGR_STABILIZATION_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
-
- /* Enable Over current detection and VREFADC output */
- p_instance_ctrl->p_reg->VREFAMPCNT = (uint8_t) (p_cfg_extend->adc_vref_control);
- }
-#endif
-
-#if BSP_FEATURE_ADC_HAS_ADHVREFCNT
-
- /* If the internal voltage is set as VREFH, discharge the VREF node for 1 us before setting ADHVREFCNT.HVSEL to 2.
- * Reference section 35.7 "A/D Conversion Procedure when Selecting Internal Reference Voltage as High-Potential
- * Reference Voltage" in the RA4M1 manual R01UH0887EJ0100.
- *
- * Also wait 5 us before using the ADC. This wait is the responsibility of the application. */
- if (ADC_PRV_ADHVREFCNT_VREF_INTERNAL_BIT_1 & p_cfg_extend->adc_vref_control)
- {
- p_instance_ctrl->p_reg->ADHVREFCNT = (uint8_t) (p_cfg_extend->adc_vref_control | R_ADC0_ADHVREFCNT_HVSEL_Msk);
-
- R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS);
- }
- p_instance_ctrl->p_reg->ADHVREFCNT = (uint8_t) p_cfg_extend->adc_vref_control;
-#endif
-
-#if BSP_FEATURE_ADC_HAS_ADBUF
- uint8_t adbuf = 0;
- if (1U == p_cfg_extend->enable_adbuf)
- {
- adbuf = R_ADC0_ADBUFEN_BUFEN_Msk;
- }
- p_instance_ctrl->p_reg->ADBUFEN = adbuf;
-#endif
-}
-
-/*******************************************************************************************************************//**
- * This function set the sensor bits taking into account group inclusion and addition/average mode.
- * This function must only be called if it has been verified that sensors are used in this configuration
- *
- * @param[in] p_instance_ctrl Pointer to instance control block
- * @param[in] p_channel_cfg Pointer to channel configuration
- **********************************************************************************************************************/
-static void r_adc_sensor_cfg (adc_instance_ctrl_t * const p_instance_ctrl,
- adc_channel_cfg_t const * const p_channel_cfg)
-{
- /* Calculate sample states required for temperature and voltage sensor at the current ADCLK speed. */
- uint32_t sample_states = 0U;
- r_adc_sensor_sample_state_calculation(&sample_states);
-
- /* Check if the temperature sensor channel is enabled */
- uint32_t combined_scan_mask = p_channel_cfg->scan_mask | p_channel_cfg->scan_mask_group_b;
- uint32_t adexicr = 0U;
- if (combined_scan_mask & ADC_MASK_TEMPERATURE)
- {
-#if BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE
-
- /* Power on the temperature sensor. This is only needed for TSNs that have the control register */
- R_BSP_MODULE_START(FSP_IP_TSN, 0U);
-
- /* Enable the temperature sensor output to the ADC */
- R_TSN_CTRL->TSCR = ADC_PRV_TSCR_TSN_ENABLE;
-#endif
-
- /* Set sample state register to the calculated value */
- p_instance_ctrl->p_reg->ADSSTRT = (uint8_t) sample_states;
-
-#if BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED
- if (p_channel_cfg->scan_mask & ADC_MASK_TEMPERATURE)
- {
- /* Scan the temperature sensor in normal/group A. */
- adexicr |= R_ADC0_ADEXICR_TSSA_Msk;
- }
- else
- {
- /* Scan the temperature sensor in group B */
- adexicr |= R_ADC0_ADEXICR_TSSB_Msk;
- }
-
-#else
-
- /* Scan the temperature sensor in normal/group A. */
- adexicr |= R_ADC0_ADEXICR_TSSA_Msk;
-#endif
-
- /* Enable temperature addition mode if configured. */
- if (p_channel_cfg->add_mask & ADC_MASK_TEMPERATURE)
- {
- adexicr |= R_ADC0_ADEXICR_TSSAD_Msk;
- }
- }
-
- /* Check if the voltage sensor channel is enabled */
- if (combined_scan_mask & ADC_MASK_VOLT)
- {
- /*sample state registers are set to the calculated value */
- p_instance_ctrl->p_reg->ADSSTRO = (uint8_t) sample_states;
-#if BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED
- if (p_channel_cfg->scan_mask & ADC_MASK_VOLT)
- {
- /* Scan the internal reference voltage in normal/group A. */
- adexicr |= R_ADC0_ADEXICR_OCSA_Msk;
- }
- else
- {
- /* Scan the internal reference voltage in group B. */
- adexicr |= R_ADC0_ADEXICR_OCSB_Msk;
- }
-
-#else
-
- /* Scan the internal reference voltage in normal/group A. */
- adexicr |= R_ADC0_ADEXICR_OCSA_Msk;
-#endif
-
- /* Enable temperature addition mode if configured. */
- if (p_channel_cfg->add_mask & ADC_MASK_VOLT)
- {
- adexicr |= R_ADC0_ADEXICR_OCSAD_Msk;
- }
- }
-
- p_instance_ctrl->p_reg->ADEXICR = (uint16_t) adexicr;
-}
-
-/*******************************************************************************************************************//**
- * This function calculates the sample states value for the internal sensors and returns an error if the calculated
- * value is outside the limit supported by the hardware
- *
- * @param[out] p_sample_states: The calculates sample state count.
- **********************************************************************************************************************/
-static void r_adc_sensor_sample_state_calculation (uint32_t * const p_sample_states)
-{
- /* Calculate sample state values such that the sample time for the temperature and voltage sensor is the
- * minimum defined by the hardware manual. The minimum is 4.15 microseconds for MF3 devices and
- * 5 microseconds for RV40. The sample states will be calculated to allow sampling for this duration. */
-
- /* Retrieve the clock source and frequency used by the ADC peripheral and sampling time required for the sensor. */
- uint32_t freq_hz = R_FSP_SystemClockHzGet(BSP_FEATURE_ADC_CLOCK_SOURCE);
-
- /* Calculate sample states required for the current ADC conversion clock (reference section 47.2.14 "A/D Sampling
- * State Register n (ADSSTRn) (n = 00 to 07, L, T, O)" in the RA6M3 manual R01UH0886EJ0100.
- *
- * sample_states = required_sample_time / adclk_period
- * = required_sample_time (nsec) * adclk_frequency (kHz) / 1000000 (usec / sec) + 1
- * (refactored to avoid overflowing 32 bits, 1 added to round up)
- */
- uint32_t sample_states = ((BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME * (freq_hz / ADC_PRV_HZ_PER_KHZ)) /
- ADC_PRV_USEC_PER_SEC) + 1U;
-
- /* The fastest ADC conversion clock is 60 MHz, and the associated sampling time is 4.15 microseconds. The number
- * of sample states in this case is 0.00000415 / (1 / 60000000) = 249. This is the maximum number of sample states
- * required for the on chip sensors, so this calculation will never overflow 8 bits (255). */
-
- /* If sample states are less than the min number of states required, then set them to the minimum. */
- if (sample_states < ADC_SAMPLE_STATE_COUNT_MIN)
- {
- sample_states = ADC_SAMPLE_STATE_COUNT_MIN;
- }
-
- *p_sample_states = sample_states;
-}
-
-#if ADC_CFG_PARAM_CHECKING_ENABLE
-
-/*******************************************************************************************************************//**
- * This function does extensive checking on channel mask settings based upon operational mode.
- *
- * @param[in] p_instance_ctrl Pointer to instance control block
- * @param[in] p_channel_cfg Pointer to channel configuration
- *
- * @retval FSP_SUCCESS No configuration errors detected
- * @retval FSP_ERR_ASSERTION An input argument is invalid.
- **********************************************************************************************************************/
-static fsp_err_t r_adc_scan_cfg_check (adc_instance_ctrl_t * const p_instance_ctrl,
- adc_channel_cfg_t const * const p_channel_cfg)
-{
- fsp_err_t err;
- uint16_t unit = p_instance_ctrl->p_cfg->unit;
-
- /* Verify at least one channel is selected for normal / group A. */
- uint32_t valid_channels = g_adc_valid_channels[unit] | ADC_MASK_TEMPERATURE | ADC_MASK_VOLT;
- FSP_ASSERT((0U != p_channel_cfg->scan_mask) && (0U == (p_channel_cfg->scan_mask & (~valid_channels))));
-
- if (ADC_MODE_GROUP_SCAN == p_instance_ctrl->p_cfg->mode)
- {
- /* Verify at least one channel is selected for group B. */
- FSP_ASSERT((0U != p_channel_cfg->scan_mask_group_b) &&
- (0U == (p_channel_cfg->scan_mask_group_b & (~valid_channels))));
-
- /* Cannot have the same channel in both groups. */
- FSP_ASSERT(0 == (p_channel_cfg->scan_mask & p_channel_cfg->scan_mask_group_b));
- }
- else
- {
- /* If group mode is not enabled, no channels can be selected for group B. */
- FSP_ASSERT(ADC_MASK_OFF == p_channel_cfg->scan_mask_group_b);
- }
-
- /* Verify sensor configuration. */
- err = r_adc_scan_cfg_check_sensors(p_instance_ctrl, p_channel_cfg);
- FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-
- /* Verify that if addition is enabled, then at least one channel is selected. */
- adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend;
- if (ADC_ADD_OFF != p_cfg_extend->add_average_count)
- {
- /* Addition mask should not include bits from inactive channels.
- * This also serves as a check for valid channels in the addition mask */
- uint32_t tmp_mask = p_channel_cfg->scan_mask_group_b | p_channel_cfg->scan_mask;
- FSP_ASSERT((0U == (p_channel_cfg->add_mask & ~tmp_mask)) && (0U != p_channel_cfg->add_mask));
- }
- else
- {
- /* Channels cannot be selected for addition if addition is not used. */
- FSP_ASSERT(ADC_MASK_OFF == p_channel_cfg->add_mask);
- }
-
- /* Check sample and hold settings. */
- err = r_adc_scan_cfg_check_sample_hold(p_instance_ctrl, p_channel_cfg);
- FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
-
- /* Check window compare settings. */
- err = r_adc_scan_cfg_check_window_compare(p_channel_cfg->p_window_cfg);
-
- return err;
-}
-
-#endif
-
-/*******************************************************************************************************************//**
- * This function does extensive checking on channel mask settings based upon operational mode. Mask registers are
- * initialized and interrupts enabled in peripheral. Interrupts are also enabled in ICU if corresponding priority
- * is not 0.
- *
- * @param[in] p_instance_ctrl Pointer to instance control block
- * @param[in] p_channel_cfg Pointer to channel configuration
- **********************************************************************************************************************/
-static void r_adc_scan_cfg (adc_instance_ctrl_t * const p_instance_ctrl, adc_channel_cfg_t const * const p_channel_cfg)
-{
- /* Set mask for Group A channels. */
- uint32_t scan_mask = p_channel_cfg->scan_mask & ~(uint32_t) ADC_MASK_SENSORS;
- adc_extended_cfg_t const * p_cfg_extend = (adc_extended_cfg_t const *) p_instance_ctrl->p_cfg->p_extend;
-
- /* Set other channel masks. */
- uint32_t scan_mask_group_b = p_channel_cfg->scan_mask_group_b & ~(uint32_t) ADC_MASK_SENSORS;
- uint32_t add_mask = p_channel_cfg->add_mask & ~(uint32_t) ADC_MASK_SENSORS;
-
- p_instance_ctrl->p_reg->ADANSA[0] = (uint16_t) (scan_mask);
- p_instance_ctrl->p_reg->ADANSB[0] = (uint16_t) (scan_mask_group_b);
- p_instance_ctrl->p_reg->ADADS[0] = (uint16_t) (add_mask);
- p_instance_ctrl->p_reg->ADANSA[1] = (uint16_t) ((scan_mask >> 16));
- p_instance_ctrl->p_reg->ADANSB[1] = (uint16_t) ((scan_mask_group_b >> 16));
- p_instance_ctrl->p_reg->ADADS[1] = (uint16_t) ((add_mask >> 16));
-
- /* If either voltage or temperature sensor are used, configure them. */
- uint32_t temp_mask = p_channel_cfg->scan_mask | p_channel_cfg->scan_mask_group_b;
- if (temp_mask & ADC_MASK_SENSORS)
- {
- /* Calculate sample state values such that the sample time for the temperature and voltage sensor is the
- * minimum defined by the hardware manual. The minimum is 4.15 microseconds for MF3 devices and
- * 5 microseconds for RV40. The sample states will be calculated to allow sampling for this duration. */
-
- /* Retrieve the clock source and frequency used by the ADC peripheral and sampling time required for the sensor. */
- r_adc_sensor_cfg(p_instance_ctrl, p_channel_cfg);
- }
-
-#if BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG
-
- /* Configure sample and hold. */
- uint32_t adshcr = p_channel_cfg->sample_hold_states;
- adshcr |= (p_channel_cfg->sample_hold_mask & ADC_MASK_SAMPLE_HOLD_BYPASS_CHANNELS) <<
- ADC_MASK_SAMPLE_HOLD_BYPASS_SHIFT;
- p_instance_ctrl->p_reg->ADSHCR = (uint16_t) adshcr;
-#endif
-
- /* Get window compare configuration */
- adc_window_cfg_t * p_window_cfg = p_channel_cfg->p_window_cfg;
-
- uint16_t adcmpcr = 0;
-
- if (p_window_cfg)
- {
- /* Save window compare config */
- adcmpcr = (uint16_t) p_window_cfg->compare_cfg;
-
- if (p_window_cfg->compare_cfg & R_ADC0_ADCMPCR_CMPAE_Msk)
- {
- /* Set Window A boundary values */
- p_instance_ctrl->p_reg->ADCMPCR = p_window_cfg->compare_cfg & UINT16_MAX;
- p_instance_ctrl->p_reg->ADCMPDR0 = p_window_cfg->compare_ref_low;
- p_instance_ctrl->p_reg->ADCMPDR1 = p_window_cfg->compare_ref_high;
-
- /* Set Window A channel mask */
- p_instance_ctrl->p_reg->ADCMPANSR[0] = p_window_cfg->compare_mask & UINT16_MAX;
- p_instance_ctrl->p_reg->ADCMPANSR[1] = (uint16_t) ((p_window_cfg->compare_mask << 4) >> 20);
- p_instance_ctrl->p_reg->ADCMPANSER = (uint8_t) (p_window_cfg->compare_mask >> 28);
-
- /* Set Window A channel inequality mode mask */
- p_instance_ctrl->p_reg->ADCMPLR[0] = p_window_cfg->compare_mode_mask & UINT16_MAX;
- p_instance_ctrl->p_reg->ADCMPLR[1] = (uint16_t) ((p_window_cfg->compare_mode_mask << 4) >> 20);
- p_instance_ctrl->p_reg->ADCMPLER = (uint8_t) (p_window_cfg->compare_mode_mask >> 28);
- }
-
- if (p_window_cfg->compare_cfg & R_ADC0_ADCMPCR_CMPBE_Msk)
- {
- /* Set Window B channel and mode */
- p_instance_ctrl->p_reg->ADCMPBNSR = (uint8_t) ((adc_window_b_mode_t) p_window_cfg->compare_b_channel |
- p_window_cfg->compare_b_mode);
-
- /* Set Window B boundary values */
- p_instance_ctrl->p_reg->ADWINLLB = p_window_cfg->compare_b_ref_low;
- p_instance_ctrl->p_reg->ADWINULB = p_window_cfg->compare_b_ref_high;
- }
- }
-
- /* Set window compare config */
- p_instance_ctrl->p_reg->ADCMPCR = adcmpcr;
-
- /* Set group A priority action (not interrupt priority!)
- * This will also start the Group B scans if configured for ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN.
- */
- p_instance_ctrl->p_reg->ADGSPCR = (uint16_t) p_channel_cfg->priority_group_a;
-
- /* In double-trigger mode set the channel select bits to the highest selected channel number then return. */
- if (ADC_DOUBLE_TRIGGER_DISABLED != p_cfg_extend->double_trigger_mode)
- {
- uint32_t adcsr = p_instance_ctrl->p_reg->ADCSR;
- adcsr = (adcsr & ~R_ADC0_ADCSR_DBLANS_Msk) + (31U - __CLZ(scan_mask));
-
- p_instance_ctrl->p_reg->ADCSR = (uint16_t) adcsr;
- p_instance_ctrl->scan_start_adcsr |= (uint16_t) adcsr;
- }
-
- p_instance_ctrl->initialized = ADC_OPEN;
-}
-
-/*******************************************************************************************************************//**
- * Disables and clears context for the requested IRQ.
- *
- * @param[in] irq IRQ to enable
- * @param[in] ipl Interrupt priority
- * @param[in] p_context Pointer to interrupt context
- **********************************************************************************************************************/
-static void r_adc_irq_enable (IRQn_Type irq, uint8_t ipl, void * p_context)
-{
- if (irq >= 0)
- {
- R_BSP_IrqCfgEnable(irq, ipl, p_context);
- }
-}
-
-/*******************************************************************************************************************//**
- * Disables and clears context for the requested IRQ.
- *
- * @param[in] irq IRQ to disable
- **********************************************************************************************************************/
-static void r_adc_irq_disable (IRQn_Type irq)
-{
- if (irq >= 0)
- {
- R_BSP_IrqDisable(irq);
- R_FSP_IsrContextSet(irq, NULL);
- }
-}
-
-/*******************************************************************************************************************//**
- * Returns the lowest channel index that is configured in order to read the results of the configured channels.
- *
- * @param[in] adc_mask scan mask of active channels retrieved from the control structure
- *
- * @retval adc_mask_count index value of lowest channel
- **********************************************************************************************************************/
-static int32_t r_adc_lowest_channel_get (uint32_t adc_mask)
-{
- /* Initialize the mask result */
- uint32_t adc_mask_result = 0U;
- int32_t adc_mask_count = -1;
- while (0U == adc_mask_result)
- {
- /* Increment channel until a channel is found in the mask. */
- adc_mask_count++;
- adc_mask_result = (uint32_t) (adc_mask & (1U << adc_mask_count));
- }
-
- return adc_mask_count;
-}
-
-/*******************************************************************************************************************//**
- * Calls user callback.
- *
- * @param[in] p_ctrl Pointer to ADC instance control block
- * @param[in] p_args Pointer to arguments on stack
- **********************************************************************************************************************/
-static void r_adc_call_callback (adc_instance_ctrl_t * p_ctrl, adc_callback_args_t * p_args)
-{
- adc_callback_args_t args;
-
- /* Store callback arguments in memory provided by user if available. This allows callback arguments to be
- * stored in non-secure memory so they can be accessed by a non-secure callback function. */
- adc_callback_args_t * p_args_memory = p_ctrl->p_callback_memory;
- if (NULL == p_args_memory)
- {
- /* Use provided args struct on stack */
- p_args_memory = p_args;
- }
- else
- {
- /* Save current arguments on the stack in case this is a nested interrupt. */
- args = *p_args_memory;
-
- /* Copy the stacked args to callback memory */
- *p_args_memory = *p_args;
- }
-
-#if BSP_TZ_SECURE_BUILD
-
- /* p_callback can point to a secure function or a non-secure function. */
- if (!cmse_is_nsfptr(p_ctrl->p_callback))
- {
- /* If p_callback is secure, then the project does not need to change security state. */
- p_ctrl->p_callback(p_args_memory);
- }
- else
- {
- /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */
- adc_prv_ns_callback p_callback = (adc_prv_ns_callback) (p_ctrl->p_callback);
- p_callback(p_args_memory);
- }
-
-#else
-
- /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */
- p_ctrl->p_callback(p_args_memory);
-#endif
-
- if (NULL != p_ctrl->p_callback_memory)
- {
- /* Restore callback memory in case this is a nested interrupt. */
- *p_ctrl->p_callback_memory = args;
- }
-}
-
-/*******************************************************************************************************************//**
- * Clears interrupt flag and calls a callback to notify application of the event.
- *
- * @param[in] event Event that triggered the ISR
- **********************************************************************************************************************/
-static void r_adc_scan_end_common_isr (adc_event_t event)
-{
- /* Save context if RTOS is used */
- FSP_CONTEXT_SAVE;
-
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) R_FSP_IsrContextGet(R_FSP_CurrentIrqGet());
-
- /* Clear the BSP IRQ Flag */
- R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet());
-
- adc_callback_args_t args;
- args.event = event;
-#if BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE
-
- /* Store the correct event into the callback argument */
- if (ADC_ADICR_CALIBRATION_INTERRUPT_DISABLED != p_instance_ctrl->p_reg->ADICR)
- {
- args.event = ADC_EVENT_CALIBRATION_COMPLETE;
-
- /* Restore the interrupt source to disable interrupts after calibration is done. */
- p_instance_ctrl->p_reg->ADICR = 0U;
- }
-#endif
-
- /* Store the unit number into the callback argument */
- args.unit = p_instance_ctrl->p_cfg->unit;
-
- /* Initialize the channel to 0. It is not used in this implementation. */
- args.channel = ADC_CHANNEL_0;
-
- /* Populate the context field. */
- args.p_context = p_instance_ctrl->p_context;
-
- /* If a callback was provided, call it with the argument */
- if (NULL != p_instance_ctrl->p_callback)
- {
- r_adc_call_callback(p_instance_ctrl, &args);
- }
-
- /* Restore context if RTOS is used */
- FSP_CONTEXT_RESTORE;
-}
-
-/*******************************************************************************************************************//**
- * This function implements the unit 0 interrupt handler for normal/Group A/double trigger scan complete.
- **********************************************************************************************************************/
-void adc_scan_end_isr (void)
-{
- r_adc_scan_end_common_isr(ADC_EVENT_SCAN_COMPLETE);
-}
-
-/*******************************************************************************************************************//**
- * This function implements the interrupt handler for Group B scan complete.
- **********************************************************************************************************************/
-void adc_scan_end_b_isr (void)
-{
- r_adc_scan_end_common_isr(ADC_EVENT_SCAN_COMPLETE_GROUP_B);
-}
-
-/*******************************************************************************************************************//**
- * This function implements the interrupt handler for window compare events.
- **********************************************************************************************************************/
-void adc_window_compare_isr (void)
-{
- /* Save context if RTOS is used */
- FSP_CONTEXT_SAVE;
-
- IRQn_Type irq = R_FSP_CurrentIrqGet();
-
- adc_instance_ctrl_t * p_instance_ctrl = (adc_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
- adc_extended_cfg_t * p_extend = (adc_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
-
- adc_callback_args_t args;
- args.event = (irq == p_extend->window_a_irq) ? ADC_EVENT_WINDOW_COMPARE_A : ADC_EVENT_WINDOW_COMPARE_B;
-
- /* Store the unit number into the callback argument */
- args.unit = p_instance_ctrl->p_cfg->unit;
-
- if (ADC_EVENT_WINDOW_COMPARE_A == args.event)
- {
- args.channel = (adc_channel_t) 0;
-
- R_ADC0_Type * p_reg = p_instance_ctrl->p_reg;
-
- /* Get all Window A status registers */
- uint16_t adcmpsr0 = p_reg->ADCMPSR[0];
- uint16_t adcmpsr1 = p_reg->ADCMPSR[1];
- uint8_t adcmpser = p_reg->ADCMPSER;
-
- /* Get the lowest channel that meets Window A criteria */
- uint32_t lowest_channel = __CLZ(__RBIT(adcmpsr0 + (uint32_t) (adcmpsr1 << 16) + (uint32_t) (adcmpser << 28)));
-
- /* Clear the status flag corresponding to the lowest channel */
- if (lowest_channel < 16)
- {
- p_reg->ADCMPSR[0] = (uint16_t) (adcmpsr0 & ~(1 << (lowest_channel & 0xF)));
- }
- else if (lowest_channel < 28)
- {
- p_reg->ADCMPSR[1] = (uint16_t) (adcmpsr1 & ~(1 << (lowest_channel & 0xF)));
- }
- else
- {
- p_reg->ADCMPSER = (uint8_t) (adcmpser & ~(1 << (lowest_channel & 0x3)));
- }
-
- args.channel = (adc_channel_t) lowest_channel;
-
- if (args.channel > 28)
- {
- /* Adjust sensor channels to align with the adc_channel_t enumeration */
- args.channel = (adc_channel_t) (ADC_CHANNEL_TEMPERATURE + (args.channel - 28));
- }
- }
- else
- {
- /* Get channel selected for Window B */
- args.channel = (adc_channel_t) p_instance_ctrl->p_reg->ADCMPBNSR_b.CMPCHB;
-
- if (args.channel > 31)
- {
- /* Adjust sensor channels to align with the adc_channel_t enumeration */
- args.channel = (adc_channel_t) (ADC_CHANNEL_TEMPERATURE + (args.channel & 0xF));
- }
-
- /* Clear IRQ */
- p_instance_ctrl->p_reg->ADCMPBSR_b.CMPSTB = 0;
- }
-
- /* Populate the context field. */
- args.p_context = p_instance_ctrl->p_context;
-
- /* If a callback was provided, call it with the argument */
- if (NULL != p_instance_ctrl->p_callback)
- {
- r_adc_call_callback(p_instance_ctrl, &args);
- }
-
- R_BSP_IrqStatusClear(irq);
-
- /* Restore context if RTOS is used */
- FSP_CONTEXT_RESTORE;
-}
diff --git a/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_gpt/r_gpt.c b/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_gpt/r_gpt.c
deleted file mode 100644
index cc54467e55..0000000000
--- a/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/r_gpt/r_gpt.c
+++ /dev/null
@@ -1,1830 +0,0 @@
-/***********************************************************************************************************************
- * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
- *
- * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
- * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
- * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
- * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
- * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
- * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
- * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
- * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
- * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
- * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
- * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
- * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
- * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
- * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Includes
- **********************************************************************************************************************/
-#include "r_gpt.h"
-#include "r_gpt_cfg.h"
-
-/***********************************************************************************************************************
- * Macro definitions
- **********************************************************************************************************************/
-
-/* "GPT" in ASCII, used to determine if channel is open. */
-#define GPT_OPEN (0x00475054ULL)
-
-#define GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK (BSP_FEATURE_GPTEH_CHANNEL_MASK | \
- BSP_FEATURE_GPTE_CHANNEL_MASK)
-
-#define GPT_PRV_GTWP_RESET_VALUE (0xA500U)
-#define GPT_PRV_GTWP_WRITE_PROTECT (0xA501U)
-
-#define GPT_PRV_GTIOR_STOP_LEVEL_BIT (6)
-#define GPT_PRV_GTIOR_INITIAL_LEVEL_BIT (4)
-
-#define GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END (0x6U)
-#define GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END (0x9U)
-
-#define GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH (0x3U)
-
-#define GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER (0x550000U)
-
-#define GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE (0x80000000U)
-
-#define GPT_PRV_GTCCRA (0U)
-#define GPT_PRV_GTCCRB (1U)
-#define GPT_PRV_GTCCRC (2U)
-#define GPT_PRV_GTCCRE (3U)
-#define GPT_PRV_GTCCRD (4U)
-#define GPT_PRV_GTCCRF (5U)
-
-/* GPT_CFG_OUTPUT_SUPPORT_ENABLE is set to 2 to enable extra features. */
-#define GPT_PRV_EXTRA_FEATURES_ENABLED (2U)
-
-#define R_GPT0_GTINTAD_ADTRAUEN_Pos (16U)
-
-/***********************************************************************************************************************
- * Typedef definitions
- **********************************************************************************************************************/
-
-/* Duty cycle mode. */
-typedef enum e_gpt_duty_cycle_mode
-{
- GPT_DUTY_CYCLE_MODE_REGISTER = 0, // Duty cycle depends on compare match
- GPT_DUTY_CYCLE_MODE_0_PERCENT = 2, // Output low
- GPT_DUTY_CYCLE_MODE_100_PERCENT = 3, // Output high
-} gpt_duty_cycle_mode_t;
-
-/* Count direction */
-typedef enum e_gpt_dir
-{
- GPT_DIR_COUNT_DOWN = 0,
- GPT_DIR_COUNT_UP = 1
-} gpt_dir_t;
-
-typedef struct st_gpt_prv_duty_registers
-{
- uint32_t gtccr_buffer;
- uint32_t omdty;
-} gpt_prv_duty_registers_t;
-
-typedef enum e_gpt_prv_capture_event
-{
- GPT_PRV_CAPTURE_EVENT_A,
- GPT_PRV_CAPTURE_EVENT_B,
-} gpt_prv_capture_event_t;
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef void (BSP_CMSE_NONSECURE_CALL * gpt_prv_ns_callback)(timer_callback_args_t * p_args);
-#elif defined(__GNUC__)
-typedef BSP_CMSE_NONSECURE_CALL void (*volatile gpt_prv_ns_callback)(timer_callback_args_t * p_args);
-#endif
-
-/***********************************************************************************************************************
- * Private function prototypes
- **********************************************************************************************************************/
-static void gpt_hardware_initialize(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
-
-static void gpt_common_open(gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg);
-
-static uint32_t gpt_clock_frequency_get(gpt_instance_ctrl_t * const p_instance_ctrl);
-
-static void gpt_hardware_events_disable(gpt_instance_ctrl_t * p_instance_ctrl);
-
-static void r_gpt_disable_irq(IRQn_Type irq);
-
-static inline void r_gpt_write_protect_enable(gpt_instance_ctrl_t * const p_instance_ctrl,
- uint32_t write_protect_setting);
-static inline uint32_t r_gpt_write_protect_disable(gpt_instance_ctrl_t * const p_instance_ctrl);
-
-/* Noinline attribute added to reduce code size for CM23 GCC build. */
-static void r_gpt_enable_irq(IRQn_Type const irq, uint32_t priority, void * p_context) __attribute__((noinline));
-
-#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
-
-static void gpt_calculate_duty_cycle(gpt_instance_ctrl_t * const p_instance_ctrl,
- uint32_t const duty_cycle_counts,
- gpt_prv_duty_registers_t * p_duty_reg,
- uint32_t pin);
-
-static uint32_t gpt_gtior_calculate(timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level);
-
-#endif
-
-static void r_gpt_call_callback(gpt_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture);
-
-/***********************************************************************************************************************
- * ISR prototypes
- **********************************************************************************************************************/
-void gpt_counter_overflow_isr(void);
-void gpt_counter_underflow_isr(void);
-void gpt_capture_a_isr(void);
-void gpt_capture_b_isr(void);
-
-/***********************************************************************************************************************
- * Private global variables
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Global Variables
- **********************************************************************************************************************/
-
-/* GPT implementation of timer interface */
-const timer_api_t g_timer_on_gpt =
-{
- .open = R_GPT_Open,
- .stop = R_GPT_Stop,
- .start = R_GPT_Start,
- .reset = R_GPT_Reset,
- .enable = R_GPT_Enable,
- .disable = R_GPT_Disable,
- .periodSet = R_GPT_PeriodSet,
- .dutyCycleSet = R_GPT_DutyCycleSet,
- .infoGet = R_GPT_InfoGet,
- .statusGet = R_GPT_StatusGet,
- .callbackSet = R_GPT_CallbackSet,
- .close = R_GPT_Close,
-};
-
-/*******************************************************************************************************************//**
- * @addtogroup GPT
- * @{
- **********************************************************************************************************************/
-
-/***********************************************************************************************************************
- * Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Initializes the timer module and applies configurations. Implements @ref timer_api_t::open.
- *
- * GPT hardware does not support one-shot functionality natively. When using one-shot mode, the timer will be stopped
- * in an ISR after the requested period has elapsed.
- *
- * The GPT implementation of the general timer can accept a gpt_extended_cfg_t extension parameter.
- *
- * Example:
- * @snippet r_gpt_example.c R_GPT_Open
- *
- * @retval FSP_SUCCESS Initialization was successful and timer has started.
- * @retval FSP_ERR_ASSERTION A required input pointer is NULL or the source divider is invalid.
- * @retval FSP_ERR_ALREADY_OPEN Module is already open.
- * @retval FSP_ERR_IRQ_BSP_DISABLED timer_cfg_t::mode is ::TIMER_MODE_ONE_SHOT or timer_cfg_t::p_callback is not
- * NULL, but ISR is not enabled. ISR must be enabled to use one-shot mode or
- * callback.
- * @retval FSP_ERR_INVALID_MODE Triangle wave PWM is only supported if GPT_CFG_OUTPUT_SUPPORT_ENABLE is 2.
- * Selected channel does not support external count sources.
- * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel requested in the p_cfg parameter is not available on this device.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_Open (timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_cfg);
- FSP_ASSERT(NULL != p_cfg->p_extend);
- FSP_ASSERT(NULL != p_instance_ctrl);
-
- #if (2U == BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE)
- #if (BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID)
- FSP_ASSERT(p_cfg->source_div <= 10U);
- #else
- FSP_ASSERT((p_cfg->source_div != 7U) && (p_cfg->source_div != 9U) && (p_cfg->source_div <= 10));
- #endif
- #else
- FSP_ASSERT((0U == (p_cfg->source_div % 2U)) && (p_cfg->source_div <= 10));
- #endif
-
- #if GPT_PRV_EXTRA_FEATURES_ENABLED != GPT_CFG_OUTPUT_SUPPORT_ENABLE
- FSP_ERROR_RETURN(p_cfg->mode <= TIMER_MODE_PWM, FSP_ERR_INVALID_MODE);
- #endif
-
- FSP_ERROR_RETURN(GPT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN);
-#endif
-
- p_instance_ctrl->channel_mask = 1U << p_cfg->channel;
-
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ERROR_RETURN((p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_VALID_CHANNEL_MASK),
- FSP_ERR_IP_CHANNEL_NOT_PRESENT);
- if ((p_cfg->p_callback) || (TIMER_MODE_ONE_SHOT == p_cfg->mode))
- {
- FSP_ERROR_RETURN(p_cfg->cycle_end_irq >= 0, FSP_ERR_IRQ_BSP_DISABLED);
- }
-
- gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend;
- FSP_ERROR_RETURN((!p_extend->count_up_source && !p_extend->count_down_source) ||
- (BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK & p_instance_ctrl->channel_mask),
- FSP_ERR_INVALID_MODE);
-
- #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
-
- /* Callback is required if underflow interrupt is enabled. */
- gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
- if (NULL != p_pwm_cfg)
- {
- if (p_pwm_cfg->trough_irq >= 0)
- {
- FSP_ASSERT(NULL != p_cfg->p_callback);
- }
- }
- #endif
-#endif
-
- /* Initialize control structure based on configurations. */
- gpt_common_open(p_instance_ctrl, p_cfg);
-
- gpt_hardware_initialize(p_instance_ctrl, p_cfg);
-
- p_instance_ctrl->open = GPT_OPEN;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Stops timer. Implements @ref timer_api_t::stop.
- *
- * Example:
- * @snippet r_gpt_example.c R_GPT_Stop
- *
- * @retval FSP_SUCCESS Timer successfully stopped.
- * @retval FSP_ERR_ASSERTION p_ctrl was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_Stop (timer_ctrl_t * const p_ctrl)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Stop timer */
- p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Starts timer. Implements @ref timer_api_t::start.
- *
- * Example:
- * @snippet r_gpt_example.c R_GPT_Start
- *
- * @retval FSP_SUCCESS Timer successfully started.
- * @retval FSP_ERR_ASSERTION p_ctrl was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_Start (timer_ctrl_t * const p_ctrl)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Start timer */
- p_instance_ctrl->p_reg->GTSTR = p_instance_ctrl->channel_mask;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Resets the counter value to 0. Implements @ref timer_api_t::reset.
- *
- * @note This function also updates to the new period if no counter overflow has occurred since the last call to
- * R_GPT_PeriodSet().
- *
- * @retval FSP_SUCCESS Counter value written successfully.
- * @retval FSP_ERR_ASSERTION p_ctrl was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_Reset (timer_ctrl_t * const p_ctrl)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Clear timer counter. */
- p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Enables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::enable.
- *
- * Example:
- * @snippet r_gpt_example.c R_GPT_Enable
- *
- * @retval FSP_SUCCESS External events successfully enabled.
- * @retval FSP_ERR_ASSERTION p_ctrl was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_Enable (timer_ctrl_t * const p_ctrl)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */
- gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
- uint32_t gtssr = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
- uint32_t gtpsr = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
- uint32_t gtcsr = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
-
- /* OR with user settings. */
- gtssr |= p_extend->start_source;
- gtpsr |= p_extend->stop_source;
- gtcsr |= p_extend->clear_source;
-
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- /* Set the count sources. Ensure stop and clear sources are set before start source, and capture sources are set
- * after start source. */
- p_instance_ctrl->p_reg->GTPSR = gtpsr;
- p_instance_ctrl->p_reg->GTCSR = gtcsr;
- p_instance_ctrl->p_reg->GTSSR = gtssr;
- p_instance_ctrl->p_reg->GTICASR = p_extend->capture_a_source;
- p_instance_ctrl->p_reg->GTICBSR = p_extend->capture_b_source;
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Disables external event triggers that start, stop, clear, or capture the counter. Implements @ref timer_api_t::disable.
- *
- * @note The timer could be running after R_GPT_Disable(). To ensure it is stopped, call R_GPT_Stop().
- *
- * Example:
- * @snippet r_gpt_example.c R_GPT_Disable
- *
- * @retval FSP_SUCCESS External events successfully disabled.
- * @retval FSP_ERR_ASSERTION p_ctrl was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_Disable (timer_ctrl_t * const p_ctrl)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- gpt_hardware_events_disable(p_instance_ctrl);
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Sets period value provided. If the timer is running, the period will be updated after the next counter overflow.
- * If the timer is stopped, this function resets the counter and updates the period.
- * Implements @ref timer_api_t::periodSet.
- *
- * @warning If periodic output is used, the duty cycle buffer registers are updated after the period buffer register.
- * If this function is called while the timer is running and a GPT overflow occurs during processing, the duty cycle
- * will not be the desired 50% duty cycle until the counter overflow after processing completes.
- *
- * Example:
- * @snippet r_gpt_example.c R_GPT_PeriodSet
- *
- * @retval FSP_SUCCESS Period value written successfully.
- * @retval FSP_ERR_ASSERTION p_ctrl was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_PeriodSet (timer_ctrl_t * const p_ctrl, uint32_t const period_counts)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- /* Update period buffer register. The actual period is one cycle longer than the register value for saw waves
- * and twice the register value for triangle waves. Reference section 23.2.21 "General PWM Timer Cycle Setting
- * Register (GTPR)". The setting passed to the configuration is expected to be half the desired period for
- * triangle waves. */
- uint32_t new_gtpr = period_counts - 1U;
-#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
- if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
- {
- new_gtpr = period_counts;
- }
-#endif
-
- p_instance_ctrl->p_reg->GTPBR = new_gtpr;
-
-#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
-
- /* Set a 50% duty cycle so the period of the waveform on the output pin matches the requested period. */
- if (TIMER_MODE_PERIODIC == p_instance_ctrl->p_cfg->mode)
- {
- /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. Reference
- * Figure 23.34 "Example setting for saw-wave PWM mode" in the RA6M3 manual R01UH0886EJ0100. To get a duty cycle
- * as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */
- uint32_t duty_cycle_50_percent = (period_counts >> 1) - 1U;
- p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_cycle_50_percent;
- p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRE] = duty_cycle_50_percent;
- }
-#endif
-
- /* If the counter is not counting, update period register and reset counter. */
- if (0U == p_instance_ctrl->p_reg->GTCR_b.CST)
- {
- p_instance_ctrl->p_reg->GTPR = new_gtpr;
-
-#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
- p_instance_ctrl->p_reg->GTBER = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER;
-#endif
-
- p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask;
- }
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Sets duty cycle on requested pin. Implements @ref timer_api_t::dutyCycleSet.
- *
- * Duty cycle is updated in the buffer register. The updated duty cycle is reflected after the next cycle end (counter
- * overflow).
- *
- * Example:
- * @snippet r_gpt_example.c R_GPT_DutyCycleSet
- *
- * @param[in] p_ctrl Pointer to instance control block.
- * @param[in] duty_cycle_counts Duty cycle to set in counts.
- * @param[in] pin Use gpt_io_pin_t to select GPT_IO_PIN_GTIOCA or GPT_IO_PIN_GTIOCB
- *
- * @retval FSP_SUCCESS Duty cycle updated successfully.
- * @retval FSP_ERR_ASSERTION p_ctrl was NULL or the pin is not one of gpt_io_pin_t
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- * @retval FSP_ERR_INVALID_ARGUMENT Duty cycle is larger than period.
- * @retval FSP_ERR_INVALID_MODE GPT_IO_PIN_TROUGH, and GPT_IO_PIN_CREST settings are invalid in the this mode.
- * @retval FSP_ERR_UNSUPPORTED GPT_CFG_OUTPUT_SUPPORT_ENABLE is 0.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_DutyCycleSet (timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
-{
-#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
- uint32_t tmp_pin = pin & 3U;
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
- #if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ASSERT(tmp_pin <= GPT_IO_PIN_GTIOCA_AND_GTIOCB);
- bool pwm_mode3_pin = 0 != (pin & (GPT_IO_PIN_CREST | GPT_IO_PIN_TROUGH));
- if (TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 == p_instance_ctrl->p_cfg->mode)
- {
- /* In TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3, the duty cycle must be for either a trough or crest. */
- FSP_ERROR_RETURN(pwm_mode3_pin, FSP_ERR_INVALID_MODE);
- }
- else
- {
- FSP_ERROR_RETURN(!pwm_mode3_pin, FSP_ERR_INVALID_MODE);
- }
-
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
- FSP_ERROR_RETURN(duty_cycle_counts <= (p_instance_ctrl->p_reg->GTPR + 1), FSP_ERR_INVALID_ARGUMENT);
- #endif
-
- /* Set duty cycle. */
- gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0};
-
- gpt_calculate_duty_cycle(p_instance_ctrl, duty_cycle_counts, &duty_regs, pin);
-
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- /* Read modify write bitfield access is used to update GTUDDTYC to make sure we don't clobber settings for the
- * other pin. */
- uint32_t gtuddtyc = p_instance_ctrl->p_reg->GTUDDTYC;
-
- /* Only update GTCCR if 0% or 100% duty is not requested */
- if (!duty_regs.omdty)
- {
- uint32_t reg_offset = 2U;
- if (0 != (pin & GPT_IO_PIN_CREST))
- {
- /*
- * In TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3, if this is a crest duty cycle, then update the crest
- * duty cycle register. Otherwise, update the trough duty cycle register.
- */
- reg_offset = 4U;
- }
-
- if (0 != (pin & GPT_IO_PIN_GTIOCA_AND_GTIOCB))
- {
- p_instance_ctrl->p_reg->GTCCR[reg_offset] = duty_regs.gtccr_buffer;
- p_instance_ctrl->p_reg->GTCCR[reg_offset + 1] = duty_regs.gtccr_buffer;
- }
- else
- {
- p_instance_ctrl->p_reg->GTCCR[tmp_pin + reg_offset] = duty_regs.gtccr_buffer;
- }
- }
-
- if (GPT_IO_PIN_GTIOCB != tmp_pin)
- {
- /* GTIOCA or both GTIOCA and GTIOCB. */
- gtuddtyc &= ~R_GPT0_GTUDDTYC_OADTY_Msk;
- gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OADTY_Pos;
- }
-
- if ((GPT_IO_PIN_GTIOCA_AND_GTIOCB == pin) && duty_regs.omdty)
- {
- /* When setting both pins to 0%/100% duty recalculate OBDTY before setting */
- gpt_calculate_duty_cycle(p_instance_ctrl, duty_cycle_counts, &duty_regs, GPT_IO_PIN_GTIOCB);
- }
-
- if (GPT_IO_PIN_GTIOCA != tmp_pin)
- {
- /* GTIOCB or both GTIOCA and GTIOCB. */
- gtuddtyc &= ~R_GPT0_GTUDDTYC_OBDTY_Msk;
- gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OBDTY_Pos;
- }
-
- p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc;
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- return FSP_SUCCESS;
-#else
- FSP_PARAMETER_NOT_USED(p_ctrl);
- FSP_PARAMETER_NOT_USED(duty_cycle_counts);
- FSP_PARAMETER_NOT_USED(pin);
-
- FSP_RETURN(FSP_ERR_UNSUPPORTED);
-#endif
-}
-
-/*******************************************************************************************************************//**
- * Get timer information and store it in provided pointer p_info. Implements @ref timer_api_t::infoGet.
- *
- * Example:
- * @snippet r_gpt_example.c R_GPT_InfoGet
- *
- * @retval FSP_SUCCESS Period, count direction, frequency, and ELC event written to caller's
- * structure successfully.
- * @retval FSP_ERR_ASSERTION p_ctrl or p_info was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_InfoGet (timer_ctrl_t * const p_ctrl, timer_info_t * const p_info)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ASSERT(NULL != p_info);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Get and store period */
- uint32_t gtpr = p_instance_ctrl->p_reg->GTPR;
- uint32_t period_counts = gtpr + 1;
-#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
- if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
- {
- period_counts = gtpr;
- }
-#endif
- p_info->period_counts = period_counts;
-
- /* Get and store clock frequency */
- p_info->clock_frequency = gpt_clock_frequency_get(p_instance_ctrl);
-
- /* Get and store clock counting direction. Read count direction setting */
- p_info->count_direction = TIMER_DIRECTION_UP;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Get current timer status and store it in provided pointer p_status. Implements @ref timer_api_t::statusGet.
- *
- * Example:
- * @snippet r_gpt_example.c R_GPT_StatusGet
- *
- * @retval FSP_SUCCESS Current timer state and counter value set successfully.
- * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_StatusGet (timer_ctrl_t * const p_ctrl, timer_status_t * const p_status)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ASSERT(NULL != p_status);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Get counter state. */
- p_status->state = (timer_state_t) p_instance_ctrl->p_reg->GTCR_b.CST;
-
- /* Get counter value */
- p_status->counter = p_instance_ctrl->p_reg->GTCNT;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Set counter value.
- *
- * @note Do not call this API while the counter is counting. The counter value can only be updated while the counter
- * is stopped.
- *
- * @retval FSP_SUCCESS Counter value updated.
- * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- * @retval FSP_ERR_IN_USE The timer is running. Stop the timer before calling this function.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_CounterSet (timer_ctrl_t * const p_ctrl, uint32_t counter)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
- FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->GTCR_b.CST, FSP_ERR_IN_USE);
-#endif
-
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- /* Set counter value */
- p_instance_ctrl->p_reg->GTCNT = counter;
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Enable output for GTIOCA and/or GTIOCB.
- *
- * @retval FSP_SUCCESS Output is enabled.
- * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_OutputEnable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- uint32_t gtior = p_instance_ctrl->p_reg->GTIOR;
- if (GPT_IO_PIN_GTIOCB != pin)
- {
- /* GTIOCA or both GTIOCA and GTIOCB. */
- gtior |= R_GPT0_GTIOR_OAE_Msk;
- }
-
- if (GPT_IO_PIN_GTIOCA != pin)
- {
- /* GTIOCB or both GTIOCA and GTIOCB. */
- gtior |= R_GPT0_GTIOR_OBE_Msk;
- }
-
- p_instance_ctrl->p_reg->GTIOR = gtior;
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Disable output for GTIOCA and/or GTIOCB.
- *
- * @retval FSP_SUCCESS Output is disabled.
- * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_OutputDisable (timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- uint32_t gtior = p_instance_ctrl->p_reg->GTIOR;
- if (GPT_IO_PIN_GTIOCB != pin)
- {
- /* GTIOCA or both GTIOCA and GTIOCB. */
- gtior &= ~R_GPT0_GTIOR_OAE_Msk;
- }
-
- if (GPT_IO_PIN_GTIOCA != pin)
- {
- /* GTIOCB or both GTIOCA and GTIOCB. */
- gtior &= ~R_GPT0_GTIOR_OBE_Msk;
- }
-
- p_instance_ctrl->p_reg->GTIOR = gtior;
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Set A/D converter start request compare match value.
- *
- * @retval FSP_SUCCESS Counter value updated.
- * @retval FSP_ERR_ASSERTION p_ctrl or p_status was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_AdcTriggerSet (timer_ctrl_t * const p_ctrl,
- gpt_adc_compare_match_t which_compare_match,
- uint32_t compare_match_value)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- /* Set A/D converter start request compare match value. */
- volatile uint32_t * p_gtadtr = &p_instance_ctrl->p_reg->GTADTRA;
- p_gtadtr[which_compare_match] = compare_match_value;
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Set the Output Delay setting for the PWM output pin.
- *
- * @retval FSP_SUCCESS The output delay was set.
- * @retval FSP_ERR_ASSERTION An input parameter was invalid.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- * @retval FSP_ERR_INVALID_CHANNEL The channel does not support this feature.
- * @retval FSP_ERR_NOT_INITIALIZED The PWM Output Delay Circuit has not been initialized.
- * @retval FSP_ERR_INVALID_STATE The PWM Output Delay setting cannot be updated in the current state.
- * @retval FSP_ERR_UNSUPPORTED This feature is not supported on this MCU.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_PwmOutputDelaySet (timer_ctrl_t * const p_ctrl,
- gpt_pwm_output_delay_edge_t edge,
- gpt_pwm_output_delay_setting_t delay_setting,
- uint32_t const pin)
-{
-#if 0U != BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK && GPT_CFG_OUTPUT_SUPPORT_ENABLE
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
-
- #if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
- FSP_ERROR_RETURN(0U != (BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK & p_instance_ctrl->channel_mask),
- FSP_ERR_INVALID_CHANNEL);
- FSP_ERROR_RETURN(0U != (R_GPT_ODC->GTDLYCR1 & R_GPT_ODC_GTDLYCR1_DLLEN_Msk), FSP_ERR_NOT_INITIALIZED);
-
- if (TIMER_MODE_PWM == p_instance_ctrl->p_cfg->mode)
- {
- /* In Saw-wave mode, do not change the settings for the delay while the compare-match value is greater than or
- * equal to GTPR - 2. */
- uint32_t gtpr = p_instance_ctrl->p_reg->GTPR;
- uint32_t compare_match = p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC + pin];
- FSP_ERROR_RETURN(gtpr - 2 > compare_match, FSP_ERR_INVALID_STATE);
- }
- else
- {
- uint32_t compare_match;
- if (TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 == p_instance_ctrl->p_cfg->mode)
- {
- /* In TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3, the trough compare match value is set in
- * GTCCRD, and GTCCRF. */
- compare_match = p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRD + pin];
- }
- else
- {
- /* In TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM and TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM, the trough compare match value is
- * set in GTCCRC, and GTCCRE. */
- compare_match = p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC + pin];
- }
-
- timer_direction_t count_direction = (timer_direction_t) p_instance_ctrl->p_reg->GTST_b.TUCF;
-
- /* In Triangle-wave mode, do not change the settings for the delay while the counter if going down and the compare-match
- * value is less than or equal to 2. */
- FSP_ERROR_RETURN(TIMER_DIRECTION_DOWN != count_direction || 2 < compare_match, FSP_ERR_INVALID_STATE);
- }
- #endif
-
- FSP_CRITICAL_SECTION_DEFINE;
-
- if (GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS == delay_setting)
- {
- /* Enter a critical section in order to ensure that multiple GPT channels don't access the common
- * register simultaneously. */
- FSP_CRITICAL_SECTION_ENTER;
-
- #if GPT_CFG_WRITE_PROTECT_ENABLE
-
- /* GTDLYCR2 is protected by R_GPT::GTWP. */
- uint32_t wp = R_GPT0->GTWP;
- R_GPT0->GTWP = GPT_PRV_GTWP_RESET_VALUE;
- R_GPT0->GTWP;
- #endif
-
- /* Enable the Delay Generation Circuit bypass. */
- R_GPT_ODC->GTDLYCR2 &= (uint16_t) (~p_instance_ctrl->channel_mask & UINT16_MAX);
-
- #if GPT_CFG_WRITE_PROTECT_ENABLE
-
- /* Restore the previous value of GTWP. */
- R_GPT0->GTWP = wp | GPT_PRV_GTWP_RESET_VALUE;
- #endif
-
- FSP_CRITICAL_SECTION_EXIT;
- }
- else
- {
- /* Calculate the offset for the register than needs to be set. */
- uint32_t channel_offset = sizeof(uint32_t) * p_instance_ctrl->p_cfg->channel;
- uint32_t pin_offset =
- (uint32_t) ((uint32_t) &R_GPT_ODC->GTDLYR[0].B - (uint32_t) &R_GPT_ODC->GTDLYR[0].A) * pin;
- uint32_t edge_offset =
- (uint32_t) ((uint32_t) &R_GPT_ODC->GTDLYF[0].A - (uint32_t) &R_GPT_ODC->GTDLYR[0].A) * edge;
- uint16_t * p_gtdlyfnx =
- (uint16_t *) ((uint32_t) &R_GPT_ODC->GTDLYR[0].A + channel_offset + pin_offset + edge_offset);
-
- /* Unprotect the delay setting register. */
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- /* Write the delay setting to the register. */
- *p_gtdlyfnx = (uint16_t) delay_setting;
-
- /* Restore the previous value of GTWP. */
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- /* Check if the channel has already been enabled. */
- if (0U == (R_GPT_ODC->GTDLYCR2 & p_instance_ctrl->channel_mask))
- {
- /* Enter a critical section in order to ensure that multiple GPT channels don't access the common
- * register simultaneously. */
- FSP_CRITICAL_SECTION_ENTER;
-
- #if GPT_CFG_WRITE_PROTECT_ENABLE
-
- /* GTDLYCR2 is protected by R_GPT::GTWP. */
- wp = R_GPT0->GTWP;
- R_GPT0->GTWP = GPT_PRV_GTWP_RESET_VALUE;
- R_GPT0->GTWP;
- #endif
-
- /* Disable the Delay Generation Circuit bypass. */
- R_GPT_ODC->GTDLYCR2 |= (uint16_t) p_instance_ctrl->channel_mask;
-
- #if GPT_CFG_WRITE_PROTECT_ENABLE
-
- /* Restore the previous value of GTWP. */
- R_GPT0->GTWP = wp | GPT_PRV_GTWP_RESET_VALUE;
- #endif
-
- FSP_CRITICAL_SECTION_EXIT;
- }
- }
-
- return FSP_SUCCESS;
-#else
- FSP_PARAMETER_NOT_USED(p_ctrl);
- FSP_PARAMETER_NOT_USED(edge);
- FSP_PARAMETER_NOT_USED(delay_setting);
- FSP_PARAMETER_NOT_USED(pin);
-
- return FSP_ERR_UNSUPPORTED;
-#endif
-}
-
-/*******************************************************************************************************************//**
- * Updates the user callback with the option to provide memory for the callback argument structure.
- * Implements @ref timer_api_t::callbackSet.
- *
- * @retval FSP_SUCCESS Callback updated successfully.
- * @retval FSP_ERR_ASSERTION A required pointer is NULL.
- * @retval FSP_ERR_NOT_OPEN The control block has not been opened.
- * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_CallbackSet (timer_ctrl_t * const p_api_ctrl,
- void ( * p_callback)(timer_callback_args_t *),
- void const * const p_context,
- timer_callback_args_t * const p_callback_memory)
-{
- gpt_instance_ctrl_t * p_ctrl = (gpt_instance_ctrl_t *) p_api_ctrl;
-
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(p_ctrl);
- FSP_ASSERT(p_callback);
- FSP_ERROR_RETURN(GPT_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
-#if BSP_TZ_SECURE_BUILD
-
- /* Get security state of p_callback */
- bool callback_is_secure =
- (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE));
-
- #if GPT_CFG_PARAM_CHECKING_ENABLE
-
- /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */
- timer_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory,
- CMSE_AU_NONSECURE);
- FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY);
- #endif
-#endif
-
- /* Store callback and context */
-#if BSP_TZ_SECURE_BUILD
- p_ctrl->p_callback = callback_is_secure ? p_callback :
- (void (*)(timer_callback_args_t *))cmse_nsfptr_create(p_callback);
-#else
- p_ctrl->p_callback = p_callback;
-#endif
- p_ctrl->p_context = p_context;
- p_ctrl->p_callback_memory = p_callback_memory;
-
- return FSP_SUCCESS;
-}
-
-/*******************************************************************************************************************//**
- * Stops counter, disables output pins, and clears internal driver data. Implements @ref timer_api_t::close.
- *
- * @retval FSP_SUCCESS Successful close.
- * @retval FSP_ERR_ASSERTION p_ctrl was NULL.
- * @retval FSP_ERR_NOT_OPEN The instance is not opened.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_Close (timer_ctrl_t * const p_ctrl)
-{
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) p_ctrl;
- fsp_err_t err = FSP_SUCCESS;
-
-#if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ASSERT(NULL != p_instance_ctrl);
- FSP_ERROR_RETURN(GPT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
-#endif
-
- /* Disable interrupts. */
- gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_instance_ctrl->p_cfg->p_extend;
- r_gpt_disable_irq(p_instance_ctrl->p_cfg->cycle_end_irq);
- r_gpt_disable_irq(p_extend->capture_a_irq);
- r_gpt_disable_irq(p_extend->capture_b_irq);
-#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
- gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
- if (NULL != p_pwm_cfg)
- {
- r_gpt_disable_irq(p_pwm_cfg->trough_irq);
- }
-#endif
-
- /* Clear open flag. */
- p_instance_ctrl->open = 0U;
-
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- /* Stop counter. */
- p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
-
- /* Disable output. */
- p_instance_ctrl->p_reg->GTIOR = 0U;
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- return err;
-}
-
-/*******************************************************************************************************************//**
- * Initialize the PWM Delay Generation Circuit (PDG).
- * This function must be called before calling @ref R_GPT_PwmOutputDelaySet.
- *
- * @note This function will delay for 20 microseconds.
- *
- * @retval FSP_SUCCESS Initialization sequence completed successfully.
- * @retval FSP_ERR_INVALID_STATE The source clock frequnecy is out of the required range for the PDG.
- * @retval FSP_ERR_UNSUPPORTED This feature is not supported.
- **********************************************************************************************************************/
-fsp_err_t R_GPT_PwmOutputDelayInitialize ()
-{
-#if 0U != BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK && GPT_CFG_OUTPUT_SUPPORT_ENABLE
- #if BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN > 0 || GPT_CFG_PARAM_CHECKING_ENABLE
- #if BSP_FEATURE_BSP_HAS_GPT_CLOCK && BSP_CFG_GPT_CLOCK_BYPASS == 0
-
- /* Calculate the GPTCK Divider. */
- uint32_t divider = R_SYSTEM->GPTCKDIVCR;
-
- if (0U == divider)
- {
- divider = 1U;
- }
- else
- {
- divider *= 2U;
- }
-
- /* Calculate the GPTCK Frequency. */
- uint32_t gpt_frequency = R_BSP_SourceClockHzGet((fsp_priv_source_clock_t) R_SYSTEM->GPTCKCR_b.GPTCKSEL) / divider;
- #else
-
- /* Calculate the PCLKD Frequency. */
- uint32_t gpt_frequency = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD);
- #endif
- #endif
-
- #if GPT_CFG_PARAM_CHECKING_ENABLE
- FSP_ERROR_RETURN(BSP_FEATURE_GPT_ODC_FREQ_MAX >= gpt_frequency, FSP_ERR_INVALID_STATE);
- FSP_ERROR_RETURN(BSP_FEATURE_GPT_ODC_FREQ_MIN <= gpt_frequency, FSP_ERR_INVALID_STATE);
- #endif
-
- uint32_t gtdlycr1 = R_GPT_ODC_GTDLYCR1_DLYRST_Msk;
-
- #if BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN > 0
- if (BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN >= gpt_frequency)
- {
- gtdlycr1 |= R_GPT_ODC_GTDLYCR1_FRANGE_Msk;
- }
- #endif
-
- #if BSP_FEATURE_BSP_HAS_GPT_CLOCK && GPT_CFG_GPTCLK_BYPASS
-
- /* Bypass the GPTCLK. GPT instances will use PCLKD as the GPT Core clock. */
- R_GPT_GTCLK->GTCLKCR = 1U;
- #endif
-
- /* Cancel the module-stop state for the PDG. */
- R_BSP_MODULE_START(FSP_IP_GPT, 0);
-
- #if GPT_CFG_WRITE_PROTECT_ENABLE
-
- /* Disable write protection for GPT registers if they are protected. */
- R_GPT0->GTWP = GPT_PRV_GTWP_RESET_VALUE;
- R_GPT0->GTWP;
- #endif
-
- /* Reset the PWM Delay Generation Circuit. */
- R_GPT_ODC->GTDLYCR1 = (uint16_t) gtdlycr1;
- R_GPT_ODC->GTDLYCR2 = 0;
-
- /* Enable the DLL. */
- R_GPT_ODC->GTDLYCR1 = (uint16_t) (gtdlycr1 | R_GPT_ODC_GTDLYCR1_DLLEN_Msk);
-
- /* Wait for the DLL to be enabled. */
- R_BSP_SoftwareDelay(20, BSP_DELAY_UNITS_MICROSECONDS);
-
- /* Release the PWM Delay Generation Circuit from reset. */
- R_GPT_ODC->GTDLYCR1 &= (uint16_t) ~R_GPT_ODC_GTDLYCR1_DLYRST_Msk;
-
- #if GPT_CFG_WRITE_PROTECT_ENABLE
-
- /* Re-enable write protection for GPT registers. */
- R_GPT0->GTWP = GPT_PRV_GTWP_WRITE_PROTECT;
- #endif
-
- return FSP_SUCCESS;
-#else
-
- return FSP_ERR_UNSUPPORTED;
-#endif
-}
-
-/** @} (end addtogroup GPT) */
-
-/*******************************************************************************************************************//**
- * Private Functions
- **********************************************************************************************************************/
-
-/*******************************************************************************************************************//**
- * Enables write protection.
- *
- * @param[in] p_instance_ctrl Instance control block.
- * @param[in] write_protect_setting The value of GTWP prior to being cleared.
- **********************************************************************************************************************/
-static inline void r_gpt_write_protect_enable (gpt_instance_ctrl_t * const p_instance_ctrl,
- uint32_t write_protect_setting)
-{
-#if GPT_CFG_WRITE_PROTECT_ENABLE
- p_instance_ctrl->p_reg->GTWP = write_protect_setting;
-#else
- FSP_PARAMETER_NOT_USED(p_instance_ctrl);
- FSP_PARAMETER_NOT_USED(write_protect_setting);
-#endif
-}
-
-/*******************************************************************************************************************//**
- * Disables write protection.
- *
- * @param[in] p_instance_ctrl Instance control block.
- **********************************************************************************************************************/
-static inline uint32_t r_gpt_write_protect_disable (gpt_instance_ctrl_t * const p_instance_ctrl)
-{
-#if GPT_CFG_WRITE_PROTECT_ENABLE
- uint32_t write_protect_setting = p_instance_ctrl->p_reg->GTWP;
- p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_RESET_VALUE;
-
- return write_protect_setting;
-#else
- FSP_PARAMETER_NOT_USED(p_instance_ctrl);
-
- return 0U;
-#endif
-}
-
-/*******************************************************************************************************************//**
- * Initializes control structure based on configuration.
- *
- * @param[in] p_instance_ctrl Instance control block.
- * @param[in] p_cfg Pointer to timer configuration.
- **********************************************************************************************************************/
-static void gpt_common_open (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
-{
- /* Initialize control structure. */
- p_instance_ctrl->p_cfg = p_cfg;
-
- /* If callback is not null or timer mode is one shot, make sure the IRQ is enabled and store callback in the
- * control block.
- * @note The GPT hardware does not support one-shot mode natively. To support one-shot mode, the timer will be
- * stopped and cleared using software in the ISR. *//* Determine if this is a 32-bit or a 16-bit timer. */
- p_instance_ctrl->variant = TIMER_VARIANT_16_BIT;
- if (0U != (p_instance_ctrl->channel_mask & BSP_FEATURE_GPT_32BIT_CHANNEL_MASK))
- {
- p_instance_ctrl->variant = TIMER_VARIANT_32_BIT;
- }
-
- /* Save register base address. */
- uint32_t base_address = (uint32_t) R_GPT0 + (p_cfg->channel * ((uint32_t) R_GPT1 - (uint32_t) R_GPT0));
- p_instance_ctrl->p_reg = (R_GPT0_Type *) base_address;
-
- /* Set callback and context pointers, if configured */
- p_instance_ctrl->p_callback = p_cfg->p_callback;
- p_instance_ctrl->p_context = p_cfg->p_context;
- p_instance_ctrl->p_callback_memory = NULL;
-}
-
-/*******************************************************************************************************************//**
- * Performs hardware initialization of the GPT.
- *
- * @param[in] p_instance_ctrl Instance control block.
- * @param[in] p_cfg Pointer to timer configuration.
- **********************************************************************************************************************/
-static void gpt_hardware_initialize (gpt_instance_ctrl_t * const p_instance_ctrl, timer_cfg_t const * const p_cfg)
-{
- /* Save pointer to extended configuration structure. */
- gpt_extended_cfg_t * p_extend = (gpt_extended_cfg_t *) p_cfg->p_extend;
-
-#if BSP_FEATURE_BSP_HAS_GPT_CLOCK && GPT_CFG_GPTCLK_BYPASS
-
- /* Bypass the GPTCLK. GPT instances will use PCLKD as the GPT Core clock. */
- R_GPT_GTCLK->GTCLKCR = 1U;
-#endif
-
- /* Power on GPT before setting any hardware registers. Make sure the counter is stopped before setting mode
- * register, PCLK divisor register, and counter register. */
- R_BSP_MODULE_START(FSP_IP_GPT, p_cfg->channel);
-
-#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
- if (0U != (BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK & p_instance_ctrl->channel_mask))
- {
- /* Enter a critical section in order to ensure that multiple GPT channels don't access the common
- * register simultaneously. */
- FSP_CRITICAL_SECTION_DEFINE;
- FSP_CRITICAL_SECTION_ENTER;
-
- #if GPT_CFG_WRITE_PROTECT_ENABLE
-
- /* Disable write protection for GPT registers if they are protected. */
- uint32_t wp = R_GPT0->GTWP;
- R_GPT0->GTWP = GPT_PRV_GTWP_RESET_VALUE;
- R_GPT0->GTWP;
- #endif
-
- /* Enable the Delay Generation Circuit bypass. */
- R_GPT_ODC->GTDLYCR2 &= (uint16_t) (~p_instance_ctrl->channel_mask & UINT16_MAX);
-
- #if GPT_CFG_WRITE_PROTECT_ENABLE
- R_GPT0->GTWP = wp | GPT_PRV_GTWP_RESET_VALUE;
- #endif
-
- FSP_CRITICAL_SECTION_EXIT;
- }
-#endif
-
- /* Initialize all registers that may affect operation of this driver to reset values. Skip these since they
- * affect all channels, and are initialized in GTCR and GTCNT: GTSTR, GTSTP, GTCLR. GTCR is set immediately after
- * clearing the module stop bit to ensure the timer is stopped before proceeding with configuration. */
- p_instance_ctrl->p_reg->GTWP = GPT_PRV_GTWP_RESET_VALUE;
- p_instance_ctrl->p_reg->GTCR = 0U;
- p_instance_ctrl->p_reg->GTST = 0U;
- p_instance_ctrl->p_reg->GTCNT = 0U;
-
- /* GTPR, GTCCRn, GTIOR, GTSSR, GTPSR, GTCSR, GTUPSR, GTDNSR, GTPBR, and GTUDDTYC are set by this driver. */
-
- /* Initialization sets all register required for up counting as described in hardware manual (Figure 23.4 in the
- * RA6M3 manual R01UH0886EJ0100) and other registers required by the driver. */
-
- /* Dividers for GPT are half the enum value. */
- uint32_t gtcr_tpcs = p_cfg->source_div;
- uint32_t gtcr = gtcr_tpcs << R_GPT0_GTCR_TPCS_Pos;
-
- /* Store period register setting. The actual period and is one cycle longer than the register value for saw waves
- * and twice the register value for triangle waves. Reference section 23.2.21 "General PWM Timer Cycle Setting
- * Register (GTPR)". The setting passed to the configuration is expected to be half the desired period for
- * triangle waves. */
- uint32_t gtpr = p_cfg->period_counts - 1U;
-#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
-
- /* Saw-wave PWM mode is set in GTCR.MD for all modes except TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM and
- * TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM. */
- if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
- {
- gtcr |= ((uint32_t) p_cfg->mode << R_GPT0_GTCR_MD_Pos);
- gtpr = p_cfg->period_counts;
- }
-#endif
-
- /* Counter must be stopped to update TPCS. Reference section 23.2.12 "General PWM Timer Control Register (GTCR)"
- * in the RA6M3 manual R01UH0886EJ0100. */
- p_instance_ctrl->p_reg->GTCR = gtcr;
-
- gpt_hardware_events_disable(p_instance_ctrl);
-
- /* Configure the up/down count sources. These are not affected by enable/disable. */
- p_instance_ctrl->p_reg->GTUPSR = p_extend->count_up_source;
- p_instance_ctrl->p_reg->GTDNSR = p_extend->count_down_source;
-
- /* Set period. The actual period is one cycle longer than the register value. Reference section 23.2.21
- * "General PWM Timer Cycle Setting Register (GTPR)". */
- p_instance_ctrl->p_reg->GTPBR = gtpr;
- p_instance_ctrl->p_reg->GTPR = gtpr;
-
- uint32_t gtuddtyc = 0U;
- uint32_t gtior = p_extend->gtior_setting.gtior;
-
-#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
-
- /* For one shot mode, the compare match buffer register must be loaded with a value that exceeds the timer
- * cycle end value so that second compare match event would never occur and hence there will be only a
- * single pulse. Writing to the upper bits is ignored for 16-bit timers. */
- gpt_prv_duty_registers_t duty_regs = {UINT32_MAX, 0};
-
- if (TIMER_MODE_PERIODIC == p_cfg->mode)
- {
- /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. Reference
- * Figure 23.34 "Example setting for saw-wave PWM mode" in the RA6M3 manual R01UH0886EJ0100. To get a duty cycle
- * as close to 50% as possible, duty cycle (register) = (period (counts) / 2) - 1. */
- uint32_t duty_cycle_50_percent = (p_cfg->period_counts >> 1) - 1U;
- duty_regs.gtccr_buffer = duty_cycle_50_percent;
- }
-
- if (p_cfg->mode >= TIMER_MODE_PWM)
- {
- gpt_calculate_duty_cycle(p_instance_ctrl, p_cfg->duty_cycle_counts, &duty_regs, GPT_IO_PIN_GTIOCA);
- }
-
- /* Set the compare match and compare match buffer registers based on previously calculated values. */
- p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_regs.gtccr_buffer;
- p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRE] = duty_regs.gtccr_buffer;
-
- /* If the requested duty cycle is 0% or 100%, set this in the registers. */
- gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OADTY_Pos;
- gtuddtyc |= duty_regs.omdty << R_GPT0_GTUDDTYC_OBDTY_Pos;
-
- /* Check if custom GTIOR settings are provided. */
- if (0 == p_extend->gtior_setting.gtior)
- {
- /* If custom GTIOR settings are not provided, calculate GTIOR. */
- if (p_extend->gtioca.output_enabled)
- {
- uint32_t gtioca_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtioca.stop_level);
- gtior |= gtioca_gtior << R_GPT0_GTIOR_GTIOA_Pos;
- }
-
- if (p_extend->gtiocb.output_enabled)
- {
- uint32_t gtiocb_gtior = gpt_gtior_calculate(p_cfg, p_extend->gtiocb.stop_level);
- gtior |= gtiocb_gtior << R_GPT0_GTIOR_GTIOB_Pos;
- }
- }
-#endif
-
-#if GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK
- if ((1U << p_cfg->channel) & GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK)
- {
- /* This register is available on GPTE and GPTEH only. It must be cleared before setting. When modifying the
- * IVTT[2:0] bits, first set the IVTC[1:0] bits to 00b. Reference section 23.2.18 "General PWM Timer Interrupt
- * and A/D Converter Start Request Skipping Setting Register (GTITC)"" of the RA6M3 manual R01UH0886EJ0100. */
- p_instance_ctrl->p_reg->GTITC = 0U;
- }
-#endif
-
-#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
- gpt_extended_pwm_cfg_t const * p_pwm_cfg = p_extend->p_pwm_cfg;
- if (NULL != p_pwm_cfg)
- {
- p_instance_ctrl->p_reg->GTINTAD = ((uint32_t) p_pwm_cfg->output_disable << R_GPT0_GTINTAD_GRPDTE_Pos) |
- ((uint32_t) p_pwm_cfg->poeg_link << R_GPT0_GTINTAD_GRP_Pos) |
- ((uint32_t) p_pwm_cfg->adc_trigger << R_GPT0_GTINTAD_ADTRAUEN_Pos);
- p_instance_ctrl->p_reg->GTDVU = p_pwm_cfg->dead_time_count_up;
-
- /* Set GTDTCR.TDE only if one of the dead time values is non-zero. */
- uint32_t gtdtcr =
- ((p_pwm_cfg->dead_time_count_up > 0) || (p_pwm_cfg->dead_time_count_down > 0));
-
- #if GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK
- if ((1U << p_cfg->channel) & GPT_PRV_GPTE_OR_GPTEH_CHANNEL_MASK)
- {
- /* These registers are only available on GPTE and GPTEH. */
- p_instance_ctrl->p_reg->GTITC = ((uint32_t) p_pwm_cfg->interrupt_skip_source << R_GPT0_GTITC_IVTC_Pos) |
- ((uint32_t) p_pwm_cfg->interrupt_skip_count << R_GPT0_GTITC_IVTT_Pos) |
- ((uint32_t) p_pwm_cfg->interrupt_skip_adc << R_GPT0_GTITC_ADTAL_Pos);
- p_instance_ctrl->p_reg->GTDVD = p_pwm_cfg->dead_time_count_down;
- p_instance_ctrl->p_reg->GTADTRA = p_pwm_cfg->adc_a_compare_match;
- p_instance_ctrl->p_reg->GTADTRB = p_pwm_cfg->adc_b_compare_match;
- }
- #endif
-
- /* Check if custom GTIOR settings are provided. */
- if (0 == p_extend->gtior_setting.gtior)
- {
- /* If custom GTIOR settings are not provided, set gtioca_disable_settings and gtiocb_disable_settings. */
- gtior |= (uint32_t) (p_pwm_cfg->gtioca_disable_setting << R_GPT0_GTIOR_OADF_Pos);
- gtior |= (uint32_t) (p_pwm_cfg->gtiocb_disable_setting << R_GPT0_GTIOR_OBDF_Pos);
- }
-
- p_instance_ctrl->p_reg->GTDTCR = gtdtcr;
- }
- else
-#endif
- {
- /* GTADTR* registers are unused if GTINTAD is cleared. */
- p_instance_ctrl->p_reg->GTINTAD = 0U;
- p_instance_ctrl->p_reg->GTDTCR = 0U;
-
- /* GTDVU, GTDVD, GTDBU, GTDBD, and GTSOTR are not used if GTDTCR is cleared. */
- }
-
- /* Check if custom GTIOR settings are provided. */
- if (0 == p_extend->gtior_setting.gtior)
- {
- /*
- * If custom GTIOR settings are not provided, configure the noise filter for
- * the GTIOC pins.
- */
- gtior |= (uint32_t) (p_extend->capture_filter_gtioca << R_GPT0_GTIOR_NFAEN_Pos);
- gtior |= (uint32_t) (p_extend->capture_filter_gtiocb << R_GPT0_GTIOR_NFBEN_Pos);
- }
-
- /* Enable the compare match buffer. */
- p_instance_ctrl->p_reg->GTBER = GPT_PRV_GTBER_BUFFER_ENABLE_FORCE_TRANSFER;
-
-#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
- if (TIMER_MODE_ONE_SHOT == p_cfg->mode)
- {
- /* In one shot mode, the output pin toggles when counting starts, then again when the period expires.
- * The buffer is enabled to set the compare match to UINT32_MAX after the one shot pulse is output
- * so that the pin level will not change if the period expires again before the timer is stopped in
- * the interrupt.*/
- p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0U;
- p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0U;
- }
-#endif
-
- /* Reset counter to 0. */
- p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask;
-
- /* Set the I/O control register. */
- p_instance_ctrl->p_reg->GTIOR = gtior;
-
- /* Configure duty cycle and force timer to count up. GTUDDTYC must be set, then cleared to force the count
- * direction to be reflected when counting starts. Reference section 23.2.13 "General PWM Timer Count Direction
- * and Duty Setting Register (GTUDDTYC)" in the RA6M3 manual R01UH0886EJ0100. */
- p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 3U;
- p_instance_ctrl->p_reg->GTUDDTYC = gtuddtyc | 1U;
-
- r_gpt_write_protect_enable(p_instance_ctrl, GPT_PRV_GTWP_WRITE_PROTECT);
-
- /* Enable CPU interrupts if callback is not null. Also enable interrupts for one shot mode.
- * @note The GPT hardware does not support one-shot mode natively. To support one-shot mode, the timer will be
- * stopped and cleared using software in the ISR. */
- r_gpt_enable_irq(p_cfg->cycle_end_irq, p_cfg->cycle_end_ipl, p_instance_ctrl);
- r_gpt_enable_irq(p_extend->capture_a_irq, p_extend->capture_a_ipl, p_instance_ctrl);
- r_gpt_enable_irq(p_extend->capture_b_irq, p_extend->capture_b_ipl, p_instance_ctrl);
-#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
- if (NULL != p_pwm_cfg)
- {
- r_gpt_enable_irq(p_pwm_cfg->trough_irq, p_pwm_cfg->trough_ipl, p_instance_ctrl);
- }
-#endif
-}
-
-/*******************************************************************************************************************//**
- * Disables hardware events that would cause the timer to start, stop, clear, or capture.
- *
- * @param[in] p_instance_ctrl Instance control structure
- **********************************************************************************************************************/
-static void gpt_hardware_events_disable (gpt_instance_ctrl_t * p_instance_ctrl)
-{
- /* Enable use of GTSTR, GTSTP, and GTCLR for this channel. */
- p_instance_ctrl->p_reg->GTSSR = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
- p_instance_ctrl->p_reg->GTPSR = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
- p_instance_ctrl->p_reg->GTCSR = GPT_PRV_ENABLE_GROUP_SOFTWARE_UPDATE;
- p_instance_ctrl->p_reg->GTICASR = GPT_SOURCE_NONE;
- p_instance_ctrl->p_reg->GTICBSR = GPT_SOURCE_NONE;
-}
-
-/*******************************************************************************************************************//**
- * Disables interrupt if it is a valid vector number.
- *
- * @param[in] irq Interrupt number
- **********************************************************************************************************************/
-static void r_gpt_disable_irq (IRQn_Type irq)
-{
- /* Disable interrupts. */
- if (irq >= 0)
- {
- R_BSP_IrqDisable(irq);
- R_FSP_IsrContextSet(irq, NULL);
- }
-}
-
-/*******************************************************************************************************************//**
- * Configures and enables interrupt if it is a valid vector number.
- *
- * @param[in] irq Interrupt number
- * @param[in] priority NVIC priority of the interrupt
- * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
- **********************************************************************************************************************/
-static void r_gpt_enable_irq (IRQn_Type const irq, uint32_t priority, void * p_context)
-{
- if (irq >= 0)
- {
- R_BSP_IrqCfgEnable(irq, priority, p_context);
- }
-}
-
-#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
-
-/*******************************************************************************************************************//**
- * Calculates duty cycle register values. GTPR must be set before entering this function.
- *
- * @param[in] p_instance_ctrl Instance control structure
- * @param[in] duty_cycle_counts Duty cycle to set
- * @param[out] p_duty_reg Duty cycle register values
- **********************************************************************************************************************/
-static void gpt_calculate_duty_cycle (gpt_instance_ctrl_t * const p_instance_ctrl,
- uint32_t const duty_cycle_counts,
- gpt_prv_duty_registers_t * p_duty_reg,
- uint32_t pin)
-{
- /* Determine the current period. The actual period is one cycle longer than the register value for saw waves
- * and twice the register value for triangle waves. Reference section 23.2.21 "General PWM Timer Cycle Setting
- * Register (GTPR)". The setting passed to the configuration is expected to be half the desired duty cycle for
- * triangle waves. */
- uint32_t current_period = p_instance_ctrl->p_reg->GTPR;
- #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
- if (p_instance_ctrl->p_cfg->mode < TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
- #endif
- {
- current_period++;
- }
-
- bool duty_zero = (0U == duty_cycle_counts);
- bool duty_high = (duty_cycle_counts >= current_period);
-
- if (duty_zero || duty_high)
- {
- uint32_t gtior;
-
- if (!(GPT_IO_PIN_GTIOCB & pin))
- {
- gtior = p_instance_ctrl->p_reg->GTIOR_b.GTIOA;
- }
- else
- {
- gtior = p_instance_ctrl->p_reg->GTIOR_b.GTIOB;
- }
-
- bool first_level_low;
-
- if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
- {
- /* In triangle PWM modes use the initial pin level to determine 0%/100% setting. */
- first_level_low = !(gtior & 0x10);
- }
- else
- {
- /* In normal PWM mode use the cycle end setting to determine 0%/100% setting */
- first_level_low = (gtior & 0xC) == 0x4;
- }
-
- if ((duty_zero && !first_level_low) || (duty_high && first_level_low))
- {
- p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_0_PERCENT;
- }
- else
- {
- p_duty_reg->omdty = GPT_DUTY_CYCLE_MODE_100_PERCENT;
- }
- }
- else
- {
- uint32_t temp_duty_cycle = duty_cycle_counts;
-
- #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
- if (p_instance_ctrl->p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
- {
- p_duty_reg->gtccr_buffer = temp_duty_cycle;
- }
- else
- #endif
- {
- /* The GTIOCA/GTIOCB pins transition 1 cycle after compare match when buffer operation is used. Reference
- * Figure 23.34 "Example setting for saw-wave PWM mode" in the RA6M3 manual R01UH0886EJ0100. */
- temp_duty_cycle--;
- p_duty_reg->gtccr_buffer = temp_duty_cycle;
- }
- }
-}
-
-#endif
-
-/*******************************************************************************************************************//**
- * Calculates clock frequency of GPT counter. Divides GPT clock by GPT clock divisor.
- *
- * @param[in] p_instance_ctrl Instance control block
- *
- * @return Clock frequency of the GPT counter.
- **********************************************************************************************************************/
-static uint32_t gpt_clock_frequency_get (gpt_instance_ctrl_t * const p_instance_ctrl)
-{
- /* Look up PCLKD frequency and divide it by GPT PCLKD divider. */
- timer_source_div_t pclk_divisor = (timer_source_div_t) (p_instance_ctrl->p_reg->GTCR_b.TPCS);
- uint32_t pclk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD);
-
- return pclk_freq_hz >> pclk_divisor;
-}
-
-#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
-
-/*******************************************************************************************************************//**
- * Calculates GTIOR settings for given mode and stop level.
- *
- * @param[in] p_instance_ctrl Instance control block
- * @param[in] p_cfg Timer configuration
- * @param[in] level Output level after timer stops
- **********************************************************************************************************************/
-static uint32_t gpt_gtior_calculate (timer_cfg_t const * const p_cfg, gpt_pin_level_t const stop_level)
-{
- /* The stop level is used as both the initial level and the stop level. */
- uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t) stop_level << R_GPT0_GTIOR_OADFLT_Pos) |
- ((uint32_t) stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT);
-
- uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END;
-
- if (TIMER_MODE_PWM == p_cfg->mode)
- {
- /* Use default: GTIOn is high at cycle end, then low at compare match. */
- }
-
- #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
- else if (p_cfg->mode >= TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM)
- {
- gtion = GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH;
- }
- #endif
- else
- {
- /* In one-shot mode, the output pin goes high after the first compare match (one cycle after the timer starts counting). */
- if (GPT_PIN_LEVEL_LOW == stop_level)
- {
- gtion = GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END;
- }
- }
-
- gtior |= gtion;
-
- return gtior;
-}
-
-#endif
-
-/*******************************************************************************************************************//**
- * Calls user callback.
- *
- * @param[in] p_ctrl Pointer to GPT instance control block
- * @param[in] event Event code
- * @param[in] capture Event capture counts (if applicable)
- **********************************************************************************************************************/
-static void r_gpt_call_callback (gpt_instance_ctrl_t * p_ctrl, timer_event_t event, uint32_t capture)
-{
- timer_callback_args_t args;
-
- /* Store callback arguments in memory provided by user if available. This allows callback arguments to be
- * stored in non-secure memory so they can be accessed by a non-secure callback function. */
- timer_callback_args_t * p_args = p_ctrl->p_callback_memory;
- if (NULL == p_args)
- {
- /* Store on stack */
- p_args = &args;
- }
- else
- {
- /* Save current arguments on the stack in case this is a nested interrupt. */
- args = *p_args;
- }
-
- p_args->event = event;
- p_args->capture = capture;
- p_args->p_context = p_ctrl->p_context;
-
-#if BSP_TZ_SECURE_BUILD
-
- /* p_callback can point to a secure function or a non-secure function. */
- if (!cmse_is_nsfptr(p_ctrl->p_callback))
- {
- /* If p_callback is secure, then the project does not need to change security state. */
- p_ctrl->p_callback(p_args);
- }
- else
- {
- /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */
- gpt_prv_ns_callback p_callback = (gpt_prv_ns_callback) (p_ctrl->p_callback);
- p_callback(p_args);
- }
-
-#else
-
- /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */
- p_ctrl->p_callback(p_args);
-#endif
-
- if (NULL != p_ctrl->p_callback_memory)
- {
- /* Restore callback memory in case this is a nested interrupt. */
- *p_ctrl->p_callback_memory = args;
- }
-}
-
-/*******************************************************************************************************************//**
- * Common processing for input capture interrupt.
- *
- * @param[in] event Which input capture event occurred
- **********************************************************************************************************************/
-static void r_gpt_capture_common_isr (gpt_prv_capture_event_t event)
-{
- /* Save context if RTOS is used */
- FSP_CONTEXT_SAVE
-
- IRQn_Type irq = R_FSP_CurrentIrqGet();
-
- /* Clear pending IRQ to make sure it doesn't fire again after exiting */
- R_BSP_IrqStatusClear(irq);
-
- /* Recover ISR context saved in open. */
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
- /* Get captured value. */
- uint32_t counter = p_instance_ctrl->p_reg->GTCCR[event];
-
- /* If we captured a one-shot pulse, then disable future captures. */
- if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
- {
- /* Disable captures. */
- gpt_hardware_events_disable(p_instance_ctrl);
-
- /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
- R_BSP_IrqClearPending(irq);
- }
-
- /* If a callback is provided, then call it with the captured counter value. */
- if (NULL != p_instance_ctrl->p_callback)
- {
- r_gpt_call_callback(p_instance_ctrl,
- (timer_event_t) ((uint32_t) TIMER_EVENT_CAPTURE_A + (uint32_t) event),
- counter);
- }
-
- /* Restore context if RTOS is used */
- FSP_CONTEXT_RESTORE
-}
-
-/*******************************************************************************************************************//**
- * Stops the timer if one-shot mode, clears interrupts, and calls callback if one was provided in the open function.
- **********************************************************************************************************************/
-void gpt_counter_overflow_isr (void)
-{
- /* Save context if RTOS is used */
- FSP_CONTEXT_SAVE;
-
- IRQn_Type irq = R_FSP_CurrentIrqGet();
-
- /* Clear pending IRQ to make sure it doesn't fire again after exiting */
- R_BSP_IrqStatusClear(irq);
-
- /* Recover ISR context saved in open. */
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
- /* If one-shot mode is selected, stop the timer since period has expired. */
- if (TIMER_MODE_ONE_SHOT == p_instance_ctrl->p_cfg->mode)
- {
- uint32_t wp = r_gpt_write_protect_disable(p_instance_ctrl);
-
- p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask;
-
- /* Clear the GPT counter and the overflow flag after the one shot pulse has being generated */
- p_instance_ctrl->p_reg->GTCNT = 0;
- p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRA] = 0;
- p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRB] = 0;
-
- r_gpt_write_protect_enable(p_instance_ctrl, wp | GPT_PRV_GTWP_RESET_VALUE);
-
- /* Clear pending interrupt to make sure it doesn't fire again if another overflow has already occurred. */
- R_BSP_IrqClearPending(irq);
- }
-
- if (NULL != p_instance_ctrl->p_callback)
- {
- r_gpt_call_callback(p_instance_ctrl, TIMER_EVENT_CYCLE_END, 0);
- }
-
- /* Restore context if RTOS is used */
- FSP_CONTEXT_RESTORE;
-}
-
-#if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
-
-/*******************************************************************************************************************//**
- * Only supported for asymmetric triangle-wave PWM. Notifies application of trough event.
- **********************************************************************************************************************/
-void gpt_counter_underflow_isr (void)
-{
- /* Save context if RTOS is used */
- FSP_CONTEXT_SAVE;
-
- IRQn_Type irq = R_FSP_CurrentIrqGet();
-
- /* Clear pending IRQ to make sure it doesn't fire again after exiting */
- R_BSP_IrqStatusClear(irq);
-
- /* Recover ISR context saved in open. */
- gpt_instance_ctrl_t * p_instance_ctrl = (gpt_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
-
- /* Call user callback. */
- r_gpt_call_callback(p_instance_ctrl, TIMER_EVENT_TROUGH, 0);
-
- /* Restore context if RTOS is used */
- FSP_CONTEXT_RESTORE;
-}
-
-#endif
-
-/*******************************************************************************************************************//**
- * Interrupt triggered by a capture A source.
- *
- * Clears interrupt, disables captures if one-shot mode, and calls callback if one was provided in the open function.
- **********************************************************************************************************************/
-void gpt_capture_a_isr (void)
-{
- r_gpt_capture_common_isr(GPT_PRV_CAPTURE_EVENT_A);
-}
-
-/*******************************************************************************************************************//**
- * Interrupt triggered by a capture B source.
- *
- * Clears interrupt, disables captures if one-shot mode, and calls callback if one was provided in the open function.
- **********************************************************************************************************************/
-void gpt_capture_b_isr (void)
-{
- r_gpt_capture_common_isr(GPT_PRV_CAPTURE_EVENT_B);
-}
diff --git a/bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_adc_cfg.h b/bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_adc_cfg.h
deleted file mode 100644
index 9c59889ca8..0000000000
--- a/bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_adc_cfg.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_ADC_CFG_H_
-#define R_ADC_CFG_H_
-#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-#endif /* R_ADC_CFG_H_ */
diff --git a/bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_gpt_cfg.h b/bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_gpt_cfg.h
deleted file mode 100644
index fd876266d3..0000000000
--- a/bsp/renesas/ra6m3-hmi-board/ra_cfg/fsp_cfg/r_gpt_cfg.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_GPT_CFG_H_
-#define R_GPT_CFG_H_
-#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (1)
-#define GPT_CFG_WRITE_PROTECT_ENABLE (0)
-#define GPT_CFG_GPTCLK_BYPASS 1
-#endif /* R_GPT_CFG_H_ */
diff --git a/bsp/renesas/ra6m3-hmi-board/ra_gen/hal_data.c b/bsp/renesas/ra6m3-hmi-board/ra_gen/hal_data.c
index 1e3a11e13e..cdcffb3b68 100644
--- a/bsp/renesas/ra6m3-hmi-board/ra_gen/hal_data.c
+++ b/bsp/renesas/ra6m3-hmi-board/ra_gen/hal_data.c
@@ -1,487 +1,5 @@
/* generated HAL source file - do not edit */
#include "hal_data.h"
-
-/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
-#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC
-#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC
-#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC
-#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC
-gpt_instance_ctrl_t g_timer8_ctrl;
-#if 0
-const gpt_extended_pwm_cfg_t g_timer8_pwm_extend =
-{
- .trough_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_GPT8_COUNTER_UNDERFLOW)
- .trough_irq = VECTOR_NUMBER_GPT8_COUNTER_UNDERFLOW,
-#else
- .trough_irq = FSP_INVALID_VECTOR,
-#endif
- .poeg_link = GPT_POEG_LINK_POEG0,
- .output_disable = GPT_OUTPUT_DISABLE_NONE,
- .adc_trigger = GPT_ADC_TRIGGER_NONE,
- .dead_time_count_up = 0,
- .dead_time_count_down = 0,
- .adc_a_compare_match = 0,
- .adc_b_compare_match = 0,
- .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE,
- .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0,
- .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE,
- .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
- .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
-};
-#endif
-const gpt_extended_cfg_t g_timer8_extend =
-{
- .gtioca = { .output_enabled = true,
- .stop_level = GPT_PIN_LEVEL_LOW
- },
- .gtiocb = { .output_enabled = true,
- .stop_level = GPT_PIN_LEVEL_LOW
- },
- .start_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .capture_a_ipl = (BSP_IRQ_DISABLED),
- .capture_b_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_GPT8_CAPTURE_COMPARE_A)
- .capture_a_irq = VECTOR_NUMBER_GPT8_CAPTURE_COMPARE_A,
-#else
- .capture_a_irq = FSP_INVALID_VECTOR,
-#endif
-#if defined(VECTOR_NUMBER_GPT8_CAPTURE_COMPARE_B)
- .capture_b_irq = VECTOR_NUMBER_GPT8_CAPTURE_COMPARE_B,
-#else
- .capture_b_irq = FSP_INVALID_VECTOR,
-#endif
- .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE,
- .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE,
-#if 0
- .p_pwm_cfg = &g_timer8_pwm_extend,
-#else
- .p_pwm_cfg = NULL,
-#endif
-#if 0
- .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U),
- .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW,
- .gtior_setting.gtior_b.oahld = 0U,
- .gtior_setting.gtior_b.oae = (uint32_t) true,
- .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
- .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
- .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
- .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U),
- .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW,
- .gtior_setting.gtior_b.obhld = 0U,
- .gtior_setting.gtior_b.obe = (uint32_t) true,
- .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
- .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
- .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
-#else
- .gtior_setting.gtior = 0U,
-#endif
-};
-const timer_cfg_t g_timer8_cfg =
-{
- .mode = TIMER_MODE_PWM,
- /* Actual period: 35.791394133333334 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = (timer_source_div_t)0,
- .channel = 8,
- .p_callback = NULL,
- /** If NULL then do not add & */
-#if defined(NULL)
- .p_context = NULL,
-#else
- .p_context = &NULL,
-#endif
- .p_extend = &g_timer8_extend,
- .cycle_end_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_GPT8_COUNTER_OVERFLOW)
- .cycle_end_irq = VECTOR_NUMBER_GPT8_COUNTER_OVERFLOW,
-#else
- .cycle_end_irq = FSP_INVALID_VECTOR,
-#endif
-};
-/* Instance structure to use this module. */
-const timer_instance_t g_timer8 =
-{
- .p_ctrl = &g_timer8_ctrl,
- .p_cfg = &g_timer8_cfg,
- .p_api = &g_timer_on_gpt
-};
-gpt_instance_ctrl_t g_timer0_ctrl;
-#if 0
-const gpt_extended_pwm_cfg_t g_timer0_pwm_extend =
-{
- .trough_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW)
- .trough_irq = VECTOR_NUMBER_GPT0_COUNTER_UNDERFLOW,
-#else
- .trough_irq = FSP_INVALID_VECTOR,
-#endif
- .poeg_link = GPT_POEG_LINK_POEG0,
- .output_disable = GPT_OUTPUT_DISABLE_NONE,
- .adc_trigger = GPT_ADC_TRIGGER_NONE,
- .dead_time_count_up = 0,
- .dead_time_count_down = 0,
- .adc_a_compare_match = 0,
- .adc_b_compare_match = 0,
- .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE,
- .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0,
- .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE,
- .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
- .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
-};
-#endif
-const gpt_extended_cfg_t g_timer0_extend =
-{
- .gtioca = { .output_enabled = true,
- .stop_level = GPT_PIN_LEVEL_LOW
- },
- .gtiocb = { .output_enabled = false,
- .stop_level = GPT_PIN_LEVEL_LOW
- },
- .start_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .capture_a_ipl = (BSP_IRQ_DISABLED),
- .capture_b_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A)
- .capture_a_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_A,
-#else
- .capture_a_irq = FSP_INVALID_VECTOR,
-#endif
-#if defined(VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B)
- .capture_b_irq = VECTOR_NUMBER_GPT0_CAPTURE_COMPARE_B,
-#else
- .capture_b_irq = FSP_INVALID_VECTOR,
-#endif
- .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE,
- .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE,
-#if 0
- .p_pwm_cfg = &g_timer0_pwm_extend,
-#else
- .p_pwm_cfg = NULL,
-#endif
-#if 0
- .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U),
- .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW,
- .gtior_setting.gtior_b.oahld = 0U,
- .gtior_setting.gtior_b.oae = (uint32_t) true,
- .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
- .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
- .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
- .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U),
- .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW,
- .gtior_setting.gtior_b.obhld = 0U,
- .gtior_setting.gtior_b.obe = (uint32_t) false,
- .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
- .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
- .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
-#else
- .gtior_setting.gtior = 0U,
-#endif
-};
-const timer_cfg_t g_timer0_cfg =
-{
- .mode = TIMER_MODE_PWM,
- /* Actual period: 35.791394133333334 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = (timer_source_div_t)0,
- .channel = 0,
- .p_callback = NULL,
- /** If NULL then do not add & */
-#if defined(NULL)
- .p_context = NULL,
-#else
- .p_context = &NULL,
-#endif
- .p_extend = &g_timer0_extend,
- .cycle_end_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW)
- .cycle_end_irq = VECTOR_NUMBER_GPT0_COUNTER_OVERFLOW,
-#else
- .cycle_end_irq = FSP_INVALID_VECTOR,
-#endif
-};
-/* Instance structure to use this module. */
-const timer_instance_t g_timer0 =
-{
- .p_ctrl = &g_timer0_ctrl,
- .p_cfg = &g_timer0_cfg,
- .p_api = &g_timer_on_gpt
-};
-gpt_instance_ctrl_t g_timer2_ctrl;
-#if 0
-const gpt_extended_pwm_cfg_t g_timer2_pwm_extend =
-{
- .trough_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW)
- .trough_irq = VECTOR_NUMBER_GPT2_COUNTER_UNDERFLOW,
-#else
- .trough_irq = FSP_INVALID_VECTOR,
-#endif
- .poeg_link = GPT_POEG_LINK_POEG0,
- .output_disable = GPT_OUTPUT_DISABLE_NONE,
- .adc_trigger = GPT_ADC_TRIGGER_NONE,
- .dead_time_count_up = 0,
- .dead_time_count_down = 0,
- .adc_a_compare_match = 0,
- .adc_b_compare_match = 0,
- .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE,
- .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0,
- .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE,
- .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
- .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED,
-};
-#endif
-const gpt_extended_cfg_t g_timer2_extend =
-{
- .gtioca = { .output_enabled = false,
- .stop_level = GPT_PIN_LEVEL_LOW
- },
- .gtiocb = { .output_enabled = true,
- .stop_level = GPT_PIN_LEVEL_LOW
- },
- .start_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE),
- .capture_a_ipl = (BSP_IRQ_DISABLED),
- .capture_b_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A)
- .capture_a_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_A,
-#else
- .capture_a_irq = FSP_INVALID_VECTOR,
-#endif
-#if defined(VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B)
- .capture_b_irq = VECTOR_NUMBER_GPT2_CAPTURE_COMPARE_B,
-#else
- .capture_b_irq = FSP_INVALID_VECTOR,
-#endif
- .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE,
- .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE,
-#if 0
- .p_pwm_cfg = &g_timer2_pwm_extend,
-#else
- .p_pwm_cfg = NULL,
-#endif
-#if 0
- .gtior_setting.gtior_b.gtioa = (0U << 4U) | (0U << 2U) | (0U << 0U),
- .gtior_setting.gtior_b.oadflt = (uint32_t) GPT_PIN_LEVEL_LOW,
- .gtior_setting.gtior_b.oahld = 0U,
- .gtior_setting.gtior_b.oae = (uint32_t) false,
- .gtior_setting.gtior_b.oadf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
- .gtior_setting.gtior_b.nfaen = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
- .gtior_setting.gtior_b.nfcsa = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
- .gtior_setting.gtior_b.gtiob = (0U << 4U) | (0U << 2U) | (0U << 0U),
- .gtior_setting.gtior_b.obdflt = (uint32_t) GPT_PIN_LEVEL_LOW,
- .gtior_setting.gtior_b.obhld = 0U,
- .gtior_setting.gtior_b.obe = (uint32_t) true,
- .gtior_setting.gtior_b.obdf = (uint32_t) GPT_GTIOC_DISABLE_PROHIBITED,
- .gtior_setting.gtior_b.nfben = ((uint32_t) GPT_CAPTURE_FILTER_NONE & 1U),
- .gtior_setting.gtior_b.nfcsb = ((uint32_t) GPT_CAPTURE_FILTER_NONE >> 1U),
-#else
- .gtior_setting.gtior = 0U,
-#endif
-};
-const timer_cfg_t g_timer2_cfg =
-{
- .mode = TIMER_MODE_PWM,
- /* Actual period: 35.791394133333334 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = (timer_source_div_t)0,
- .channel = 2,
- .p_callback = NULL,
- /** If NULL then do not add & */
-#if defined(NULL)
- .p_context = NULL,
-#else
- .p_context = &NULL,
-#endif
- .p_extend = &g_timer2_extend,
- .cycle_end_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW)
- .cycle_end_irq = VECTOR_NUMBER_GPT2_COUNTER_OVERFLOW,
-#else
- .cycle_end_irq = FSP_INVALID_VECTOR,
-#endif
-};
-/* Instance structure to use this module. */
-const timer_instance_t g_timer2 =
-{
- .p_ctrl = &g_timer2_ctrl,
- .p_cfg = &g_timer2_cfg,
- .p_api = &g_timer_on_gpt
-};
-sci_uart_instance_ctrl_t g_uart4_ctrl;
-
- baud_setting_t g_uart4_baud_setting =
- {
- /* Baud rate calculated with 0.160% error. */ .abcse = 0, .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t) 256, .brme = false
- };
-
- /** UART extended configuration for UARTonSCI HAL driver */
- const sci_uart_extended_cfg_t g_uart4_cfg_extend =
- {
- .clock = SCI_UART_CLOCK_INT,
- .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,
- .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE,
- .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,
- .p_baud_setting = &g_uart4_baud_setting,
- .flow_control = SCI_UART_FLOW_CONTROL_RTS,
- #if 0xFF != 0xFF
- .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
- #else
- .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX,
- #endif
- };
-
- /** UART interface configuration */
- const uart_cfg_t g_uart4_cfg =
- {
- .channel = 4,
- .data_bits = UART_DATA_BITS_8,
- .parity = UART_PARITY_OFF,
- .stop_bits = UART_STOP_BITS_1,
- .p_callback = user_uart4_callback,
- .p_context = NULL,
- .p_extend = &g_uart4_cfg_extend,
-#define RA_NOT_DEFINED (1)
-#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
- .p_transfer_tx = NULL,
-#else
- .p_transfer_tx = &RA_NOT_DEFINED,
-#endif
-#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
- .p_transfer_rx = NULL,
-#else
- .p_transfer_rx = &RA_NOT_DEFINED,
-#endif
-#undef RA_NOT_DEFINED
- .rxi_ipl = (12),
- .txi_ipl = (12),
- .tei_ipl = (12),
- .eri_ipl = (12),
-#if defined(VECTOR_NUMBER_SCI4_RXI)
- .rxi_irq = VECTOR_NUMBER_SCI4_RXI,
-#else
- .rxi_irq = FSP_INVALID_VECTOR,
-#endif
-#if defined(VECTOR_NUMBER_SCI4_TXI)
- .txi_irq = VECTOR_NUMBER_SCI4_TXI,
-#else
- .txi_irq = FSP_INVALID_VECTOR,
-#endif
-#if defined(VECTOR_NUMBER_SCI4_TEI)
- .tei_irq = VECTOR_NUMBER_SCI4_TEI,
-#else
- .tei_irq = FSP_INVALID_VECTOR,
-#endif
-#if defined(VECTOR_NUMBER_SCI4_ERI)
- .eri_irq = VECTOR_NUMBER_SCI4_ERI,
-#else
- .eri_irq = FSP_INVALID_VECTOR,
-#endif
- };
-
-/* Instance structure to use this module. */
-const uart_instance_t g_uart4 =
-{
- .p_ctrl = &g_uart4_ctrl,
- .p_cfg = &g_uart4_cfg,
- .p_api = &g_uart_on_sci
-};
-adc_instance_ctrl_t g_adc0_ctrl;
-const adc_extended_cfg_t g_adc0_cfg_extend =
-{
- .add_average_count = ADC_ADD_OFF,
- .clearing = ADC_CLEAR_AFTER_READ_ON,
- .trigger_group_b = ADC_TRIGGER_SYNC_ELC,
- .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
- .adc_vref_control = ADC_VREF_CONTROL_VREFH,
- .enable_adbuf = 0,
-#if defined(VECTOR_NUMBER_ADC0_WINDOW_A)
- .window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A,
-#else
- .window_a_irq = FSP_INVALID_VECTOR,
-#endif
- .window_a_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_ADC0_WINDOW_B)
- .window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B,
-#else
- .window_b_irq = FSP_INVALID_VECTOR,
-#endif
- .window_b_ipl = (BSP_IRQ_DISABLED),
-};
-const adc_cfg_t g_adc0_cfg =
-{
- .unit = 0,
- .mode = ADC_MODE_CONTINUOUS_SCAN,
- .resolution = ADC_RESOLUTION_12_BIT,
- .alignment = (adc_alignment_t) ADC_ALIGNMENT_RIGHT,
- .trigger = ADC_TRIGGER_SOFTWARE,
- .p_callback = NULL,
- /** If NULL then do not add & */
-#if defined(NULL)
- .p_context = NULL,
-#else
- .p_context = &NULL,
-#endif
- .p_extend = &g_adc0_cfg_extend,
-#if defined(VECTOR_NUMBER_ADC0_SCAN_END)
- .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
-#else
- .scan_end_irq = FSP_INVALID_VECTOR,
-#endif
- .scan_end_ipl = (BSP_IRQ_DISABLED),
-#if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
- .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
-#else
- .scan_end_b_irq = FSP_INVALID_VECTOR,
-#endif
- .scan_end_b_ipl = (BSP_IRQ_DISABLED),
-};
-#if ((0) | (0))
-const adc_window_cfg_t g_adc0_window_cfg =
-{
- .compare_mask = 0,
- .compare_mode_mask = 0,
- .compare_cfg = (0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR),
- .compare_ref_low = 0,
- .compare_ref_high = 0,
- .compare_b_channel = (ADC_WINDOW_B_CHANNEL_0),
- .compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE),
- .compare_b_ref_low = 0,
- .compare_b_ref_high = 0,
-};
-#endif
-const adc_channel_cfg_t g_adc0_channel_cfg =
-{
- .scan_mask = ADC_MASK_CHANNEL_0 | ADC_MASK_CHANNEL_1 | ADC_MASK_CHANNEL_2 | ADC_MASK_CHANNEL_3 | ADC_MASK_CHANNEL_5 | ADC_MASK_CHANNEL_7 | ADC_MASK_CHANNEL_20 | 0,
- .scan_mask_group_b = 0,
- .priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
- .add_mask = 0,
- .sample_hold_mask = 0,
- .sample_hold_states = 24,
-#if ((0) | (0))
- .p_window_cfg = (adc_window_cfg_t *) &g_adc0_window_cfg,
-#else
- .p_window_cfg = NULL,
-#endif
-};
-/* Instance structure to use this module. */
-const adc_instance_t g_adc0 =
-{
- .p_ctrl = &g_adc0_ctrl,
- .p_cfg = &g_adc0_cfg,
- .p_channel_cfg = &g_adc0_channel_cfg,
- .p_api = &g_adc_on_adc
-};
sci_uart_instance_ctrl_t g_uart9_ctrl;
baud_setting_t g_uart9_baud_setting =
diff --git a/bsp/renesas/ra6m3-hmi-board/ra_gen/hal_data.h b/bsp/renesas/ra6m3-hmi-board/ra_gen/hal_data.h
index c5e48699b0..7e3e2152a5 100644
--- a/bsp/renesas/ra6m3-hmi-board/ra_gen/hal_data.h
+++ b/bsp/renesas/ra6m3-hmi-board/ra_gen/hal_data.h
@@ -4,69 +4,9 @@
#include
#include "bsp_api.h"
#include "common_data.h"
-#include "r_gpt.h"
-#include "r_timer_api.h"
#include "r_sci_uart.h"
#include "r_uart_api.h"
-#include "r_adc.h"
-#include "r_adc_api.h"
FSP_HEADER
-/** Timer on GPT Instance. */
-extern const timer_instance_t g_timer8;
-
-/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */
-extern gpt_instance_ctrl_t g_timer8_ctrl;
-extern const timer_cfg_t g_timer8_cfg;
-
-#ifndef NULL
-void NULL(timer_callback_args_t * p_args);
-#endif
-/** Timer on GPT Instance. */
-extern const timer_instance_t g_timer0;
-
-/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */
-extern gpt_instance_ctrl_t g_timer0_ctrl;
-extern const timer_cfg_t g_timer0_cfg;
-
-#ifndef NULL
-void NULL(timer_callback_args_t * p_args);
-#endif
-/** Timer on GPT Instance. */
-extern const timer_instance_t g_timer2;
-
-/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */
-extern gpt_instance_ctrl_t g_timer2_ctrl;
-extern const timer_cfg_t g_timer2_cfg;
-
-#ifndef NULL
-void NULL(timer_callback_args_t * p_args);
-#endif
-/** UART on SCI Instance. */
- extern const uart_instance_t g_uart4;
-
- /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
- extern sci_uart_instance_ctrl_t g_uart4_ctrl;
- extern const uart_cfg_t g_uart4_cfg;
- extern const sci_uart_extended_cfg_t g_uart4_cfg_extend;
-
- #ifndef user_uart4_callback
- void user_uart4_callback(uart_callback_args_t * p_args);
- #endif
-/** ADC on ADC Instance. */
-extern const adc_instance_t g_adc0;
-
-/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
-extern adc_instance_ctrl_t g_adc0_ctrl;
-extern const adc_cfg_t g_adc0_cfg;
-extern const adc_channel_cfg_t g_adc0_channel_cfg;
-
-#ifndef NULL
-void NULL(adc_callback_args_t * p_args);
-#endif
-
-#ifndef NULL
-#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 7
-#endif
/** UART on SCI Instance. */
extern const uart_instance_t g_uart9;
diff --git a/bsp/renesas/ra6m3-hmi-board/ra_gen/vector_data.c b/bsp/renesas/ra6m3-hmi-board/ra_gen/vector_data.c
index 28065e8415..1bddd01208 100644
--- a/bsp/renesas/ra6m3-hmi-board/ra_gen/vector_data.c
+++ b/bsp/renesas/ra6m3-hmi-board/ra_gen/vector_data.c
@@ -8,10 +8,6 @@
[1] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */
[2] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
[3] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
- [4] = sci_uart_rxi_isr, /* SCI4 RXI (Received data full) */
- [5] = sci_uart_txi_isr, /* SCI4 TXI (Transmit data empty) */
- [6] = sci_uart_tei_isr, /* SCI4 TEI (Transmit end) */
- [7] = sci_uart_eri_isr, /* SCI4 ERI (Receive error) */
};
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
{
@@ -19,9 +15,5 @@
[1] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */
[2] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */
[3] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */
- [4] = BSP_PRV_IELS_ENUM(EVENT_SCI4_RXI), /* SCI4 RXI (Received data full) */
- [5] = BSP_PRV_IELS_ENUM(EVENT_SCI4_TXI), /* SCI4 TXI (Transmit data empty) */
- [6] = BSP_PRV_IELS_ENUM(EVENT_SCI4_TEI), /* SCI4 TEI (Transmit end) */
- [7] = BSP_PRV_IELS_ENUM(EVENT_SCI4_ERI), /* SCI4 ERI (Receive error) */
};
#endif
\ No newline at end of file
diff --git a/bsp/renesas/ra6m3-hmi-board/ra_gen/vector_data.h b/bsp/renesas/ra6m3-hmi-board/ra_gen/vector_data.h
index bd5655b853..d1ae7d9cbd 100644
--- a/bsp/renesas/ra6m3-hmi-board/ra_gen/vector_data.h
+++ b/bsp/renesas/ra6m3-hmi-board/ra_gen/vector_data.h
@@ -3,7 +3,7 @@
#define VECTOR_DATA_H
/* Number of interrupts allocated */
#ifndef VECTOR_DATA_IRQ_COUNT
- #define VECTOR_DATA_IRQ_COUNT (8)
+ #define VECTOR_DATA_IRQ_COUNT (4)
#endif
/* ISR prototypes */
void sci_uart_rxi_isr(void);
@@ -20,12 +20,4 @@
#define SCI9_TEI_IRQn ((IRQn_Type) 2) /* SCI9 TEI (Transmit end) */
#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type) 3) /* SCI9 ERI (Receive error) */
#define SCI9_ERI_IRQn ((IRQn_Type) 3) /* SCI9 ERI (Receive error) */
- #define VECTOR_NUMBER_SCI4_RXI ((IRQn_Type) 4) /* SCI4 RXI (Received data full) */
- #define SCI4_RXI_IRQn ((IRQn_Type) 4) /* SCI4 RXI (Received data full) */
- #define VECTOR_NUMBER_SCI4_TXI ((IRQn_Type) 5) /* SCI4 TXI (Transmit data empty) */
- #define SCI4_TXI_IRQn ((IRQn_Type) 5) /* SCI4 TXI (Transmit data empty) */
- #define VECTOR_NUMBER_SCI4_TEI ((IRQn_Type) 6) /* SCI4 TEI (Transmit end) */
- #define SCI4_TEI_IRQn ((IRQn_Type) 6) /* SCI4 TEI (Transmit end) */
- #define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type) 7) /* SCI4 ERI (Receive error) */
- #define SCI4_ERI_IRQn ((IRQn_Type) 7) /* SCI4 ERI (Receive error) */
#endif /* VECTOR_DATA_H */
\ No newline at end of file
diff --git a/bsp/renesas/ra6m3-hmi-board/rtconfig.h b/bsp/renesas/ra6m3-hmi-board/rtconfig.h
index dfd1959641..d9cbc69663 100644
--- a/bsp/renesas/ra6m3-hmi-board/rtconfig.h
+++ b/bsp/renesas/ra6m3-hmi-board/rtconfig.h
@@ -27,7 +27,6 @@
#define RT_USING_DEBUG
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
-#define RT_DEBUGING_INIT
/* Inter-Thread communication */
@@ -85,11 +84,7 @@
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V2
#define RT_SERIAL_USING_DMA
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
#define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_PWM
/* Using USB */
@@ -113,17 +108,16 @@
/* Socket is in the 'Network' category */
-#define RT_USING_CPLUSPLUS
/* Network */
+/* Memory protection */
+
+
/* Utilities */
-/* Memory management */
-
-
/* RT-Thread Utestcases */
@@ -143,6 +137,12 @@
/* CYW43012 WiFi */
+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
/* IoT Cloud */
@@ -181,8 +181,6 @@
/* Micrium: Micrium software products porting for RT-Thread */
-#define PKG_USING_PERF_COUNTER
-#define PKG_USING_PERF_COUNTER_LATEST_VERSION
/* peripheral libraries and drivers */
@@ -213,14 +211,6 @@
/* Arduino libraries */
-#define PKG_USING_RTDUINO
-#define RTDUINO_THREAD_SIZE 2048
-#define RTDUINO_THREAD_PRIO 30
-#define RTDUINO_SUPPORT_HIGH_PRECISION_MICROS
-#define RTDUINO_USING_WIRE
-#define RTDUINO_WIRE_BUFFER_LENGTH 32
-#define RTDUINO_USING_SERVO
-#define PKG_USING_RTDUINO_LATEST_VERSION
/* Projects and Demos */
@@ -262,24 +252,14 @@
/* Onboard Peripheral Drivers */
-#define BSP_USING_ARDUINO
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
-#define BSP_USING_UART4
-#define BSP_UART4_RX_BUFSIZE 256
-#define BSP_UART4_TX_BUFSIZE 0
#define BSP_USING_UART9
#define BSP_UART9_RX_BUFSIZE 256
#define BSP_UART9_TX_BUFSIZE 0
-#define BSP_USING_I2C
-#define BSP_USING_ADC
-#define BSP_USING_ADC0
-#define BSP_USING_PWM
-#define BSP_USING_PWM2
-#define BSP_USING_PWM2_CH2
/* Board extended module Drivers */
diff --git a/bsp/renesas/ra6m4-cpk/README.md b/bsp/renesas/ra6m4-cpk/README.md
index bc0141bb1f..facf3401ad 100644
--- a/bsp/renesas/ra6m4-cpk/README.md
+++ b/bsp/renesas/ra6m4-cpk/README.md
@@ -168,6 +168,15 @@ void hal_entry(void)
3. 如何将 **”CPK-RA6M4板级支持包“**添加到 FSP 中,请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
4. 请查看文档:[使用 FSP 配置外设驱动](../docs/RA系列使用FSP配置外设驱动.md),在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
+目前仓库 bsp 默认使能最小体量配置,用户可通过如下步骤使能 env 外设配置:
+
+1. 在 bsp 目录下打开 env 工具,使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件,选择上方导航栏的 `Software Components`配置,打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮,该操作会自动查找当前电脑环境下安装的 fsp 版本,选择指定版本后进入 fsp。
+ ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现,已经存在了一些已经配置完成的外设,此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+ ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env,使能所需的外设配置后保存退出即可。
+
**ENV 配置**
- 如何使用 ENV 工具:[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
diff --git a/bsp/renesas/ra6m4-cpk/board/Kconfig b/bsp/renesas/ra6m4-cpk/board/Kconfig
index 308a32b680..c7f17e6cf8 100644
--- a/bsp/renesas/ra6m4-cpk/board/Kconfig
+++ b/bsp/renesas/ra6m4-cpk/board/Kconfig
@@ -8,11 +8,36 @@ menu "Hardware Drivers Config"
default y
menu "Onboard Peripheral Drivers"
- config BSP_USING_SEGGER_RTT_CONSOLE
- bool "Enable SEGGER-RTT for console"
- select PKG_USING_SEGGER_RTT
+
+ config BSP_USING_SEGGER_RTT_CONSOLE
+ bool "Enable SEGGER-RTT for console"
+ select PKG_USING_SEGGER_RTT
+ default n
+
+ config BSP_USING_SPI_LCD
+ bool "Enable SPI LCD"
+ select BSP_USING_GPIO
+ select BSP_USING_SPI
+ select BSP_USING_SPI1
default n
+ menuconfig BSP_USING_LVGL
+ bool "Enable LVGL for LCD"
+ select PKG_USING_LVGL
+ default n
+ if BSP_USING_LVGL
+ config BSP_USING_LCD_ILI9431
+ bool "Enable LVGL for LCD_ILI9431"
+ select PKG_USING_ILI9341
+ select BSP_USING_SPI_LCD
+ default n
+
+ config BSP_USING_LVGL_DEMO
+ bool "Enable LVGL demo"
+ select PKG_USING_LV_MUSIC_DEMO
+ default y
+ endif
+
endmenu
menu "On-chip Peripheral Drivers"
@@ -446,10 +471,24 @@ menu "Hardware Drivers Config"
select RT_LIBC_USING_FILEIO
select RT_USING_POSIX_DEVIO
if BSP_USING_SDHI
- config SDHI_USING_1_BIT
- bool "Use 1-bit Mode(4-bit when disable)"
- default y
- endif
+ menuconfig BSP_USING_SDHI0
+ bool "Enable SDHI0"
+ default n
+ if BSP_USING_SDHI0
+ config SDHI_USING_1_BIT
+ bool "Use 1-bit Mode(4-bit when disable)"
+ default y
+ endif
+
+ menuconfig BSP_USING_SDHI1
+ bool "Enable SDHI1"
+ default n
+ if BSP_USING_SDHI1
+ config SDHI_USING_1_BIT
+ bool "Use 1-bit Mode(4-bit when disable)"
+ default y
+ endif
+ endif
menuconfig BSP_USING_CAN
bool "Enable CAN"
@@ -465,32 +504,6 @@ menu "Hardware Drivers Config"
default n
endif
- config BSP_USING_SPI_LCD
- bool "Enable SPI LCD"
- select BSP_USING_GPIO
- select BSP_USING_SPI
- select BSP_USING_SPI1
- default n
-
- menuconfig BSP_USING_LVGL
- bool "Enable LVGL for LCD"
- select PKG_USING_LVGL
- default n
- if BSP_USING_LVGL
- config BSP_USING_LCD_ILI9431
- bool "Enable LVGL for LCD_ILI9431"
- select PKG_USING_ILI9341
- select BSP_USING_SPI_LCD
- default n
- endif
-
- if BSP_USING_LVGL
- config BSP_USING_LVGL_DEMO
- bool "Enable LVGL demo"
- select PKG_USING_LV_MUSIC_DEMO
- default y
- endif
-
endmenu
menu "Board extended module Drivers"
diff --git a/bsp/renesas/ra6m4-iot/README.md b/bsp/renesas/ra6m4-iot/README.md
index 5dbc72639b..8e31ab83d8 100644
--- a/bsp/renesas/ra6m4-iot/README.md
+++ b/bsp/renesas/ra6m4-iot/README.md
@@ -155,6 +155,15 @@ void hal_entry(void)
3. 如何将 **”IOT-RA6M4 板级支持包“**添加到 FSP 中,请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
4. 请查看文档:[使用瑞萨 FSP 配置工具](../docs/RA系列使用FSP配置外设驱动.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
+目前仓库 bsp 默认使能最小体量配置,用户可通过如下步骤使能 env 外设配置:
+
+1. 在 bsp 目录下打开 env 工具,使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件,选择上方导航栏的 `Software Components`配置,打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮,该操作会自动查找当前电脑环境下安装的 fsp 版本,选择指定版本后进入 fsp。
+ ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现,已经存在了一些已经配置完成的外设,此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+ ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env,使能所需的外设配置后保存退出即可。
+
**ENV 配置**
- 如何使用 ENV 工具:[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
@@ -167,7 +176,6 @@ void hal_entry(void)
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
-
## FAQ
### 使用 MDK 的 DEBUG 时如果遇到提示 “Error: Flash Download failed Cortex-M33” 怎么办?
diff --git a/bsp/renesas/ra6m4-iot/board/Kconfig b/bsp/renesas/ra6m4-iot/board/Kconfig
index 8fcf428d6c..709d626b68 100644
--- a/bsp/renesas/ra6m4-iot/board/Kconfig
+++ b/bsp/renesas/ra6m4-iot/board/Kconfig
@@ -425,10 +425,24 @@ menu "Hardware Drivers Config"
select RT_LIBC_USING_FILEIO
select RT_USING_POSIX_DEVIO
if BSP_USING_SDHI
- config SDHI_USING_1_BIT
- bool "Use 1-bit Mode(4-bit when disable)"
- default y
- endif
+ menuconfig BSP_USING_SDHI0
+ bool "Enable SDHI0"
+ default n
+ if BSP_USING_SDHI0
+ config SDHI_USING_1_BIT
+ bool "Use 1-bit Mode(4-bit when disable)"
+ default y
+ endif
+
+ menuconfig BSP_USING_SDHI1
+ bool "Enable SDHI1"
+ default n
+ if BSP_USING_SDHI1
+ config SDHI_USING_1_BIT
+ bool "Use 1-bit Mode(4-bit when disable)"
+ default y
+ endif
+ endif
menuconfig BSP_USING_CAN
bool "Enable CAN"
diff --git a/bsp/renesas/ra8d1-ek/.config b/bsp/renesas/ra8d1-ek/.config
index cb796468ff..bc43e16064 100644
--- a/bsp/renesas/ra8d1-ek/.config
+++ b/bsp/renesas/ra8d1-ek/.config
@@ -22,6 +22,7 @@ CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
@@ -73,6 +74,7 @@ CONFIG_RT_USING_HEAP=y
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREDSAFE_PRINTF is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart9"
@@ -117,16 +119,6 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
# DFS: device virtual file system
#
# CONFIG_RT_USING_DFS is not set
-# CONFIG_RT_USING_DFS_V1 is not set
-# CONFIG_RT_USING_DFS_V2 is not set
-# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
-# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
-# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
-# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
-# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set
-# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
-# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
-# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
# CONFIG_RT_USING_FAL is not set
#
@@ -283,6 +275,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
@@ -304,7 +311,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
-# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@@ -325,6 +331,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
+# CONFIG_PKG_USING_CYW43XX is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
@@ -344,6 +352,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set
#
# security packages
@@ -390,7 +400,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
@@ -465,6 +474,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
#
# system packages
@@ -501,6 +511,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
@@ -524,6 +536,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
@@ -537,6 +550,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set
#
# peripheral libraries and drivers
@@ -601,6 +619,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
@@ -701,6 +720,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_FINGERPRINT is not set
# CONFIG_PKG_USING_BT_ECB02C is not set
# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
+# CONFIG_PKG_USING_BT_MX01 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
#
@@ -715,6 +739,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set
#
# Signal Processing and Control Algorithm Packages
@@ -724,6 +749,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
#
# miscellaneous packages
@@ -755,12 +781,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_TINYSQUARE is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
@@ -798,6 +826,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
@@ -805,13 +834,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
-# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
-# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
@@ -856,7 +885,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
-# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
@@ -895,7 +924,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
-# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
@@ -918,7 +946,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
-# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
@@ -926,7 +954,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
-# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
@@ -939,12 +967,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
@@ -953,6 +983,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# Timing
#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
# CONFIG_PKG_USING_ARDUINO_TICKER is not set
# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
@@ -978,18 +1009,17 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
-# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
-# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@@ -1019,6 +1049,12 @@ CONFIG_SOC_SERIES_R7FA8M85=y
#
CONFIG_SOC_R7FA8D1AH=y
+#
+# Onboard Peripheral Drivers
+#
+# CONFIG_BSP_USING_FS is not set
+# CONFIG_BSP_USING_LVGL is not set
+
#
# On-chip Peripheral Drivers
#
@@ -1037,14 +1073,11 @@ CONFIG_BSP_UART9_TX_BUFSIZE=0
# CONFIG_BSP_USING_SCI is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C is not set
-# CONFIG_BSP_USING_FS is not set
# CONFIG_BSP_USING_SDHI is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_LCD is not set
-CONFIG_BSP_USING_SDRAM=y
-CONFIG_BSP_USING_SDRAM_SIZE=0x8000000
+# CONFIG_BSP_USING_SDRAM is not set
# CONFIG_BSP_USING_G2D is not set
# CONFIG_BSP_USING_JPEG is not set
# CONFIG_BSP_USING_ETH is not set
-# CONFIG_BSP_USING_LVGL is not set
diff --git a/bsp/renesas/ra8d1-ek/README.md b/bsp/renesas/ra8d1-ek/README.md
index 742bb9afbf..e5304a82f7 100644
--- a/bsp/renesas/ra8d1-ek/README.md
+++ b/bsp/renesas/ra8d1-ek/README.md
@@ -167,6 +167,19 @@ void hal_entry(void)
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
+**FSP配置**
+
+* 如何使用 FSP:[RA系列使用 FSP 配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)
+
+目前仓库 bsp 默认使能最小体量配置,用户可通过如下步骤使能 env 外设配置:
+
+1. 在 bsp 目录下打开 env 工具,使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件,选择上方导航栏的 `Software Components`配置,打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮,该操作会自动查找当前电脑环境下安装的 fsp 版本,选择指定版本后进入 fsp。
+ ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现,已经存在了一些已经配置完成的外设,此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+ ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env,使能所需的外设配置后保存退出即可。
+
## 联系人信息
在使用过程中若您有任何的想法和建议,建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
diff --git a/bsp/renesas/ra8d1-ek/README_EN.md b/bsp/renesas/ra8d1-ek/README_EN.md
index f4bca06975..326bf88c50 100644
--- a/bsp/renesas/ra8d1-ek/README_EN.md
+++ b/bsp/renesas/ra8d1-ek/README_EN.md
@@ -138,6 +138,19 @@ The steps are as follows:
3. Enter the `pkgs --update` command to update the software package.
4. Enter the `scons --target=mdk5` command to regenerate the project.
+**FSP Configuration**
+
+* How to Use FSP: [Configuring Peripheral Drivers for RA Series Using FSP](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)
+
+The current repository's BSP is configured with the minimum footprint enabled by default. Users can enable peripheral configurations through the following steps:
+
+1. Open the `env` tool in the BSP directory and use the `scons --target=mdk5` command to generate an MDK project.
+2. Open the `project.uvprojx` file in the BSP directory, select the `Software Components` configuration in the top navigation bar, and open the configuration button next to `RA Configuration` under `Flex Software`. This operation will automatically detect the installed FSP version on the current computer. After selecting the specified version, enter FSP.
+ ![](../docs/figures/mdk_rasc.png)
+3. Upon entering FSP, pre-configured peripherals are already present. Click the `Generate Project Content` button to generate the required driver files.
+ ![](../docs/figures/fsp_configure.png)
+4. Return to `env`, enable the necessary peripheral configurations, save, and exit.
+
## Contribute the Code
If you’re interested in the EK-RA8D1 and have some cool projects you’d like to share with everyone, we’d love for you to contribute your code! You can check out [how to contribute to RT-Thread’s code](https://www.rt-thread.io/contribution.html). Let’s make something awesome together!
\ No newline at end of file
diff --git a/bsp/renesas/ra8d1-ek/board/Kconfig b/bsp/renesas/ra8d1-ek/board/Kconfig
index 531186b99d..e2ce5bef45 100644
--- a/bsp/renesas/ra8d1-ek/board/Kconfig
+++ b/bsp/renesas/ra8d1-ek/board/Kconfig
@@ -7,6 +7,47 @@ menu "Hardware Drivers Config"
select RT_USING_USER_MAIN
default y
+ menu "Onboard Peripheral Drivers"
+
+ menuconfig BSP_USING_FS
+ bool "Enable filesystem"
+ default n
+ if BSP_USING_FS
+ config BSP_USING_ONCHIP_FS
+ bool "Enable ONCHIP filesystem"
+ select RT_USING_FAL
+ select RT_USING_DFS_ELMFAT
+ select RT_USING_MTD_NOR
+ select BSP_USING_ONCHIP_FLASH
+ default n
+ config BSP_USING_SDCARD_FS
+ bool "Enable SDCARD filesystem"
+ select BSP_USING_SDHI
+ select BSP_USING_SDHI1
+ select RT_USING_DFS_ELMFAT
+ default n
+ config BSP_USING_SPICARD_FS
+ bool "Enable SPI FLASH filesystem"
+ select BSP_USING_SCI_SPI
+ select BSP_USING_SCI_SPI2
+ select RT_USING_SPI_MSD
+ select RT_USING_DFS_ELMFAT
+ default n
+ endif
+
+ menuconfig BSP_USING_LVGL
+ bool "Enable LVGL for LCD"
+ select PKG_USING_LVGL
+ default n
+ if BSP_USING_LVGL
+ config BSP_USING_LCD_RGB
+ bool "Enable LVGL for LCD_RGB565"
+ select BSP_USING_LCD
+ default n
+ endif
+
+ endmenu
+
menu "On-chip Peripheral Drivers"
source "../libraries/HAL_Drivers/Kconfig"
@@ -473,31 +514,6 @@ menu "Hardware Drivers Config"
endif
endif
- menuconfig BSP_USING_FS
- bool "Enable filesystem"
- default n
- if BSP_USING_FS
- config BSP_USING_ONCHIP_FS
- bool "Enable ONCHIP filesystem"
- select RT_USING_FAL
- select RT_USING_DFS_ELMFAT
- select RT_USING_MTD_NOR
- select BSP_USING_ONCHIP_FLASH
- default n
- config BSP_USING_SDCARD_FS
- bool "Enable SDCARD filesystem"
- select BSP_USING_SDHI
- select RT_USING_DFS_ELMFAT
- default n
- config BSP_USING_SPICARD_FS
- bool "Enable SPI FLASH filesystem"
- select BSP_USING_SCI_SPI
- select BSP_USING_SCI_SPI2
- select RT_USING_SPI_MSD
- select RT_USING_DFS_ELMFAT
- default n
- endif
-
menuconfig BSP_USING_SDHI
bool "Enable SDHI"
default n
@@ -506,10 +522,24 @@ menu "Hardware Drivers Config"
select RT_LIBC_USING_FILEIO
select RT_USING_POSIX_DEVIO
if BSP_USING_SDHI
- config SDHI_USING_1_BIT
- bool "Use 1-bit Mode(4-bit when disable)"
- default y
- endif
+ menuconfig BSP_USING_SDHI0
+ bool "Enable SDHI0"
+ default n
+ if BSP_USING_SDHI0
+ config SDHI_USING_1_BIT
+ bool "Use 1-bit Mode(4-bit when disable)"
+ default y
+ endif
+
+ menuconfig BSP_USING_SDHI1
+ bool "Enable SDHI1"
+ default n
+ if BSP_USING_SDHI1
+ config SDHI_USING_1_BIT
+ bool "Use 1-bit Mode(4-bit when disable)"
+ default y
+ endif
+ endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
@@ -566,16 +596,5 @@ menu "Hardware Drivers Config"
select RT_USING_LWIP
select RT_USING_NETDEV
default n
-
- menuconfig BSP_USING_LVGL
- bool "Enable LVGL for LCD"
- select PKG_USING_LVGL
- default n
- if BSP_USING_LVGL
- config BSP_USING_LCD_RGB
- bool "Enable LVGL for LCD_RGB565"
- select BSP_USING_LCD
- default n
- endif
endmenu
endmenu
diff --git a/bsp/renesas/ra8d1-ek/ra/SConscript b/bsp/renesas/ra8d1-ek/ra/SConscript
index 52e96ac900..294776d305 100644
--- a/bsp/renesas/ra8d1-ek/ra/SConscript
+++ b/bsp/renesas/ra8d1-ek/ra/SConscript
@@ -22,5 +22,9 @@ elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
+if GetDepend('BSP_USING_G2D'):
+ src += Glob(cwd + '/tes/dave2d/src/*.c')
+ CPPPATH += [cwd + '/tes/dave2d/inc']
+
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
diff --git a/bsp/renesas/ra8d1-ek/rtconfig.h b/bsp/renesas/ra8d1-ek/rtconfig.h
index 3a11c24175..2745a13091 100644
--- a/bsp/renesas/ra8d1-ek/rtconfig.h
+++ b/bsp/renesas/ra8d1-ek/rtconfig.h
@@ -137,6 +137,15 @@
/* Wiced WiFi */
+/* CYW43012 WiFi */
+
+
+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
/* IoT Cloud */
@@ -244,6 +253,9 @@
#define SOC_R7FA8D1AH
+/* Onboard Peripheral Drivers */
+
+
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
@@ -251,7 +263,5 @@
#define BSP_USING_UART9
#define BSP_UART9_RX_BUFSIZE 256
#define BSP_UART9_TX_BUFSIZE 0
-#define BSP_USING_SDRAM
-#define BSP_USING_SDRAM_SIZE 0x8000000
#endif
diff --git a/bsp/renesas/ra8m1-ek/README.md b/bsp/renesas/ra8m1-ek/README.md
index d65b45e491..23e4d0c7c2 100644
--- a/bsp/renesas/ra8m1-ek/README.md
+++ b/bsp/renesas/ra8m1-ek/README.md
@@ -167,6 +167,19 @@ void hal_entry(void)
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
+**FSP配置**
+
+* 如何使用 FSP:[RA系列使用 FSP 配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)
+
+目前仓库 bsp 默认使能最小体量配置,用户可通过如下步骤使能 env 外设配置:
+
+1. 在 bsp 目录下打开 env 工具,使用 `scons --target=mdk5`命令生成 MDK 工程。
+2. 打开 bsp 目录下的`project.uvprojx`文件,选择上方导航栏的 `Software Components`配置,打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮,该操作会自动查找当前电脑环境下安装的 fsp 版本,选择指定版本后进入 fsp。
+ ![](../docs/figures/mdk_rasc.png)
+3. 在进入 fsp 后我们可以发现,已经存在了一些已经配置完成的外设,此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
+ ![](../docs/figures/fsp_configure.png)
+4. 接下来回到 env,使能所需的外设配置后保存退出即可。
+
## 联系人信息
在使用过程中若您有任何的想法和建议,建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
diff --git a/bsp/renesas/ra8m1-ek/README_EN.md b/bsp/renesas/ra8m1-ek/README_EN.md
index 44e5570713..fab3d5c88e 100644
--- a/bsp/renesas/ra8m1-ek/README_EN.md
+++ b/bsp/renesas/ra8m1-ek/README_EN.md
@@ -127,6 +127,19 @@ The steps are as follows:
3. Enter the `pkgs --update` command to update the software package.
4. Enter the `scons --target=mdk5` command to regenerate the project.
+**FSP Configuration**
+
+* How to Use FSP: [Configuring Peripheral Drivers for RA Series Using FSP](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)
+
+The current repository's BSP is configured with the minimum footprint enabled by default. Users can enable peripheral configurations through the following steps:
+
+1. Open the `env` tool in the BSP directory and use the `scons --target=mdk5` command to generate an MDK project.
+2. Open the `project.uvprojx` file in the BSP directory, select the `Software Components` configuration in the top navigation bar, and open the configuration button next to `RA Configuration` under `Flex Software`. This operation will automatically detect the installed FSP version on the current computer. After selecting the specified version, enter FSP.
+ ![](../docs/figures/mdk_rasc.png)
+3. Upon entering FSP, pre-configured peripherals are already present. Click the `Generate Project Content` button to generate the required driver files.
+ ![](../docs/figures/fsp_configure.png)
+4. Return to `env`, enable the necessary peripheral configurations, save, and exit.
+
## Contribute the Code
If you’re interested in the EK-RA8M1 and have some cool projects you’d like to share with everyone, we’d love for you to contribute your code! You can check out [how to contribute to RT-Thread’s code](https://www.rt-thread.io/contribution.html). Let’s make something awesome together!
\ No newline at end of file
diff --git a/bsp/renesas/ra8m1-ek/board/Kconfig b/bsp/renesas/ra8m1-ek/board/Kconfig
index af5784d1f5..e8142ff363 100644
--- a/bsp/renesas/ra8m1-ek/board/Kconfig
+++ b/bsp/renesas/ra8m1-ek/board/Kconfig
@@ -9,6 +9,19 @@ menu "Hardware Drivers Config"
menu "Onboard Peripheral Drivers"
+ menuconfig BSP_USING_FS
+ bool "Enable filesystem"
+ default n
+ if BSP_USING_FS
+ config BSP_USING_SPICARD_FS
+ bool "Enable SPI FLASH filesystem"
+ select BSP_USING_SPI
+ select BSP_USING_SCI_SPI6
+ select RT_USING_SPI_MSD
+ select RT_USING_DFS_ELMFAT
+ default n
+ endif
+
endmenu
menu "On-chip Peripheral Drivers"
@@ -495,18 +508,6 @@ menu "Hardware Drivers Config"
bool "Enable DAC0"
default n
endif
- menuconfig BSP_USING_FS
- bool "Enable filesystem"
- default n
- if BSP_USING_FS
- config BSP_USING_SPICARD_FS
- bool "Enable SPI FLASH filesystem"
- select BSP_USING_SPI
- select BSP_USING_SCI_SPI6
- select RT_USING_SPI_MSD
- select RT_USING_DFS_ELMFAT
- default n
- endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
diff --git a/bsp/renesas/tools/startup_check.py b/bsp/renesas/tools/startup_check.py
index 0cf1e4f38b..94f4a012b8 100644
--- a/bsp/renesas/tools/startup_check.py
+++ b/bsp/renesas/tools/startup_check.py
@@ -2,9 +2,6 @@ import subprocess
import sys
import os
-# cwd_path = os.getcwd()
-# sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
-
def check_git_exists():
try:
# Check if Git is installed
@@ -43,7 +40,7 @@ def revert_to_original(filepath):
subprocess.call(["git", "checkout", filepath])
def startup_check():
- file_path = os.getcwd() + f"/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"
+ file_path = os.getcwd() + "/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"
python_executable = 'python' if sys.version_info[0] == 2 else 'python3'
# Check if Git is installed, if not, try to install it